; -------------------------------------------------------------------------------- ; @Title: Kinetis K70 On-Chip Peripherals ; @Props: Released ; @Author: KRW, KAP, KAO, PBU, ZUO, BCA, MTR, KWI ; @Changelog: 2014-01-22 KAP ; 2014-11-20 KAO ; 2015-08-25 ZUO ; 2017-10-11 BCA ; 2018-02-15 KWI ; @Manufacturer: NXP - NXP Semiconductors ; @Doc: K70P256M150SF3RM.pdf (Rev.2, 2011-12) ; K70P256M150SF3RM.pdf (Rev.3, 2014-11) ; K70P256M150SF3RM.pdf (Rev.4, 2015-10) ; @Core: Cortex-M4 ; @Chip: MK70FX512VMJ12, MK70FN1M0VMJ12, MK70FN1M0VMJ12R, MK70FN1M0VMJ15R, ; MK70FX512VMJ15, MK70FN1M0VMJ15 ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perk70.per 17653 2024-03-20 16:44:46Z kwisniewski $ tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end config 16. 8. tree.open "PORT (Pin control and interrupts)" tree "PORTA" base ad:0x40049000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT A Pin Control Registers" ; 0x0 - adres ; A - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTA_PCR_0,PORTA Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; A - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTA_PCR_1,PORTA Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; A - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTA_PCR_2,PORTA Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; A - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTA_PCR_3,PORTA Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; A - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTA_PCR_4,PORTA Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; A - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTA_PCR_5,PORTA Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; A - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTA_PCR_6,PORTA Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; A - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTA_PCR_7,PORTA Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; A - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTA_PCR_8,PORTA Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; A - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTA_PCR_9,PORTA Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; A - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTA_PCR_10,PORTA Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; A - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTA_PCR_11,PORTA Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; A - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTA_PCR_12,PORTA Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; A - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTA_PCR_13,PORTA Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; A - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTA_PCR_14,PORTA Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; A - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTA_PCR_15,PORTA Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; A - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTA_PCR_16,PORTA Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; A - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTA_PCR_17,PORTA Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; A - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTA_PCR_18,PORTA Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; A - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTA_PCR_19,PORTA Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x60 - adres ; A - litera portu (A,B,C,...) ; 24 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(24>=1)&&(24<=5)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(24>=1)&&(24<=4)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==5)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTA_PCR_24,PORTA Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x64 - adres ; A - litera portu (A,B,C,...) ; 25 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(25>=1)&&(25<=5)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(25>=1)&&(25<=4)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==5)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTA_PCR_25,PORTA Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x68 - adres ; A - litera portu (A,B,C,...) ; 26 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(26>=1)&&(26<=5)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(26>=1)&&(26<=4)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==5)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTA_PCR_26,PORTA Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x6C - adres ; A - litera portu (A,B,C,...) ; 27 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(27>=1)&&(27<=5)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(27>=1)&&(27<=4)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==5)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTA_PCR_27,PORTA Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x70 - adres ; A - litera portu (A,B,C,...) ; 28 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(28>=1)&&(28<=5)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(28>=1)&&(28<=4)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==5)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTA_PCR_28,PORTA Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x74 - adres ; A - litera portu (A,B,C,...) ; 29 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('A'=='A')&&(29>=1)&&(29<=5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('A'=='A')&&(29>=1)&&(29<=4)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==5)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('A'=='A')&&(29==0)) group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x74++0x03 line.long 0x00 "PORTA_PCR_29,PORTA Pin Control Register 29" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x7 line.long 0x00 "PORTA_GPCLR,PORTA Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable" textline " " bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" textline " " bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" textline " " bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTA_GPCHR,PORTA Global Pin Control High Register" bitfld.long 0x04 29. " GPWE29 ,Global pin 29 write enable" "Disable,Enable" bitfld.long 0x04 28. " GPWE28 ,Global pin 28 write enable" "Disable,Enable" textline " " bitfld.long 0x04 27. " GPWE27 ,Global Pin 27 write enable" "Disable,Enable" bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable" bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable" bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable" textline " " bitfld.long 0x04 19. " GPWE19 ,Global Pin 19 write enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable" textline " " hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTA_ISFR,PORTA Interrupt Status Flag Register" eventfld.long 0x00 29. " ISF29 ,Interrupt status flag 29" "No interrupt,Interrupt" eventfld.long 0x00 28. " ISF28 ,Interrupt status flag 28" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " ISF27 ,Interrupt status flag 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26" "No interrupt,Interrupt" eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x03 line.long 0x00 "PORTA_DFER,Digital Filter Enable Register" bitfld.long 0x00 29. " DFE29 ,Digital filter enable 29" "Disabled,Enabled" bitfld.long 0x00 28. " DFE28 ,Digital filter enable 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " DFE27 ,Digital filter enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DFE26 ,Digital filter enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DFE25 ,Digital filter enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DFE24 ,Digital filter enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DFE19 ,Pin 19 Digital filter enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital filter enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital filter enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DFE15 ,Digital filter enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DFE14 ,Digital filter enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DFE13 ,Digital filter enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DFE12 ,Digital filter enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" rgroup.long 0xC4++0x07 line.long 0x00 "PORTA_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x04 "PORTA_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree "PORTB" base ad:0x4004a000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT B Pin Control Registers" ; 0x0 - adres ; B - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTB_PCR_0,PORTB Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; B - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTB_PCR_1,PORTB Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; B - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTB_PCR_2,PORTB Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; B - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTB_PCR_3,PORTB Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; B - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTB_PCR_4,PORTB Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; B - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTB_PCR_5,PORTB Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; B - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTB_PCR_6,PORTB Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; B - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTB_PCR_7,PORTB Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; B - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTB_PCR_8,PORTB Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; B - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTB_PCR_9,PORTB Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; B - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTB_PCR_10,PORTB Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; B - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTB_PCR_11,PORTB Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; B - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTB_PCR_16,PORTB Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; B - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTB_PCR_17,PORTB Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; B - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTB_PCR_18,PORTB Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; B - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTB_PCR_19,PORTB Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x50 - adres ; B - litera portu (A,B,C,...) ; 20 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(20>=1)&&(20<=5)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(20>=1)&&(20<=4)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==5)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTB_PCR_20,PORTB Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x54 - adres ; B - litera portu (A,B,C,...) ; 21 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(21>=1)&&(21<=5)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(21>=1)&&(21<=4)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==5)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTB_PCR_21,PORTB Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x58 - adres ; B - litera portu (A,B,C,...) ; 22 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(22>=1)&&(22<=5)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(22>=1)&&(22<=4)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==5)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTB_PCR_22,PORTB Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x5C - adres ; B - litera portu (A,B,C,...) ; 23 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('B'=='A')&&(23>=1)&&(23<=5)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('B'=='A')&&(23>=1)&&(23<=4)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==5)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('B'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTB_PCR_23,PORTB Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x7 line.long 0x00 "PORTB_GPCLR,PORTB Global Pin Control Low Register" bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" textline " " bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" textline " " bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPwd ,global pin write Data" line.long 0x04 "PORTB_GPCHR,PORTB Global Pin control high register" bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable" bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable" bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable" bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable" textline " " bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable" textline " " hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTB_ISFR,PORTB Interrupt Status Flag Register" eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23" "No interrupt,Interrupt" eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x03 line.long 0x00 "PORTB_DFER,Digital Filter Enable Register" bitfld.long 0x00 23. " DFE23 ,Digital filter enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DFE22 ,Digital filter enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DFE21 ,Digital filter enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DFE20 ,Digital filter enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DFE19 ,Pin 19 Digital filter enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital filter enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital filter enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" rgroup.long 0xC4++0x07 line.long 0x00 "PORTB_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x04 "PORTB_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree "PORTC" base ad:0x4004b000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT C Pin Control Registers" ; 0x0 - adres ; C - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTC_PCR_0,PORTC Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; C - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTC_PCR_1,PORTC Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; C - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTC_PCR_2,PORTC Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; C - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTC_PCR_3,PORTC Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; C - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTC_PCR_4,PORTC Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; C - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTC_PCR_5,PORTC Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; C - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTC_PCR_6,PORTC Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; C - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTC_PCR_7,PORTC Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; C - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTC_PCR_8,PORTC Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; C - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTC_PCR_9,PORTC Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; C - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTC_PCR_10,PORTC Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; C - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTC_PCR_11,PORTC Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; C - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTC_PCR_12,PORTC Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; C - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTC_PCR_13,PORTC Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; C - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTC_PCR_14,PORTC Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; C - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTC_PCR_15,PORTC Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; C - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTC_PCR_16,PORTC Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; C - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTC_PCR_17,PORTC Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; C - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTC_PCR_18,PORTC Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; C - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('C'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('C'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('C'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTC_PCR_19,PORTC Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTC_GPCLR,PORTC Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable" textline " " bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" textline " " bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" textline " " bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPwd ,global pin write Data" line.long 0x04 "PORTC_GPCHR,PORTC Global Pin control high register" bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable" textline " " hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTC_ISFR,PORTC Interrupt Status Flag Register" eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x03 line.long 0x00 "PORTC_DFER,Digital Filter Enable Register" bitfld.long 0x00 19. " DFE19 ,Pin 19 Digital filter enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital filter enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital filter enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DFE15 ,Digital filter enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DFE14 ,Digital filter enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DFE13 ,Digital filter enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DFE12 ,Digital filter enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" rgroup.long 0xC4++0x07 line.long 0x00 "PORTC_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x04 "PORTC_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree "PORTD" base ad:0x4004c000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT D Pin Control Registers" ; 0x0 - adres ; D - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTD_PCR_0,PORTD Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; D - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTD_PCR_1,PORTD Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; D - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTD_PCR_2,PORTD Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; D - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTD_PCR_3,PORTD Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; D - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTD_PCR_4,PORTD Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; D - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTD_PCR_5,PORTD Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; D - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTD_PCR_6,PORTD Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; D - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTD_PCR_7,PORTD Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; D - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTD_PCR_8,PORTD Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; D - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTD_PCR_9,PORTD Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; D - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTD_PCR_10,PORTD Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; D - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTD_PCR_11,PORTD Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; D - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTD_PCR_12,PORTD Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; D - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTD_PCR_13,PORTD Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; D - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTD_PCR_14,PORTD Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; D - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('D'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('D'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('D'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTD_PCR_15,PORTD Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x07 line.long 0x00 "PORTD_GPCLR,PORTD Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable" textline " " bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" textline " " bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" textline " " bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTD_ISFR,PORTD Interrupt Status Flag Register" eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x03 line.long 0x00 "PORTD_DFER,Digital Filter Enable Register" bitfld.long 0x00 15. " DFE15 ,Digital filter enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DFE14 ,Digital filter enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DFE13 ,Digital filter enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DFE12 ,Digital filter enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" rgroup.long 0xC4++0x07 line.long 0x00 "PORTD_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x04 "PORTD_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree "PORTE" base ad:0x4004d000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT E Pin Control Registers" ; 0x0 - adres ; E - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; E - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; E - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; E - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; E - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; E - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; E - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; E - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; E - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; E - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; E - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; E - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; E - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; E - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; E - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; E - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; E - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x60 - adres ; E - litera portu (A,B,C,...) ; 24 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(24>=1)&&(24<=5)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(24>=1)&&(24<=4)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==5)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x64 - adres ; E - litera portu (A,B,C,...) ; 25 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(25>=1)&&(25<=5)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(25>=1)&&(25<=4)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==5)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x68 - adres ; E - litera portu (A,B,C,...) ; 26 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(26>=1)&&(26<=5)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(26>=1)&&(26<=4)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==5)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x6C - adres ; E - litera portu (A,B,C,...) ; 27 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(27>=1)&&(27<=5)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(27>=1)&&(27<=4)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==5)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x70 - adres ; E - litera portu (A,B,C,...) ; 28 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(28>=1)&&(28<=5)) group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(28>=1)&&(28<=4)) group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(28==5)) group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(28==0)) group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x70++0x03 line.long 0x00 "PORTE_PCR_28,PORTE Pin Control Register 28" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x7 line.long 0x00 "PORTE_GPCLR,PORTE Global Pin Control Low Register" bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable" bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" textline " " bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" textline " " bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" textline " " bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTE_GPCHR,PORTE Global Pin Control High Register" bitfld.long 0x04 28. " GPWE28 ,Global pin 28 write enable" "Disable,Enable" bitfld.long 0x04 27. " GPWE27 ,Global pin 27 write enable" "Disable,Enable" bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable" bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable" textline " " bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable" bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable" textline " " bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable" textline " " hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTE_ISFR,PORTE Interrupt Status Flag Register" eventfld.long 0x00 28. " ISF28 ,Interrupt status flag 28" "No interrupt,Interrupt" eventfld.long 0x00 27. " ISF27 ,Interrupt status flag 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26" "No interrupt,Interrupt" eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25" "No interrupt,Interrupt" textline " " eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24" "No interrupt,Interrupt" eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17" "No interrupt,Interrupt" textline " " eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x03 line.long 0x00 "PORTE_DFER,Digital Filter Enable Register" bitfld.long 0x00 28. " DFE28 ,Digital filter enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " DFE27 ,Digital filter enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DFE26 ,Digital filter enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DFE25 ,Digital filter enable 25" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " DFE24 ,Digital filter enable 24" "Disabled,Enabled" bitfld.long 0x00 19. " DFE19 ,Pin 19 Digital filter enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital filter enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DFE16 ,Digital filter enable 16" "Disabled,Enabled" bitfld.long 0x00 12. " DFE12 ,Digital filter enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" rgroup.long 0xC4++0x07 line.long 0x00 "PORTE_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x04 "PORTE_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree "PORTF" base ad:0x4004e000 width 13. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15") tree "PORT F Pin Control Registers" ; 0x0 - adres ; E - litera portu (A,B,C,...) ; 0 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(0>=1)&&(0<=5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(0>=1)&&(0<=4)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==5)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(0==0)) group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x0++0x03 line.long 0x00 "PORTE_PCR_0,PORTE Pin Control Register 0" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4 - adres ; E - litera portu (A,B,C,...) ; 1 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(1>=1)&&(1<=5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(1>=1)&&(1<=4)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==5)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(1==0)) group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4++0x03 line.long 0x00 "PORTE_PCR_1,PORTE Pin Control Register 1" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x8 - adres ; E - litera portu (A,B,C,...) ; 2 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(2>=1)&&(2<=5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(2>=1)&&(2<=4)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==5)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(2==0)) group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x8++0x03 line.long 0x00 "PORTE_PCR_2,PORTE Pin Control Register 2" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0xC - adres ; E - litera portu (A,B,C,...) ; 3 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(3>=1)&&(3<=5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(3>=1)&&(3<=4)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==5)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(3==0)) group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0xC++0x03 line.long 0x00 "PORTE_PCR_3,PORTE Pin Control Register 3" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x10 - adres ; E - litera portu (A,B,C,...) ; 4 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(4>=1)&&(4<=5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(4>=1)&&(4<=4)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==5)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(4==0)) group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x10++0x03 line.long 0x00 "PORTE_PCR_4,PORTE Pin Control Register 4" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x14 - adres ; E - litera portu (A,B,C,...) ; 5 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(5>=1)&&(5<=5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(5>=1)&&(5<=4)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==5)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(5==0)) group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x14++0x03 line.long 0x00 "PORTE_PCR_5,PORTE Pin Control Register 5" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x18 - adres ; E - litera portu (A,B,C,...) ; 6 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(6>=1)&&(6<=5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(6>=1)&&(6<=4)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==5)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(6==0)) group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x18++0x03 line.long 0x00 "PORTE_PCR_6,PORTE Pin Control Register 6" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x1C - adres ; E - litera portu (A,B,C,...) ; 7 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(7>=1)&&(7<=5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(7>=1)&&(7<=4)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==5)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(7==0)) group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x1C++0x03 line.long 0x00 "PORTE_PCR_7,PORTE Pin Control Register 7" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x20 - adres ; E - litera portu (A,B,C,...) ; 8 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(8>=1)&&(8<=5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(8>=1)&&(8<=4)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==5)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(8==0)) group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x20++0x03 line.long 0x00 "PORTE_PCR_8,PORTE Pin Control Register 8" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x24 - adres ; E - litera portu (A,B,C,...) ; 9 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(9>=1)&&(9<=5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(9>=1)&&(9<=4)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==5)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(9==0)) group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x24++0x03 line.long 0x00 "PORTE_PCR_9,PORTE Pin Control Register 9" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x28 - adres ; E - litera portu (A,B,C,...) ; 10 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(10>=1)&&(10<=5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(10>=1)&&(10<=4)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==5)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(10==0)) group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x28++0x03 line.long 0x00 "PORTE_PCR_10,PORTE Pin Control Register 10" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x2C - adres ; E - litera portu (A,B,C,...) ; 11 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(11>=1)&&(11<=5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(11>=1)&&(11<=4)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==5)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(11==0)) group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x2C++0x03 line.long 0x00 "PORTE_PCR_11,PORTE Pin Control Register 11" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x30 - adres ; E - litera portu (A,B,C,...) ; 12 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(12>=1)&&(12<=5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(12>=1)&&(12<=4)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==5)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(12==0)) group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x30++0x03 line.long 0x00 "PORTE_PCR_12,PORTE Pin Control Register 12" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x34 - adres ; E - litera portu (A,B,C,...) ; 13 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(13>=1)&&(13<=5)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(13>=1)&&(13<=4)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==5)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(13==0)) group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x34++0x03 line.long 0x00 "PORTE_PCR_13,PORTE Pin Control Register 13" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x38 - adres ; E - litera portu (A,B,C,...) ; 14 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(14>=1)&&(14<=5)) group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(14>=1)&&(14<=4)) group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(14==5)) group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(14==0)) group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x38++0x03 line.long 0x00 "PORTE_PCR_14,PORTE Pin Control Register 14" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x3C - adres ; E - litera portu (A,B,C,...) ; 15 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(15>=1)&&(15<=5)) group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(15>=1)&&(15<=4)) group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(15==5)) group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(15==0)) group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x3C++0x03 line.long 0x00 "PORTE_PCR_15,PORTE Pin Control Register 15" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x40 - adres ; E - litera portu (A,B,C,...) ; 16 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(16>=1)&&(16<=5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(16>=1)&&(16<=4)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==5)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(16==0)) group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x40++0x03 line.long 0x00 "PORTE_PCR_16,PORTE Pin Control Register 16" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x44 - adres ; E - litera portu (A,B,C,...) ; 17 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(17>=1)&&(17<=5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(17>=1)&&(17<=4)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==5)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(17==0)) group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x44++0x03 line.long 0x00 "PORTE_PCR_17,PORTE Pin Control Register 17" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x48 - adres ; E - litera portu (A,B,C,...) ; 18 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(18>=1)&&(18<=5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(18>=1)&&(18<=4)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==5)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(18==0)) group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x48++0x03 line.long 0x00 "PORTE_PCR_18,PORTE Pin Control Register 18" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x4C - adres ; E - litera portu (A,B,C,...) ; 19 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(19>=1)&&(19<=5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(19>=1)&&(19<=4)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==5)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(19==0)) group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x4C++0x03 line.long 0x00 "PORTE_PCR_19,PORTE Pin Control Register 19" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x50 - adres ; E - litera portu (A,B,C,...) ; 20 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(20>=1)&&(20<=5)) group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(20>=1)&&(20<=4)) group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(20==5)) group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(20==0)) group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x50++0x03 line.long 0x00 "PORTE_PCR_20,PORTE Pin Control Register 20" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x54 - adres ; E - litera portu (A,B,C,...) ; 21 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(21>=1)&&(21<=5)) group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(21>=1)&&(21<=4)) group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(21==5)) group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(21==0)) group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x54++0x03 line.long 0x00 "PORTE_PCR_21,PORTE Pin Control Register 21" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x58 - adres ; E - litera portu (A,B,C,...) ; 22 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(22>=1)&&(22<=5)) group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(22>=1)&&(22<=4)) group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(22==5)) group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(22==0)) group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x58++0x03 line.long 0x00 "PORTE_PCR_22,PORTE Pin Control Register 22" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x5C - adres ; E - litera portu (A,B,C,...) ; 23 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(23>=1)&&(23<=5)) group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(23>=1)&&(23<=4)) group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(23==5)) group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(23==0)) group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x5C++0x03 line.long 0x00 "PORTE_PCR_23,PORTE Pin Control Register 23" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x60 - adres ; E - litera portu (A,B,C,...) ; 24 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(24>=1)&&(24<=5)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(24>=1)&&(24<=4)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==5)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(24==0)) group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x60++0x03 line.long 0x00 "PORTE_PCR_24,PORTE Pin Control Register 24" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x64 - adres ; E - litera portu (A,B,C,...) ; 25 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(25>=1)&&(25<=5)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(25>=1)&&(25<=4)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==5)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(25==0)) group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x64++0x03 line.long 0x00 "PORTE_PCR_25,PORTE Pin Control Register 25" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x68 - adres ; E - litera portu (A,B,C,...) ; 26 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(26>=1)&&(26<=5)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(26>=1)&&(26<=4)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==5)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(26==0)) group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x68++0x03 line.long 0x00 "PORTE_PCR_26,PORTE Pin Control Register 26" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B ; 0x6C - adres ; E - litera portu (A,B,C,...) ; 27 - numer portu width 16. sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")) if (('E'=='A')&&(27>=1)&&(27<=5)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D????AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22F*VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22F*VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R") if (('E'=='A')&&(27>=1)&&(27<=4)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==5)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" eventfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif (('E'=='A')&&(27==0)) group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" eventfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline eventfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" eventfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif elif cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK02F*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VFX12*") group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--11. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7,ALT8,ALT9,ALT10,ALT11,ALT12,ALT13,ALT14,ALT15" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "Disabled,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" else group.long 0x6C++0x03 line.long 0x00 "PORTE_PCR_27,PORTE Pin Control Register 27" eventfld.long 0x00 24. " ISF ,Interrupt status flag (in digital modes only)" "No interrupt,Interrupt" bitfld.long 0x00 16.--19. " IRQC ,Interrupt / DMA request configuration (in digital modes only)" "Disabled,DMA Req on rising edge,DMA Req on falling edge,DMA Req on either edge,,,,,Int when logic zero,Int on rising edge,Int on falling edge,Int on either edge,Int when logic one,?..." newline bitfld.long 0x00 15. " LK ,Lock bits [15:0]" "Not locked,Locked" bitfld.long 0x00 8.--10. " MUX ,Pin mux control" "ALT0,ALT1,ALT2,ALT3,ALT4,ALT5,ALT6,ALT7" newline bitfld.long 0x00 6. " DSE ,Drive strength enable (in digital modes only)" "Low,High" bitfld.long 0x00 5. " ODE ,Open drain enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 4. " PFE ,Passive filter enable (in digital modes only)" "Disabled,Enabled" newline bitfld.long 0x00 2. " SRE ,Slew rate enable (in digital modes only)" "Fast,Slow" bitfld.long 0x00 1. " PE ,Pull enable (in digital modes only)" "Disabled,Enabled" bitfld.long 0x00 0. " PS ,Pull select (in digital modes only)" "Down,Up" endif width 0x0B tree.end width 13. wgroup.long 0x80++0x7 line.long 0x00 "PORTF_GPCLR,PORTF Global Pin Control Low Register" bitfld.long 0x00 31. " GPWE15 ,Global pin 15 write enable" "Disable,Enable" bitfld.long 0x00 30. " GPWE14 ,Global pin 14 write enable" "Disable,Enable" bitfld.long 0x00 29. " GPWE13 ,Global pin 13 write enable" "Disable,Enable" bitfld.long 0x00 28. " GPWE12 ,Global pin 12 write enable" "Disable,Enable" textline " " bitfld.long 0x00 27. " GPWE11 ,Global pin 11 write enable" "Disable,Enable" bitfld.long 0x00 26. " GPWE10 ,Global pin 10 write enable" "Disable,Enable" bitfld.long 0x00 25. " GPWE9 ,Global pin 9 write enable" "Disable,Enable" bitfld.long 0x00 24. " GPWE8 ,Global pin 8 write enable" "Disable,Enable" textline " " bitfld.long 0x00 23. " GPWE7 ,Global pin 7 write enable" "Disable,Enable" bitfld.long 0x00 22. " GPWE6 ,Global pin 6 write enable" "Disable,Enable" bitfld.long 0x00 21. " GPWE5 ,Global pin 5 write enable" "Disable,Enable" bitfld.long 0x00 20. " GPWE4 ,Global pin 4 write enable" "Disable,Enable" textline " " bitfld.long 0x00 19. " GPWE3 ,Global pin 3 write enable" "Disable,Enable" bitfld.long 0x00 18. " GPWE2 ,Global pin 2 write enable" "Disable,Enable" bitfld.long 0x00 17. " GPWE1 ,Global pin 1 write enable" "Disable,Enable" bitfld.long 0x00 16. " GPWE0 ,Global pin 0 write enable" "Disable,Enable" textline " " hexmask.long.word 0x00 0.--15. 1. " GPWD ,Global pin write data" line.long 0x04 "PORTF_GPCHR,PORTF Global Pin Control High Register" bitfld.long 0x04 27. " GPWE27 ,Global pin 27 write enable" "Disable,Enable" bitfld.long 0x04 26. " GPWE26 ,Global pin 26 write enable" "Disable,Enable" bitfld.long 0x04 25. " GPWE25 ,Global pin 25 write enable" "Disable,Enable" bitfld.long 0x04 24. " GPWE24 ,Global pin 24 write enable" "Disable,Enable" textline " " bitfld.long 0x04 23. " GPWE23 ,Global pin 23 write enable" "Disable,Enable" bitfld.long 0x04 22. " GPWE22 ,Global pin 22 write enable" "Disable,Enable" bitfld.long 0x04 21. " GPWE21 ,Global pin 21 write enable" "Disable,Enable" bitfld.long 0x04 20. " GPWE20 ,Global pin 20 write enable" "Disable,Enable" textline " " bitfld.long 0x04 19. " GPWE19 ,Global pin 19 write enable" "Disable,Enable" bitfld.long 0x04 18. " GPWE18 ,Global pin 18 write enable" "Disable,Enable" bitfld.long 0x04 17. " GPWE17 ,Global pin 17 write enable" "Disable,Enable" bitfld.long 0x04 16. " GPWE16 ,Global pin 16 write enable" "Disable,Enable" textline " " hexmask.long.word 0x04 0.--15. 1. " GPWD ,Global pin write data" group.long 0xa0++0x3 line.long 0x00 "PORTF_ISFR,PORTF Interrupt Status Flag Register" eventfld.long 0x00 27. " ISF27 ,Interrupt status flag 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " ISF26 ,Interrupt status flag 26" "No interrupt,Interrupt" eventfld.long 0x00 25. " ISF25 ,Interrupt status flag 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " ISF24 ,Interrupt status flag 24" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " ISF23 ,Interrupt status flag 23" "No interrupt,Interrupt" eventfld.long 0x00 22. " ISF22 ,Interrupt status flag 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " ISF21 ,Interrupt status flag 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " ISF20 ,Interrupt status flag 20" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " ISF19 ,Interrupt status flag 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " ISF18 ,Interrupt status flag 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " ISF17 ,Interrupt status flag 17" "No interrupt,Interrupt" eventfld.long 0x00 16. " ISF16 ,Interrupt status flag 16" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " ISF15 ,Interrupt status flag 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " ISF14 ,Interrupt status flag 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " ISF13 ,Interrupt status flag 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " ISF12 ,Interrupt status flag 12" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " ISF11 ,Interrupt status flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " ISF10 ,Interrupt status flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " ISF9 ,Interrupt status flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " ISF8 ,Interrupt status flag 8" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " ISF7 ,Interrupt status flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " ISF6 ,Interrupt status flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " ISF5 ,Interrupt status flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " ISF4 ,Interrupt status flag 4" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " ISF3 ,Interrupt status flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " ISF2 ,Interrupt status flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " ISF1 ,Interrupt status flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " ISF0 ,Interrupt status flag 0" "No interrupt,Interrupt" rgroup.long 0xC0++0x0B line.long 0x00 "PORTF_DFER,Digital Filter Enable Register" bitfld.long 0x00 27. " DFE27 ,Digital filter enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " DFE26 ,Digital filter enable 26" "Disabled,Enabled" bitfld.long 0x00 25. " DFE25 ,Digital filter enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " DFE24 ,Digital filter enable 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DFE23 ,Digital filter enable 23" "Disabled,Enabled" bitfld.long 0x00 22. " DFE22 ,Digital filter enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " DFE21 ,Digital filter enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " DFE20 ,Digital filter enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DFE19 ,Pin 19 Digital filter enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " DFE18 ,Digital filter enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " DFE17 ,Digital filter enable 17" "Disabled,Enabled" bitfld.long 0x00 16. " DFE16 ,Digital filter enable 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " DFE15 ,Digital filter enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " DFE14 ,Digital filter enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " DFE13 ,Digital filter enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " DFE12 ,Digital filter enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " DFE11 ,Digital filter enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " DFE10 ,Digital filter enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " DFE9 ,Digital filter enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " DFE8 ,Digital filter enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " DFE7 ,Digital filter enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " DFE6 ,Digital filter enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " DFE5 ,Digital filter enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " DFE4 ,Digital filter enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DFE3 ,Digital filter enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " DFE2 ,Digital filter enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " DFE1 ,Digital filter enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " DFE0 ,Digital filter enable 0" "Disabled,Enabled" line.long 0x04 "PORTF_DFCR,Digital Filter Clock Register" bitfld.long 0x00 0. " CS ,Clock source" "Bus clk,1 kHz LPO" line.long 0x08 "PORTF_DFWR,Digital Filter Width Register" bitfld.long 0x04 0. " FILT ,Filter length" "0,1" endif width 0x0B tree.end tree.end tree.open "System Modules" tree "SIM (System Integration Module)" base ad:0x40047000 width 10. group.long 0x00++0x07 line.long 0x00 "SOPT1,System Options Register 1" bitfld.long 0x00 31. " USBREGEN ,USB voltage regulator enable" "Disabled,Enabled" bitfld.long 0x00 30. " USBSSTBY ,USB voltage regulator in standby mode during stop" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " USBSTBY ,USB voltage regulator in standby mode during VLP" "Disabled,Enabled" bitfld.long 0x00 19. " OSC32KSEL ,32K oscillator clock select" "System,RTC" textline " " rbitfld.long 0x00 12.--15. " RAMSIZE ,RAM size" ",,,,,,,,,128 kB,?..." line.long 0x04 "SOPT1CFG,SOPT1 Configuration Register" bitfld.long 0x04 26. " USSWE ,USB voltage regulator stop standby write enable" "Disabled,Enabled" bitfld.long 0x04 25. " UVSWE ,UUSB voltage regulator VLP standby write enable" "Disabled,Enabled" textline " " bitfld.long 0x04 24. " URWE ,USB voltage regulator enable write enable" "Disabled,Enabled" base ad:0x40048000 group.long 0x04++0x03 line.long 0x00 "SOPT2,System Options Register 2" bitfld.long 0x00 30.--31. " NFCSRC ,NFC Flash clock source select" "Bus clock,MCGPLL0CLK,MCGPLL1CLK,OSC0ERCLK" bitfld.long 0x00 28.--29. " ESDHCSRC ,ESDHC perclk source select" "Core/system clock,MCGPLLCLK/MCGFLLCLK,EXTAL clock,External bypass clock (PTD11)" textline " " bitfld.long 0x00 26.--27. " LCDCSRC ,LCDC Pixel clock source select" "Bus clock,MCGPLL0CLK,MCGPLL1CLK,OSC0ERCLK" bitfld.long 0x00 22.--23. " USBFSRC ,USB FS clock source select" "MCGPLLCLK/MCGFLLCLK,MCGPLL0CLK,MCGPLL1CLK,OSC0ERCLK" textline " " bitfld.long 0x00 20.--21. " TIMESRC ,Ethernet timestamp clock source select" "System platform clock,MCGPLLCLK/MCGFLLCLK,OSC0ERCLK,External bypass clock (PTE26)" bitfld.long 0x00 18. " USBF_CLKSEL ,USB FS clock select" "External bypass clock (PTE26),Clock divider USB FS clock" textline " " bitfld.long 0x00 16.--17. " PLLFLLSEL ,PLL/FLL clock select" "MCGFLLCLK,MCGPLL0CLK,MCGPLL1CLK,System platform clock" bitfld.long 0x00 15. " NFC_CLKSEL ,NFC Flash clock select" "Clock divider NFC clock,EXTAL clock" textline " " bitfld.long 0x00 14. " LCDC_CLKSEL ,LCDC pixel clock select" "Clock divider LCDC pixel clock,EXTAL clock" bitfld.long 0x00 12. " TRACECLKSEL ,Debug trace clock select" "MCGCLKOUT,Core/system clock" textline " " bitfld.long 0x00 11. " CMTUARTPAD ,CMT/UART pad drive strength" "Single-pad,Dual-pad" textline " " bitfld.long 0x00 8.--9. " FBSL ,Flexbus security level" "All off-chip disallowed,,Off-chip op code disallowed/Data acess allowed,Off-chip op code allowed & data access allowed" textline " " bitfld.long 0x00 5.--7. " CLKOUTSEL ,Clock out select" "FlexBus clock,,Flash ungated clock,LPO clock (1 kHz),MCGIRCLK,RTC 32 kHz clock,OSC0ERCLK,OSC1ERCLK" textline " " bitfld.long 0x00 4. " RTCCLKOUTSEL ,RTC clock out select" "RTC 1 Hz clock,RTC 32 kHz oscillator" bitfld.long 0x00 2.--3. " USBHSRC ,USB HS clock source select" "Bus clock,MCGPLL0CLK,MCGPLL1CLK,OSC0ERCLK" group.long 0x0c++0x0f line.long 0x00 "SOPT4,System Options Register 4" bitfld.long 0x00 31. " FTM3TRG1SRC ,FlexTimer 3 hardware trigger 1 Source Select" "PDB,FTM3" bitfld.long 0x00 30. " FTM3TRG0SRC ,FlexTimer 3 hardware trigger 0 Source Select" "CMP3,FTM1" textline " " bitfld.long 0x00 29. " FTM0TRG1SRC ,FlexTimer 0 hardware trigger 1 Source Select" "PDB,FTM2" bitfld.long 0x00 28. " FTM0TRG0SRC ,FlexTimer 0 hardware trigger 0 Source Select" "CMP0,FTM1" textline " " bitfld.long 0x00 27. " FTM3CLKSEL ,FlexTimer 3 external clock pin select" "FTM_CLKIN0,FTM_CLKIN1" bitfld.long 0x00 26. " FTM2CLKSEL ,FlexTimer 2 External Clock Pin Select" "FTM_CLKIN0,FTM_CLKIN1" textline " " bitfld.long 0x00 25. " FTM1CLKSEL ,FlexTimer 1 External Clock Pin Select" "FTM_CLKIN0,FTM_CLKIN1" bitfld.long 0x00 24. " FTM0CLKSEL ,FlexTimer 0 External Clock Pin Select" "FTM_CLKIN0,FTM_CLKIN1" textline " " bitfld.long 0x00 20.--21. " FTM2CH0SRC ,Flextimer 2 channel 0 input capture source select" "FTM2_CH0 pin,CMP0 output,CMP1 output,?..." bitfld.long 0x00 18.--19. " FTM1CH0SRC ,Flextimer 1 channel 0 input capture source select" "FTM1_CH0 pin,CMP0 output,CMP1 output,USB SOF trigger" textline " " bitfld.long 0x00 12. " FTM3FLT0 ,Flextimer 3 Fault 0 Select" "FTM3_FLT0 pin,CMP0 out" bitfld.long 0x00 8. " FTM2FLT0 ,Flextimer 2 Fault 0 Select" "FTM2_FLT0 pin,CMP0 out" textline " " bitfld.long 0x00 4. " FTM1FLT0 ,FlexTimer 1 Fault 0 Select" "FTM1_FLT0 pin,CMP0 out" bitfld.long 0x00 3. " FTM0FLT3 ,FlexTimer 0 Fault 3 Select" "FTM0_FLT3 pin,CMP0 out" textline " " bitfld.long 0x00 2. " FTM0FLT2 ,FlexTimer 0 Fault 2 Select" "FTM0_FLT2,CMP2 out" bitfld.long 0x00 1. " FTM0FLT1 ,FlexTimer 0 Fault 1 Select" "FTM0_FLT1,CMP1 out" textline " " bitfld.long 0x00 0. " FTM0FLT0 ,FlexTimer 0 Fault 0 Select" "FTM0_FLT0,CMP0 out" textline " " line.long 0x04 "SOPT5,System Options Register 5" bitfld.long 0x04 6.--7. " UART1RXSRC ,UART 1 receive data source select" "UART1_RX,CMP0,CMP1,?..." bitfld.long 0x04 4.--5. " UART1TXSRC ,UART 1 transmit data source select" "UART1_TX,UART1_TX mod with FTM1 ch#0 Out,UART1_TX mod with FTM2 ch#0 Out,?..." textline " " bitfld.long 0x04 2.--3. " UART0RXSRC ,UART 0 receive data source select" "UART0_RX,CMP0,CMP1,?..." bitfld.long 0x04 0.--1. " UART0TXSRC ,UART 0 transmit data source select" "UART0_TX,UART0_TX mod with FTM1 ch#0 Out,UART0_TX mod with FTM2 ch#0 Out,?..." line.long 0x08 "SOPT6,System Options Register 6" bitfld.long 0x08 16.--19. " PCR ,FlexBus hold cycles before FlexBus can release bus to NFC or to IDLE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x08 0.--15. 1. " MCC ,NFC hold cycle in case FlexBus request while NFC is granted" line.long 0x0c "SOPT7,System Options Register 7" bitfld.long 0x0C 31. " ADC3ALTTRGEN ,ADC3 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x0C 28. " ADC3PRETRGSEL ,ADC3 pre-trigger select" "Pre-trigger A,Pre-trigger B" textline " " bitfld.long 0x0C 24.--27. " ADC3TRGSEL ,ADC3 trigger select" "External trigger,HS comparator 0 Out,HS comparator 1 Out,HS comparator 2 Out,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,RTC alarm,RTC seconds,Low-power timer trigger,HS comparator 3 Out" bitfld.long 0x0C 23. " ADC2ALTTRGEN ,ADC2 alternate trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 20. " ADC2PRETRGSEL ,ADC2 pre-trigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x0C 16.--19. " ADC2TRGSEL ,ADC2 trigger select" "External trigger,HS comparator 0 Out,HS comparator 1 Out,HS comparator 2 Out,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,RTC alarm,RTC seconds,Low-power timer trigger,HS comparator 3 Out" textline " " bitfld.long 0x0C 15. " ADC1ALTTRGEN ,ADC1 alternate trigger enable" "Disabled,Enabled" bitfld.long 0x0C 12. " ADC1PRETRGSEL ,ADC1 pre-trigger select" "Pre-trigger A,Pre-trigger B" textline " " bitfld.long 0x0C 8.--11. " ADC1TRGSEL ,ADC1 trigger select" "External trigger,HS comparator 0 Out,HS comparator 1 Out,HS comparator 2 Out,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,RTC alarm,RTC seconds,Low-power timer trigger,HS comparator 3 Out" bitfld.long 0x0C 7. " ADC0ALTTRGEN ,ADC0 alternate trigger enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 4. " ADC0PRETRGSEL ,ADC0 pretrigger select" "Pre-trigger A,Pre-trigger B" bitfld.long 0x0C 0.--3. " ADC0TRGSEL ,ADC0 trigger select" "External trigger,HS comparator 0 Out,HS comparator 1 Out,HS comparator 2 Out,PIT trigger 0,PIT trigger 1,PIT trigger 2,PIT trigger 3,FTM0 trigger,FTM1 trigger,FTM2 trigger,FTM3 trigger,RTC alarm,RTC seconds,Low-power timer trigger,HS comparator 3 Out" rgroup.long 0x24++0x03 line.long 0x00 "SDID,System Device Identification Register" hexmask.long.byte 0x00 12.--15. 1. " REVID ,Device Revision Number" bitfld.long 0x00 4.--6. " FAMID ,Kinetis family identification" "K10,K20,K61,,K60,K70,?..." textline " " bitfld.long 0x00 0.--3. " PINID ,Pincount identification" ",,,,,,,,,,144-pin,,196-pin,,256-pin,?..." group.long 0x28++0x03 line.long 0x00 "SCGC1,System Clock Gating Control Register 1" bitfld.long 0x00 11. " UART5 ,UART5 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x00 10. " UART4 ,UART4 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x00 5. " OSC1 ,OSC1 clock gate control" "Clock disabled,Clock enabled" group.long 0x2C++0x1F line.long 0x00 "SCGC2,System Clock Gating Control Register 2" bitfld.long 0x00 13. " DAC1 ,DAC1 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x00 12. " DAC0 ,DAC0 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x00 0. " ENET ,ENET clock gate control" "Clock disabled,Clock enabled" line.long 0x04 "SCGC3,System Clock Gating Control Register 3" bitfld.long 0x04 28. " ADC3 ,ADC3 clock gate control" "Clock is disabled,Clock is enabled" bitfld.long 0x04 27. " ADC1 ,ADC1 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x04 25. " FTM3 ,FTM3 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x04 24. " FTM2 ,FTM2 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x04 22. " LCDC ,LCDC clock gate control" "Clock is disabled,Clock is enabled" bitfld.long 0x04 17. " ESDHC ,ESDHC clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x04 15. " SAI1 ,SAI1 clock gate control" "Clock is disabled,Clock is enabled" bitfld.long 0x04 14. " DDR ,DDR clock gate control" "Clock is disabled,Clock is enabled" textline " " bitfld.long 0x04 12. " DSPI2 ,DSPI2 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x04 8. " NFC ,NFC clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x04 4. " FLEXCAN1 ,FlexCAN1 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x04 0. " RNGA ,RNGA clock gate control" "Clock disabled,Clock enabled" line.long 0x08 "SCGC4,System Clock Gating Control Register 4" bitfld.long 0x08 28. " LLWU ,LLWU clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 20. " VREF ,VREF clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x08 19. " CMP ,Comparator clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 18. " USBFS ,USB clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x08 13. " UART3 ,UART3 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 12. " UART2 ,UART2 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x08 11. " UART1 ,UART1 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 10. " UART0 ,UART0 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x08 7. " IIC1 ,IIC1 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 6. " IIC0 ,IIC0 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x08 2. " CMT ,CMT clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x08 1. " EWM ,EWM clock gate control" "Clock disabled,Clock enabled" line.long 0x0C "SCGC5,System Clock Gating Control Register 5" bitfld.long 0x0C 14. " PORTF ,Port F clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x0C 13. " PORTE ,Port E clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 12. " PORTD ,Port D clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x0C 11. " PORTC ,Port C clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 10. " PORTB ,Port B clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x0C 9. " PORTA ,Port A clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 5. " TSI ,TSI clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x0C 3. " DRYICESECREG ,Dryice SECREG clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 2. " DRYICE ,Dryice clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 1. " REGFILE ,Register file clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x0C 0. " LPTIMER ,Low power timer clock gate control" "Clock disabled,Clock enabled" line.long 0x10 "SCGC6,System Clock Gating Control Register 6" bitfld.long 0x10 29. " RTC ,RTC clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 28. " ADC2 ,ADC2 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 27. " ADC0 ,ADC0 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 25. " FTM1 ,FTM1 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 24. " FTM0 ,FTM0 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 23. " PIT ,PIT clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 22. " PDB ,PDB clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 21. " USBDCD ,USB DCD clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 20. " USBHS ,USB2 OTG clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 18. " CRC ,CRC clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 15. " SAI0 ,SAI0 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 13. " DSPI1 ,DSPI1 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 12. " DSPI0 ,DSPI0 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 4. " FLEXCAN0 ,FlexCAN0 clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x10 2. " DMAMUX1 ,DMA Mux 1 clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x10 1. " DMAMUX0 ,DMA Mux 0 clock gate control" "Clock disabled,Clock enabled" line.long 0x14 "SCGC7,System Clock Gating Control Register 7" bitfld.long 0x14 2. " MPU ,MPU clock gate control" "Clock disabled,Clock enabled" bitfld.long 0x14 1. " DMA ,DMA clock gate control" "Clock disabled,Clock enabled" textline " " bitfld.long 0x14 0. " FLEXBUS ,FlexBus clock gate control" "Clock disabled,Clock enabled" line.long 0x18 "CLKDIV1,System Clock Divider Register 1" bitfld.long 0x18 28.--31. " OUTDIV1 ,Clock 1 output divider value" "Div by 1,Div by 2,Div by 3,Div by 4,Div by 5,Div by 6,Div by 7,Div by 8,Div by 9,Div by 10,Div by 11,Div by 12,Div by 13,Div by 14,Div by 15,Div by 16" bitfld.long 0x18 24.--27. " OUTDIV2 ,Clock 2 output Divider value" "Div by 1,Div by 2,Div by 3,Div by 4,Div by 5,Div by 6,Div by 7,Div by 8,Div by 9,Div by 10,Div by 11,Div by 12,Div by 13,Div by 14,Div by 15,Div by 16" textline " " bitfld.long 0x18 20.--23. " OUTDIV3 ,Clock 3 output Divider value" "Div by 1,Div by 2,Div by 3,Div by 4,Div by 5,Div by 6,Div by 7,Div by 8,Div by 9,Div by 10,Div by 11,Div by 12,Div by 13,Div by 14,Div by 15,Div by 16" bitfld.long 0x18 16.--19. " OUTDIV4 ,Clock 4 output divider value" "Div by 1,Div by 2,Div by 3,Div by 4,Div by 5,Div by 6,Div by 7,Div by 8,Div by 9,Div by 10,Div by 11,Div by 12,Div by 13,Div by 14,Div by 15,Div by 16" line.long 0x1C "CLKDIV2,System Clock Divider Register 2" bitfld.long 0x1C 9.--11. " USBHSDIV ,USB HS clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 8. " USBHSFRAC ,USB HS clock divider fraction" "0,1" textline " " bitfld.long 0x1C 1.--3. " USBFSDIV ,USB FS clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 0. " USBFSFRAC ,USB FS clock divider fraction" "0,1" group.long 0x4C++0x03 line.long 0x00 "FCFG1,Flash Configuration Register 1" rbitfld.long 0x00 28.--31. " NVMSIZE ,FlexNVM memory size" "0 KB,,,,,,,,,,,512 KB,,,,512 KB" rbitfld.long 0x00 24.--27. " PFSIZE ,Program flash size" ",,,,,,,,,,,512 KB,,1024 KB,,1024 KB" textline " " rbitfld.long 0x00 16.--19. " EESIZE ,EEPROM size" "16 KB,8 KB,4 KB,2 KB,1 KB,512 Bytes,256 Bytes,128 Bytes,64 Bytes,32 Bytes,,,,,,0 bytes" textline " " sif (!cpuis("MK70FN*")) rbitfld.long 0x00 8.--11. " DEPART ,FlexNVM partition (Data flash / EEPROM backup split)" "256/0 Kb,,,,192/64 Kb,128/128 Kb,0/256 Kb,,0/256 Kb,,,,64/192 Kb,128/128 Kb,256/0 Kb,256/0 Kb" textline " " endif bitfld.long 0x00 0. " FTFDIS , Disable FTFE" "No,Yes" sif (cpuis("MK70FN*")) rgroup.long 0x50++0x13 line.long 0x00 "FCFG2,Flash Configuration Register 2" bitfld.long 0x00 31. " SWAPPFLSH , Swap program flash" "Not active,Active" bitfld.long 0x00 24.--29. " MAXADDR01 , Max address block 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 23. " PFLSH , Program flash only" "Supported FlexNVM,Not supported FlexNVM" bitfld.long 0x00 16.--21. " MAXADDR23 , Max address block 2 or 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else rgroup.long 0x50++0x13 line.long 0x00 "FCFG2,Flash Configuration Register 2" bitfld.long 0x00 24.--29. " MAXADDR01 , Max address block 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 23. " PFLSH , Program flash only" "Supported FlexNVM,Not supported FlexNVM" bitfld.long 0x00 16.--21. " MAXADDR23 , Max address block 2 or 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif rgroup.long 0x54++0x13 line.long 0x00 "UIDH,Unique Identification Register High" line.long 0x04 "UIDMH,Unique Identification Register Mid-High" line.long 0x08 "UIDML,Unique Identification Register Mid Low" line.long 0x0C "UIDL,Unique Identification Register Low" group.long 0x64++0xB line.long 0x00 "CLKDIV3,System Clock Divider Register 3" hexmask.long.word 0x00 16.--27. 1. " LCDCDIV ,LCDC Clock divider fraction" hexmask.long.byte 0x00 8.--15. 1. " LCDCFRAC ,LCDCFRAC clock divider fraction" line.long 0x04 "CLKDIV4,System Clock Divider Register 4" bitfld.long 0x04 27.--31. " NFCDIV ,NFC clock divider divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 24.--26. " NFCFRAC ,NFC clock divider fraction" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 1.--3. " TRACEDIV ,Trace clock divider divisor" "0,1,2,3,4,5,6,7" bitfld.long 0x04 0. " TRACEFRAC ,Trace clock divider fraction" "0,1" line.long 0x08 "MCR,Misc Control Register" bitfld.long 0x08 31. " TRACECLKDIS ,Trace clock disable" "No,Yes" textline " " sif (cpu()!="MK70FN1M0VMJ12")||(cpu()!="MK70FN1M0VMJ15") bitfld.long 0x08 30. " ULPICLKOBE ,60 MHz ULPI clock output enable" "Disabled,Enabled" textline " " endif bitfld.long 0x08 29. " PDBLOOP ,PDB Loop Mode" "Separate,Common" bitfld.long 0x08 16. " LCDSTART ,Start LCDC display" "Stopped,Started" textline " " bitfld.long 0x08 9. " RCRRST ,DDR RCR Reset Status" "No reset,Reset" bitfld.long 0x08 8. " RCRRSTEN ,DDR RCR Special Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 5.--7. " DDRCFG ,DDR configuration select" "LPDDR Half Strength,LPDDR Full Strength,DDR2 Half Strength,DDR1,,DDR2 Full Strength,?..." bitfld.long 0x08 3. " DDRDQSDIS ,DDR_DQS analog circuit disable" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " DDRPEN ,Pin enable for all DDR I/O" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " DDRS ,DDR Self Refresh Status" "Disabled,Enabled" bitfld.long 0x08 0. " DDRSREN ,DDR self refresh enable" "Disabled,Enabled" width 0x0B tree.end tree "RCM (Reset Control Module)" base ad:0x4007F000 width 7. rgroup.byte 0x00++0x01 line.byte 0x00 "SRS0,System Reset Status Register 0" bitfld.byte 0x00 7. " POR ,Power-on reset" "Not caused,Caused" bitfld.byte 0x00 6. " PIN ,External reset pin" "Not caused,Caused" bitfld.byte 0x00 5. " WDOG ,Watchdog" "Not caused,Caused" sif cpuis("MK02*")||cpuis("MK22FN128*")||cpuis("MK60F*") newline bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" else newline bitfld.byte 0x00 3. " LOL ,Loss-of-lock reset" "Not caused,Caused" bitfld.byte 0x00 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x00 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" newline bitfld.byte 0x00 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" endif line.byte 0x01 "SRS1,System Reset Status Register 1" sif !cpuis("MK26FN*")&&!cpuis("MK24FN*")&&!cpuis("MK22F*")&&!cpuis("MK22D*")&&!cpuis("MK20*")&&!cpuis("MK10F*")&&!cpuis("MK10D*")&&!cpuis("MK12D*")&&!cpuis("MK30D*")&&!cpuis("MK40D*")&&!cpuis("MK5?D*")&&!cpuis("MK60*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&(!cpuis("MK84FN2M0CAU15R"))&&!cpuis("MK8?FN256V*")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MKS2?FN???V??12")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 7. " TAMPER ,Tamper detect" "Not caused,Caused" newline endif sif cpuis("MK02*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12") bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused" bitfld.byte 0x01 2. " SW ,Software reset" "Not caused,Caused" newline bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "Not caused,Caused" else bitfld.byte 0x01 5. " SACKERR ,Stop mode acknowledge error reset" "Not caused,Caused" bitfld.byte 0x01 4. " EZPT ,EzPort reset" "Not caused,Caused" bitfld.byte 0x01 3. " MDM_AP ,MDM-AP system reset request" "Not caused,Caused" newline bitfld.byte 0x01 2. " SW ,Software reset" "Not caused,Caused" bitfld.byte 0x01 1. " LOCKUP ,Core lockup" "Not caused,Caused" bitfld.byte 0x01 0. " JTAG ,JTAG generated reset" "Not caused,Caused" endif group.byte 0x04++0x01 line.byte 0x00 "RPFC,Reset Pin Filter Control Register" bitfld.byte 0x00 2. " RSTFLTSS ,Reset pin filter select in stop mode" "All filtering disabled,LPO clock filter enabled" newline bitfld.byte 0x00 0.--1. " RSTFLTSRW ,Reset pin filter select in run and wait modes" "All filtering disabled,Bus clock filter enabled,LPO clock filter enabled,?..." line.byte 0x01 "RPFW,Reset Pin Filter Width Register" bitfld.byte 0x01 0.--4. " RSTFLTSEL ,Selects the reset pin bus clock filter width" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x06++0x00 line.byte 0x00 "FM,Force Mode Register" bitfld.byte 0x00 1.--2. " FORCEROM ,Force ROM Boot" "No effect,Force w/ RCM_MR[1] set,Force w/ RCM_MR[2] set,Force w/ RCM_MR[2:1] set" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1.--2. " BOOTROM ,Boot ROM Configuration" "Flash,BOOTCFG0,FOPT[7],BOOTCFG0 and FOPT[7]" elif !cpuis("MK02*")&&!cpuis("MKS2?FN???V??12") rgroup.byte 0x07++0x00 line.byte 0x00 "MR,Mode Register" bitfld.byte 0x00 1. " EZP_MS ,EZP_MS_B pin state" "Deasserted,Asserted" endif newline sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R") group.byte 0x08++0x01 line.byte 0x00 "SSRS0,Sticky System Reset Status Register 0" eventfld.byte 0x00 7. " SPOR ,Sticky power-on reset" "Not caused,Caused" eventfld.byte 0x00 6. " SPIN ,Sticky external reset pin" "Not caused,Caused" eventfld.byte 0x00 5. " SWDOG ,Sticky watchdog" "Not caused,Caused" sif cpuis("MK02*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN128VLH10R") newline eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "Not caused,Caused" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused" eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused" else newline eventfld.byte 0x00 3. " SLOL ,Sticky loss-of-lock reset" "Not caused,Caused" eventfld.byte 0x00 2. " SLOC ,Sticky loss-of-clock reset" "Not caused,Caused" eventfld.byte 0x00 1. " SLVD ,Sticky low-voltage detect reset" "Not caused,Caused" newline eventfld.byte 0x00 0. " SWAKEUP ,Sticky low leakage wakeup reset" "Not caused,Caused" endif line.byte 0x01 "SSRS1,Sticky System Reset Status Register 1" eventfld.byte 0x01 5. " SSACKERR ,Sticky stop mode acknowledge error reset" "Not caused,Caused" sif !cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MKS2?FN???V??12") eventfld.byte 0x01 4. " SEZPT ,Sticky EzPort reset" "Not caused,Caused" endif eventfld.byte 0x01 3. " SMDM_AP ,Sticky MDM-AP system reset request" "Not caused,Caused" eventfld.byte 0x01 2. " SSW ,Sticky software" "Not caused,Caused" newline eventfld.byte 0x01 1. " SLOCKUP ,Sticky core lockup" "Not caused,Caused" eventfld.byte 0x01 0. " SJTAG ,Sticky JTAG generated reset" "Not caused,Caused" endif width 0x0B tree.end tree "SMC (System Mode Controller)" base ad:0x4007E000 sif (cpuis("MK60D*AB10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("KK60DN512ZCAB10R")) width 8. rgroup.byte 0x00++0x01 line.byte 0x00 "SRSH,System Reset Status Register High" bitfld.byte 0x00 2. " SW ,Software reset" "Not caused,Caused" bitfld.byte 0x00 1. " LOCKUP ,Core-lockup reset" "Not caused,Caused" bitfld.byte 0x00 0. " JTAG ,JTAG generated reset" "Not caused,Caused" line.byte 0x01 "SRSL,System Reset Status Register Low" bitfld.byte 0x01 7. " POR ,Power-on reset" "Not caused,Caused" bitfld.byte 0x01 6. " PIN ,External reset pin" "Not caused,Caused" bitfld.byte 0x01 5. " COP ,Computer operating properly (Cop) watchdog" "Not caused,Caused" newline bitfld.byte 0x01 2. " LOC ,Loss-of-clock reset" "Not caused,Caused" bitfld.byte 0x01 1. " LVD ,Low-voltage detect reset" "Not caused,Caused" bitfld.byte 0x01 0. " WAKEUP ,Low-leakage wakeup reset" "Not caused,Caused" group.byte 0x02++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.byte 0x00 4. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" bitfld.byte 0x00 2. " AVLLS3 ,Allow very low leakage stop 3 mode" "Not allowed,Allowed" newline bitfld.byte 0x00 1. " AVLLS2 ,Allow very low leakage stop 2 mode" "Not allowed,Allowed" bitfld.byte 0x00 0. " AVLLS1 ,Allow very low leakage stop 1 mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" hexmask.byte 0x01 0.--7. 1. "PMCTRL,Power mode control" newline else width 10. group.byte 0x00++0x01 line.byte 0x00 "PMPROT,Power Mode Protection Register" sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " AHSRUN ,Allow high speed run mode" "Not allowed,Allowed" newline endif bitfld.byte 0x00 5. " AVLP ,Allow very low power modes" "Not allowed,Allowed" bitfld.byte 0x00 3. " ALLS ,Allow low leakage stop mode" "Not allowed,Allowed" bitfld.byte 0x00 1. " AVLLS ,Allow very low leakage stop mode" "Not allowed,Allowed" line.byte 0x01 "PMCTRL,Power Mode Control Register" sif !cpuis("MK?0D*7")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK30DX256VLL7R") bitfld.byte 0x01 7. " LPWUI ,Low power wake up on interrupt" "Remain,Exit" newline endif sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High speed run mode" newline elif cpuis("MK84FN2M0CAU15R") bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,High speed" newline else bitfld.byte 0x01 5.--6. " RUNM ,Run mode control" "Normal,,Very low power,?..." newline endif rbitfld.byte 0x01 3. " STOPA ,Stop aborted" "Not aborted,Aborted" bitfld.byte 0x01 0.--2. " STOPM ,Stop mode control" "Normal stop,,VLPS,LLS,VLLSX,?..." sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK02*")||cpuis("KK65FN2M0CAC18R") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline bitfld.byte 0x00 0.--2. " LLSM ,LLS mode control" ",,LLS2,LLS3,?..." endif else sif cpuis("MK02*") group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" endif endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x01))&0x07)==0x03) group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" newline bitfld.byte 0x00 0.--2. " LLSM ,VLLS mode control" ",,LLS2,LLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "STOPCTRL,VLLS Control Register" bitfld.byte 0x00 6.--7. " PSTOPO ,Partial stop option" "STOP,PSTOP1,PSTOP2,?..." bitfld.byte 0x00 5. " PORPO ,Disable POR detect circuit in VLLS0 mode" "No,Yes" bitfld.byte 0x00 4. " RAM2PO ,Powering of RAM partition 2 in LLS2 or VLLS2 mode" "Not powered,Powered" bitfld.byte 0x00 3. " LPOPO ,Disable 1 kHz LPO clock in LLS/VLLSX modes" "No,Yes" endif elif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) if (((per.b(ad:0x4007E000+0x02))&0x07)==0x00) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif (((per.b(ad:0x4007E000+0x02))&0x07)==0x02) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." else group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif else hgroup.byte 0x02++0x00 hide.byte 0x00 "VLLSCTRL,VLLS Control Register" endif else if (((per.b(ad:0x4007E000+0x01))&0x07)==0x04) group.byte 0x02++0x00 line.byte 0x00 "VLLSCTRL,Stop Control Register" sif cpuis("MK10D*5")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK63F*") bitfld.byte 0x00 5. " PORPO ,POR power option" "Enabled,Disabled" newline endif sif cpuis("MK?0D*10")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK5?D*10")||cpuis("MK60D*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") bitfld.byte 0x00 4. " RAM2PO ,RAM2 power option" "Not powered,Powered" newline endif sif cpuis("MK63FN1M0VLQ12R") bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." elif cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK10F*12")||cpuis("MK5?D*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DX256VLL7R")||cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" ",VLLS1,VLLS2,VLLS3,?..." else bitfld.byte 0x00 0.--2. " VLLSM ,VLLS mode control" "VLLS0,VLLS1,VLLS2,VLLS3,?..." endif else hgroup.byte 0x02++0x00 hide.byte 0x00 "VLLSCTRL,VLLS Control Register" endif endif rgroup.byte 0x03++0x00 line.byte 0x00 "PMSTAT,Power Mode Status Register" sif !cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK02*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK63F*")&&!cpuis("MK60F*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK65FN2M0CAC18R") hexmask.byte 0x00 0.--6. 1. "PMSTAT ,PMSTAT" endif endif width 0x0B tree.end tree "PMC (Power Management Controller)" base ad:0x4007D000 width 8. group.byte 0x00++0x02 line.byte 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 Register" rbitfld.byte 0x00 7. " LVDF ,Low-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " LVDACK ,Low-voltage detect acknowledge" "NACK,ACK" bitfld.byte 0x00 5. " LVDIE ,Low-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " LVDRE ,Low-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0.--1. " LVDV ,Low-voltage detect voltage select" "Low trip,High trip,?..." line.byte 0x01 "LVDSC2,Low Voltage Detect Status and Control 2 Register" rbitfld.byte 0x01 7. " LVWF ,Low-voltage warning flag" "Not detected,Detected" bitfld.byte 0x01 6. " LVWACK ,Low-voltage warning acknowledge" "NACK,ACK" bitfld.byte 0x01 5. " LVWIE ,Low-voltage warning interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x01 0.--1. " LVWV ,Low-voltage warning voltage select" "Low trip point,Mid 1 trip point,Mid 2 trip point,High trip point" line.byte 0x02 "REGSC,Regulator Status and Control Register" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40DX*Z*10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 4. " TRAMPO ,Traditional RAM power option" "Not powered,Powered" newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK02*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 4. " BGEN ,Bandgap Enable In VLPx/LLS/VLLSx modes" "Disabled,Enabled" newline elif !cpuis("MK10F*12*")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x02 4. " BGEN ,Bandgap enable" "Enabled,Disabled" newline elif cpuis("MK10DX256ZV??10*") bitfld.byte 0x02 4. " TRAMPO ,Traditional RAM power option" "Not powered,Powered" newline endif sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("KK60DN512ZCAB10R") rbitfld.byte 0x02 3. " VLPRS ,Very low power run status" "Off,On" newline else eventfld.byte 0x02 3. " ACKISO ,Acknowledge isolation" "Disabled,Enabled" newline endif rbitfld.byte 0x02 2. " REGONS ,Regulator in run regulation status" "Stop,Run" sif cpuis("MK?0D*7") newline bitfld.byte 0x02 1. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" else newline bitfld.byte 0x02 0. " BGBE ,Bandgap buffer enable" "Disabled,Enabled" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.byte 0x0B++0x00 line.byte 0x00 "HVDSC1,High Voltage Detect Status And Control 1 Register" rbitfld.byte 0x00 7. " HVDF ,High-voltage detect flag" "Not detected,Detected" bitfld.byte 0x00 6. " HVDACK ,High-voltage detect acknowledge" "NACK,ACK" bitfld.byte 0x00 5. " HVDIE ,High-voltage detect interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " HVDRE ,High-voltage detect reset enable" "Disabled,Enabled" bitfld.byte 0x00 0. " HVDV ,High-voltage detect voltage select" "Low trip,High trip" endif width 0x0B tree.end tree "LLWU (Low-Leakage Wake-up Unit)" base ad:0x4007C000 width 7. sif cpuis("MK02*") sif cpuis("*LH*") group.byte 0x00++0x02 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE_3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 0.--1. " WUPE_0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE_7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 4.--5. " WUPE_6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 2.--3. " WUPE_5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x01 0.--1. " WUPE_4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 6.--7. " WUPE_11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 4.--5. " WUPE_10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 2.--3. " WUPE_9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x02 0.--1. " WUPE_8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" else group.byte 0x00++0x02 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE_3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE_7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 4.--5. " WUPE_6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 2.--3. " WUPE_5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 4.--5. " WUPE_10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 2.--3. " WUPE_9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 0.--1. " WUPE_8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" endif sif cpuis("*LH*")||cpuis("*LF*") group.byte 0x03++0x00 line.byte 0x00 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x00 6.--7. " WUPE_15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 4.--5. " WUPE_14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 2.--3. " WUPE_13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x00 0.--1. " WUPE_12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" else group.byte 0x03++0x00 line.byte 0x00 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x00 6.--7. " WUPE_15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 4.--5. " WUPE_14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" endif textline " " group.byte 0x04++0x00 line.byte 0x00 "ME,LLWU Module Enable Register" bitfld.byte 0x00 7. " WUME_7 ,Wakeup module enable for module 7" "Disabled,Enabled" bitfld.byte 0x00 6. " WUME_6 ,Wakeup module enable for module 6" "Disabled,Enabled" bitfld.byte 0x00 5. " WUME_5 ,Wakeup module enable for module 5" "Disabled,Enabled" bitfld.byte 0x00 4. " WUME_4 ,Wakeup module enable for module 4" "Disabled,Enabled" textline " " bitfld.byte 0x00 3. " WUME_3 ,Wakeup module enable for module 3" "Disabled,Enabled" bitfld.byte 0x00 2. " WUME_2 ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x00 1. " WUME_1 ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x00 0. " WUME_0 ,Wakeup module enable for module 0" "Disabled,Enabled" sif cpuis("*LH*") group.byte 0x05++0x00 line.byte 0x00 "F1,LLWU Flag 1 Register" eventfld.byte 0x00 7. " WUF_7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x00 6. " WUF_6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x00 5. " WUF_5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x00 4. " WUF_4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup" textline " " eventfld.byte 0x00 3. " WUF_3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" eventfld.byte 0x00 0. " WUF_0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup" else group.byte 0x05++0x00 line.byte 0x00 "F1,LLWU Flag 1 Register" eventfld.byte 0x00 7. " WUF_7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x00 6. " WUF_6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x00 5. " WUF_5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x00 3. " WUF_3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" endif sif cpuis("*LH*") group.byte 0x06++0x00 line.byte 0x00 "F2,LLWU Flag 2 Register" eventfld.byte 0x00 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x00 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x00 5. " WUF_13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x00 4. " WUF_12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" textline " " eventfld.byte 0x00 3. " WUF_11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup" eventfld.byte 0x00 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x00 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x00 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" elif cpuis("*LF*") group.byte 0x06++0x00 line.byte 0x00 "F2,LLWU Flag 2 Register" eventfld.byte 0x00 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x00 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x00 5. " WUF_13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x00 4. " WUF_12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" textline " " eventfld.byte 0x00 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x00 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x00 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" else group.byte 0x06++0x00 line.byte 0x00 "F2,LLWU Flag 2 Register" eventfld.byte 0x00 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x00 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x00 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x00 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" textline " " eventfld.byte 0x00 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" endif rgroup.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 Register" bitfld.byte 0x00 7. " MWUF_7 ,Wakeup flag for module 7" "No wakeup,Wakeup" bitfld.byte 0x00 6. " MWUF_6 ,Wakeup flag for module 6" "No wakeup,Wakeup" bitfld.byte 0x00 5. " MWUF_5 ,Wakeup flag for module 5" "No wakeup,Wakeup" bitfld.byte 0x00 4. " MWUF_4 ,Wakeup flag for module 4" "No wakeup,Wakeup" textline " " bitfld.byte 0x00 3. " MWUF_3 ,Wakeup flag for module 3" "No wakeup,Wakeup" bitfld.byte 0x00 2. " MWUF_2 ,Wakeup flag for module 2" "No wakeup,Wakeup" bitfld.byte 0x00 1. " MWUF_1 ,Wakeup flag for module 1" "No wakeup,Wakeup" bitfld.byte 0x00 0. " MWUF_0 ,Wakeup flag for module 0" "No wakeup,Wakeup" else group.byte 0x00++0x06 line.byte 0x00 "PE1,LLWU Pin Enable 1 Register" bitfld.byte 0x00 6.--7. " WUPE_3 ,Wakeup pin enable for LLWU_P3" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLH12*")&&!cpuis("MK22FN256CAH12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FX512AVLH12R") bitfld.byte 0x00 4.--5. " WUPE_2 ,Wakeup pin enable for LLWU_P2" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x00 2.--3. " WUPE_1 ,Wakeup pin enable for LLWU_P1" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" endif textline " " bitfld.byte 0x00 0.--1. " WUPE_0 ,Wakeup pin enable for LLWU_P0" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x01 "PE2,LLWU Pin Enable 2 Register" bitfld.byte 0x01 6.--7. " WUPE_7 ,Wakeup pin enable for LLWU_P7" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 4.--5. " WUPE_6 ,Wakeup pin enable for LLWU_P6" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x01 2.--3. " WUPE_5 ,Wakeup pin enable for LLWU_P5" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x01 0.--1. " WUPE_4 ,Wakeup pin enable for LLWU_P4" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x02 "PE3,LLWU Pin Enable 3 Register" bitfld.byte 0x02 6.--7. " WUPE_11 ,Wakeup pin enable for LLWU_P11" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 4.--5. " WUPE_10 ,Wakeup pin enable for LLWU_P10" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x02 2.--3. " WUPE_9 ,Wakeup pin enable for LLWU_P9" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x02 0.--1. " WUPE_8 ,Wakeup pin enable for LLWU_P8" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" line.byte 0x03 "PE4,LLWU Pin Enable 4 Register" bitfld.byte 0x03 6.--7. " WUPE_15 ,Wakeup pin enable for LLWU_P15" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 4.--5. " WUPE_14 ,Wakeup pin enable for LLWU_P14" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" bitfld.byte 0x03 2.--3. " WUPE_13 ,Wakeup pin enable for LLWU_P13" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " bitfld.byte 0x03 0.--1. " WUPE_12 ,Wakeup pin enable for LLWU_P12" "Disabled as wakeup,Enabled with rising edge,Enabled with falling edge,Enabled with any change" textline " " line.byte 0x04 "ME,LLWU Module Enable Register" bitfld.byte 0x04 7. " WUME_7 ,Wakeup module enable for module 7" "Disabled,Enabled" textline " " sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") bitfld.byte 0x04 6. " WUME_6 ,Wakeup module enable for module 6" "Disabled,Enabled" textline " " endif bitfld.byte 0x04 5. " WUME_5 ,Wakeup module enable for module 5" "Disabled,Enabled" textline " " sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R") bitfld.byte 0x04 4. " WUME_4 ,Wakeup module enable for module 4" "Disabled,Enabled" textline " " endif sif !cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R") bitfld.byte 0x04 3. " WUME_3 ,Wakeup module enable for module 3" "Disabled,Enabled" textline " " endif bitfld.byte 0x04 2. " WUME_2 ,Wakeup module enable for module 2" "Disabled,Enabled" bitfld.byte 0x04 1. " WUME_1 ,Wakeup module enable for module 1" "Disabled,Enabled" bitfld.byte 0x04 0. " WUME_0 ,Wakeup module enable for module 0" "Disabled,Enabled" line.byte 0x05 "F1,LLWU Flag 1 Register" eventfld.byte 0x05 7. " WUF_7 ,Wakeup flag for LLWU_P7" "No wakeup,Wakeup" eventfld.byte 0x05 6. " WUF_6 ,Wakeup flag for LLWU_P6" "No wakeup,Wakeup" eventfld.byte 0x05 5. " WUF_5 ,Wakeup flag for LLWU_P5" "No wakeup,Wakeup" eventfld.byte 0x05 4. " WUF_4 ,Wakeup flag for LLWU_P4" "No wakeup,Wakeup" textline " " eventfld.byte 0x05 3. " WUF_3 ,Wakeup flag for LLWU_P3" "No wakeup,Wakeup" textline " " sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLH12*")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FX512AVLH12R") eventfld.byte 0x05 2. " WUF_2 ,Wakeup flag for LLWU_P2" "No wakeup,Wakeup" eventfld.byte 0x05 1. " WUF_1 ,Wakeup flag for LLWU_P1" "No wakeup,Wakeup" textline " " endif eventfld.byte 0x05 0. " WUF_0 ,Wakeup flag for LLWU_P0" "No wakeup,Wakeup" line.byte 0x06 "F2,LLWU Flag 2 Register" eventfld.byte 0x06 7. " WUF_15 ,Wakeup flag for LLWU_P15" "No wakeup,Wakeup" eventfld.byte 0x06 6. " WUF_14 ,Wakeup flag for LLWU_P14" "No wakeup,Wakeup" eventfld.byte 0x06 5. " WUF_13 ,Wakeup flag for LLWU_P13" "No wakeup,Wakeup" eventfld.byte 0x06 4. " WUF_12 ,Wakeup flag for LLWU_P12" "No wakeup,Wakeup" textline " " eventfld.byte 0x06 3. " WUF_11 ,Wakeup flag for LLWU_P11" "No wakeup,Wakeup" eventfld.byte 0x06 2. " WUF_10 ,Wakeup flag for LLWU_P10" "No wakeup,Wakeup" eventfld.byte 0x06 1. " WUF_9 ,Wakeup flag for LLWU_P9" "No wakeup,Wakeup" eventfld.byte 0x06 0. " WUF_8 ,Wakeup flag for LLWU_P8" "No wakeup,Wakeup" sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*"))||cpuis("MK40D*Z*10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")||cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10")||cpu()==("MK51DN512ZCLL10")||cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10") group.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 Register" eventfld.byte 0x00 7. " MWUF_7 ,Wakeup flag for module 7" "No wakeup,Wakeup" textline " " sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") rbitfld.byte 0x00 6. " MWUF_6 ,Wakeup flag for module 6" "No wakeup,Wakeup" textline " " endif rbitfld.byte 0x00 5. " MWUF_5 ,Wakeup flag for module 5" "No wakeup,Wakeup" rbitfld.byte 0x00 4. " MWUF_4 ,Wakeup flag for module 4" "No wakeup,Wakeup" rbitfld.byte 0x00 3. " MWUF_3 ,Wakeup flag for module 3" "No wakeup,Wakeup" textline " " rbitfld.byte 0x00 2. " MWUF_2 ,Wakeup flag for module 2" "No wakeup,Wakeup" rbitfld.byte 0x00 1. " MWUF_1 ,Wakeup flag for module 1" "No wakeup,Wakeup" rbitfld.byte 0x00 0. " MWUF_0 ,Wakeup flag for module 0" "No wakeup,Wakeup" else rgroup.byte 0x07++0x00 line.byte 0x00 "F3,LLWU Flag 3 Register" bitfld.byte 0x00 7. " MWUF_7 ,Wakeup flag for module 7" "No wakeup,Wakeup" textline " " sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK20DN512VLK10R") bitfld.byte 0x00 6. " MWUF_6 ,Wakeup flag for module 6" "No wakeup,Wakeup" textline " " endif bitfld.byte 0x00 5. " MWUF_5 ,Wakeup flag for module 5" "No wakeup,Wakeup" textline " " sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FX512AVLH12R") bitfld.byte 0x00 4. " MWUF_4 ,Wakeup flag for module 4" "No wakeup,Wakeup" textline " " endif sif !cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R")&&!cpuis("MK21DN512AVMC5R")&&!cpuis("MK21DX256AVMC5R")&&!cpuis("MK22FN128VLH10R") bitfld.byte 0x00 3. " MWUF_3 ,Wakeup flag for module 3" "No wakeup,Wakeup" textline " " endif bitfld.byte 0x00 2. " MWUF_2 ,Wakeup flag for module 2" "No wakeup,Wakeup" bitfld.byte 0x00 1. " MWUF_1 ,Wakeup flag for module 1" "No wakeup,Wakeup" bitfld.byte 0x00 0. " MWUF_0 ,Wakeup flag for module 0" "No wakeup,Wakeup" endif endif textline " " sif (cpuis("MK20D*AB10")||cpuis("MK20DN512*AB10R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R"))||cpuis("MK40D*Z*10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")||cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10")||cpu()==("MK51DN512ZCLL10")||cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10") group.byte 0x08++0x00 line.byte 0x00 "CS,LLWU Control And Status Register" eventfld.byte 0x00 7. " ACKISO ,Acknowledge isolation" "Disabled,Enabled" bitfld.byte 0x00 1. " FLTEP ,Digital filter on external pin" "Disabled,Enabled" bitfld.byte 0x00 0. " FLTR ,Digital filter on RESET pin" "Disabled,Enabled" else sif cpuis("MK02*LH*") group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" elif cpuis("MK02*LF*") group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" elif cpuis("MK02*FM*") group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15" line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" ",,,LLWU_P3,,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,,,,LLWU_P14,LLWU_P15" else group.byte 0x08++0x01 line.byte 0x00 "FILT1,LLWU Pin Filter 1 Register" eventfld.byte 0x00 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x00 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVLH12*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN256VMP12")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN256CAH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN128VLH10R") bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" else bitfld.byte 0x00 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" endif line.byte 0x01 "FILT2,LLWU Pin Filter 2 Register" eventfld.byte 0x01 7. " FILTF ,Filter detect flag" "No wakeup,Wakeup" bitfld.byte 0x01 5.--6. " FILTE ,Digital filter on external pin" "Disabled,Filter posedge,Filter negedge,Filter any edge" sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVLH12*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLH12*")||cpuis("MK22FN256VMP12")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN256CAH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN128VLH10R") bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,,,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" else bitfld.byte 0x01 0.--3. " FILTSEL ,Filter pin select" "LLWU_P0,LLWU_P1,LLWU_P2,LLWU_P3,LLWU_P4,LLWU_P5,LLWU_P6,LLWU_P7,LLWU_P8,LLWU_P9,LLWU_P10,LLWU_P11,LLWU_P12,LLWU_P13,LLWU_P14,LLWU_P15" endif sif !cpuis("MK22FN256*")&&!cpuis("MK22FN128*")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("KK22FN256CAP12R")&&!cpuis("KK22FN512CBP12R")&&!cpuis("MK22FN512V??12*")&&!cpuis("KK22FN128CAH12R")&&!cpuis("KK22FN256CAH12R") group.byte 0x0A++0x00 line.byte 0x00 "RST,LLWU Reset Enable Register" bitfld.byte 0x00 1. " LLRSTE ,Low-leakage mode RESET enable" "Disabled,Enabled" bitfld.byte 0x00 0. " RSTFILT ,Digital filter on RESET pin" "Disabled,Enabled" endif endif endif width 0x0B tree.end tree "MCM (Miscellaneous Control Module)" base ad:0xE0080000 width 8. rgroup.word 0x08++0x03 line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration" bitfld.word 0x00 7. " ASC[7] ,Connection to the crossbar switch's slave input port 7" "Not connected,Connected" bitfld.word 0x00 6. " [6] ,Connection to the crossbar switch's slave input port 6" "Not connected,Connected" bitfld.word 0x00 5. " [5] ,Connection to the crossbar switch's slave input port 5" "Not connected,Connected" bitfld.word 0x00 4. " [4] ,Connection to the crossbar switch's slave input port 4" "Not connected,Connected" newline bitfld.word 0x00 3. " [3] ,Connection to the crossbar switch's slave input port 3" "Not connected,Connected" bitfld.word 0x00 2. " [2] ,Connection to the crossbar switch's slave input port 2" "Not connected,Connected" bitfld.word 0x00 1. " [1] ,Connection to the crossbar switch's slave input port 1" "Not connected,Connected" bitfld.word 0x00 0. " [0] ,Connection to the crossbar switch's slave input port 0" "Not connected,Connected" line.word 0x02 "PLAMC,Crossbar Switch (AXBS) Master Configuration" bitfld.word 0x02 7. " AMC[7] ,Connection to the AXBS master input port 7" "Not connected,Connected" bitfld.word 0x02 6. " [6] ,Connection to the AXBS master input port 6" "Not connected,Connected" bitfld.word 0x02 5. " [5] ,Connection to the AXBS master input port 5" "Not connected,Connected" bitfld.word 0x02 4. " [4] ,Connection to the AXBS master input port 4" "Not connected,Connected" newline bitfld.word 0x02 3. " [3] ,Connection to the AXBS master input port 3" "Not connected,Connected" bitfld.word 0x02 2. " [2] ,Connection to the AXBS master input port 2" "Not connected,Connected" bitfld.word 0x02 1. " [1] ,Connection to the AXBS master input port 1" "Not connected,Connected" bitfld.word 0x02 0. " [0] ,Connection to the AXBS master input port 0" "Not connected,Connected" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7R") group.long 0x0C++0x03 line.long 0x00 "CR,Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" elif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DN512ZVLQ10R"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R") group.long 0x0C++0x03 line.long 0x00 "SRAMAP,SRAM Arbitration And Protection Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Not protected,Protected" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Not protected,Protected" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Processor highest,Backdoor highest" elif cpuis("MK10D*7")||cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK5?D*")||cpuis("MK6*")||cpuis("MK70*") group.long 0x0C++0x03 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 30. " SRAMLWP ,SRAM_L write protect" "Disabled,Enabled" bitfld.long 0x00 28.--29. " SRAMLAP ,SRAM_L arbitration priority" "Round robin,Special round robin,Fixed priority (Hi),Fixed priority (Low)" bitfld.long 0x00 26. " SRAMUWP ,SRAM_U write protect" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " SRAMUAP ,SRAM_U arbitration priority" "Round robin,Special round robin,Fixed priority (Hi),Fixed priority (Low)" sif cpuis("MK61*VMJ*")||cpuis("MK70*") newline bitfld.long 0x00 20.--21. " DDRSIZE ,DDR address size translation" "Disabled,128MB,256MB,512MB" endif else group.long 0x0C++0x03 line.long 0x00 "PLACR,Platform Control Register" bitfld.long 0x00 9. " ARB ,Arbitration select" "Fixed-priority,Round-robin" endif sif cpuis("MK02*") group.long 0x10++0x03 line.long 0x00 "ISCR,Interrupt Status And Control Register" bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" elif cpuis("MK?0D*10")||cpuis("MK10F*12")||cpuis("MK5?D*10")||cpuis("MK6*")||cpuis("MK70*")||cpuis("MK10DN512ZVLK10R")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK30DN512ZVLQ10R") group.long 0x10++0x0B line.long 0x00 "ISR,Interrupt Status Register" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*") bitfld.long 0x00 20. " CWBEE ,Cache write buffer error enable" "Disabled,Enabled" newline endif rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" newline sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*") eventfld.long 0x00 4. " CWBER ,Cache write buffer error status" "Not occurred,Occurred" newline endif endif sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60*AB10")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZCAB10R")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10") rbitfld.long 0x00 3. " DHREQ ,Debug halt request indicator" "Not occurred,Occurred" newline endif eventfld.long 0x00 2. " NMI ,Non-maskable interrupt pending" "Not pending,Pending" eventfld.long 0x00 1. " IRQ ,Normal interrupt pending" "Not pending,Pending" line.long 0x04 "ETBCC,ETB Counter Control Register" bitfld.long 0x04 5. " ITDIS ,ITM-to-TPIU disable" "No,Yes" bitfld.long 0x04 4. " ETDIS ,ETM-to-TPIU disable" "No,Yes" bitfld.long 0x04 3. " RLRQ ,Reload request clear" "No effect,Cleared" newline bitfld.long 0x04 1.--2. " RSPT ,Response type when the ETB count expires" "No response,Normal interrupt,NMI,Debug" bitfld.long 0x04 0. " CNTEN ,Counter enable" "Disabled,Enabled" line.long 0x08 "ETBRL,ETB Reload Register" hexmask.long.word 0x08 0.--10. 1. " RELOAD ,Byte count reload value" rgroup.long 0x1C++0x03 line.long 0x00 "ETBCNT,ETB Counter Value Register" hexmask.long.word 0x00 0.--10. 1. " COUNTER ,Byte count counter value" sif !cpuis("MK63FN1M0VLQ12R") sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "Not occurred,Occurred" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" endif endif sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK60*AB10")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10") group.long 0x30++0x03 line.long 0x00 "PID,Process ID Register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID and M1_PID for MPU" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15") group.long 0x10++0x03 line.long 0x00 "ISCR,Interrupt Status Register" bitfld.long 0x00 31. " FIDCE ,FPU input denormal interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " FIXCE ,FPU inexact interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " FUFCE ,FPU underflow interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " FOFCE ,FPU overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " FDZCE ,FPU divide-by-zero interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " FIOCE ,FPU invalid operation interrupt enable" "Disabled,Enabled" newline rbitfld.long 0x00 15. " FIDC ,FPU input denormal interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 12. " FIXC ,FPU inexact interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 11. " FUFC ,FPU underflow interrupt status" "Not occurred,Occurred" newline rbitfld.long 0x00 10. " FOFC ,FPU overflow interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 9. " FDZC ,FPU divide-by-zero interrupt status" "Not occurred,Occurred" rbitfld.long 0x00 8. " FIOC ,FPU invalid operation interrupt status" "Not occurred,Occurred" sif !cpuis("MK60FN1M0VLQ15") newline rbitfld.long 0x00 6. " WABORTS_OVERRUN ,WABORTS assertion overrun" "No overrun,Overrun" rbitfld.long 0x00 5. " WABORTS ,WABORTS imprecise write fault from the TCM backdoor" "Not occurred,Occurred" else newline eventfld.long 0x00 4. " CWBER ,Cache write buffer error status" "Not occurred,Occurred" rbitfld.long 0x00 3. " DHREQ ,Debug halt request indicator" "Not requested,Initiated request" eventfld.long 0x00 2. " NMI ,Not maskable interrupt pending" "No pending,Pending" newline eventfld.long 0x00 1. " IRQ ,Normal interrupt pending" "No pending,Pending" endif sif cpuis("MK60FN1M0VLQ15") group.long 0x14++0x0B line.long 0x00 "ETBCC,ETB Counter Control Register" bitfld.long 0x00 5. " ITDIS ,ITM-to-TPIU disable" "No,Yes" bitfld.long 0x00 4. " ETDIS ,ETM-to-TPIU disable" "No,Yes" bitfld.long 0x00 3. " RLRQ ,Reload request clear" "No effect,Cleared" newline bitfld.long 0x00 1.--2. " RSPT ,Response type when the ETB count expires" "No response,Normal interrupt,NMI,Debug" bitfld.long 0x00 0. " CNTEN ,Counter enable" "Disabled,Enabled" line.long 0x04 "ETBRL,ETB Reload Register" hexmask.long.word 0x04 0.--10. 1. " RELOAD ,Byte count reload value" line.long 0x08 "ETBCNT,ETB Counter Value Register" hexmask.long.word 0x08 0.--10. 1. " COUNTER ,Byte count counter value" endif rgroup.long 0x20++0x0B line.long 0x00 "FADR,Fault Address Register" line.long 0x04 "FATR,Fault Attributes Register" bitfld.long 0x04 31. " BEOVR ,Bus error overrun" "Not occurred,Occurred" bitfld.long 0x04 8.--11. " BEMN ,Bus error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 7. " BEWT ,Bus error write" "Read,Write" newline bitfld.long 0x04 4.--5. " BESZ ,Bus error size" "8-bit,16-bit,32-bit,?..." bitfld.long 0x04 1. " BEMD ,Bus error privilege level" "User mode,Supervisor mode" bitfld.long 0x04 0. " BEDA ,Bus error access type" "Instruction,Data" line.long 0x08 "FDR,Fault Data Register" group.long 0x30++0x03 line.long 0x00 "PID,Process ID Register" hexmask.long.byte 0x00 0.--7. 1. " PID ,M0_PID and M1_PID for MPU" sif !cpuis("MK60FN1M0VLQ15") group.long 0x40++0x03 line.long 0x00 "CPO,Compute Operation Control Register" bitfld.long 0x00 2. " CPOWOI ,Compute operation wakeup on interrupt" "No effect,Clr CPOREQ on int." rbitfld.long 0x00 1. " CPOACK ,Compute operation acknowledge" "Completed,Not completed" bitfld.long 0x00 0. " CPOREQ ,Compute operation request" "Not requested,Requested" endif endif width 0x0B tree.end tree "AXBS (Crossbar Switch)" base ad:0x40004000 width 9. sif cpuis("MK26F*") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512ZVLQ10") sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x0+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x100+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x200+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x300+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x400+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x500+0x10))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 28.--30. " ETH ,Ethernet priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " USB_HS ,USB_HS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " SDHC/NFC/USB_FS ,SDHC/NFC/USB_FS priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " DMA/EzPort ,DMA/EzPort priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " ARM_CSB ,ARM core system bus priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " ARM_CCB ,ARM core code bus priority" "Highest,2,3,4,5,6,7,Lowest" else sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" endif rgroup.long (0x500+0x10)++0x03 sif !cpuis("KK60FN1M0VLQ15") line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,?..." else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else if (((per.l(ad:0x40004000+0x0+0x10))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x100+0x10))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x200+0x10))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x300+0x10))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x400+0x10))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif if (((per.l(ad:0x40004000+0x500+0x10))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK60DN512ZVLQ10") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif sif !cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/Write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK24F*DC12")||cpuis("MK24F*LQ12") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif (cpuis("MK22F*LQ12")&&!cpuis("MK22FX512AVLQ12"))||cpuis("MK21F*MC12")||cpuis("MK21F*MD")||cpuis("MK21F*LQ") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DN512ZCAB10R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read Only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,,Port M4,Port M5,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK20FN1M0VLQ12R") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,,,Port M6,?..." endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register 0 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register 0" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register 1 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register 1" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register 2 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register 2" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register 3 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register 3" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register 4 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register 4" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register 5 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register 5" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register 6 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register 6" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register 7 Slave" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register 7" bitfld.long 0x00 31. " RO ,Read only" "Read/write,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Highest,Lowest" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin/rotating,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register 0" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register 1" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register 2" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register 3" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register 4" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register 5" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register 6" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register 7" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." elif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif if (((per.l(ad:0x40004000+0x10+0x500))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." else sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x0))&0x80000000)==0x80000000) rgroup.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x0++0x03 line.long 0x00 "PRS0,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x0+0x10)++0x03 line.long 0x00 "CRS0,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x100))&0x80000000)==0x80000000) rgroup.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x100++0x03 line.long 0x00 "PRS1,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x100+0x10)++0x03 line.long 0x00 "CRS1,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x200))&0x80000000)==0x80000000) rgroup.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x200++0x03 line.long 0x00 "PRS2,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x200+0x10)++0x03 line.long 0x00 "CRS2,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x300))&0x80000000)==0x80000000) rgroup.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x300++0x03 line.long 0x00 "PRS3,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x300+0x10)++0x03 line.long 0x00 "CRS3,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x400))&0x80000000)==0x80000000) rgroup.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x400++0x03 line.long 0x00 "PRS4,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x400+0x10)++0x03 line.long 0x00 "CRS4,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x500))&0x80000000)==0x80000000) rgroup.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x500++0x03 line.long 0x00 "PRS5,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x500+0x10)++0x03 line.long 0x00 "CRS5,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x600))&0x80000000)==0x80000000) rgroup.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x600++0x03 line.long 0x00 "PRS6,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x600+0x10)++0x03 line.long 0x00 "CRS6,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif sif cpuis("MK40D*Z*")||cpuis("MK20D????ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.l(ad:0x40004000+0x10+0x700))&0x80000000)==0x80000000) rgroup.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" rgroup.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif else group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif !cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") sif !cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" sif !cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0*12R")&&!cpuis("MK22FX512*12R") bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" endif bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." sif cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0*12R")||cpuis("MK22FX512*12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" else bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,?..." endif endif else group.long 0x700++0x03 line.long 0x00 "PRS7,Priority Register Slave" sif cpuis("MK?0F*")||cpuis("MK?0D*7")||cpuis("MK?0D*10")||cpuis("MK5?D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK30DN512ZVLQ10R") sif cpuis("MK65F*")||cpuis("MK66F*") bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,Lowest,?..." elif !cpuis("MK20D*AB10")&&!cpuis("MK21F*")&&!cpuis("MK60D*AB10")&&!cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 28.--30. " M7 ,Master 7 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 24.--26. " M6 ,Master 6 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" elif cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 12.--14. " M3 ,Master 3 priority" "Highest,2,3,4,5,6,7,Lowest" newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,5,6,7,Lowest" bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,5,6,7,Lowest" else bitfld.long 0x00 20.--22. " M5 ,Master 5 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 16.--18. " M4 ,Master 4 priority" "Highest,2,3,4,Lowest,?..." newline bitfld.long 0x00 8.--10. " M2 ,Master 2 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 4.--6. " M1 ,Master 1 priority" "Highest,2,3,4,Lowest,?..." bitfld.long 0x00 0.--2. " M0 ,Master 0 priority" "Highest,2,3,4,Lowest,?..." endif group.long (0x700+0x10)++0x03 line.long 0x00 "CRS7,Control Register" bitfld.long 0x00 31. " RO ,Read only" "Writable,Read only" bitfld.long 0x00 30. " HLP ,Halt low priority" "Not halted,Halted" bitfld.long 0x00 8.--9. " ARB ,Arbitration mode" "Fixed,Round-robin,?..." bitfld.long 0x00 4.--5. " PCTL ,Parking control" "Master port (PARK),Last master of slave,Not parked,?..." newline bitfld.long 0x00 0.--2. " PARK ,PARK master port" "Port M0,Port M1,Port M2,Port M3,Port M4,Port M5,Port M6,Port M7" endif group.long 0x800++0x03 line.long 0x00 "MGPCR0,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0x900++0x03 line.long 0x00 "MGPCR1,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xA00++0x03 line.long 0x00 "MGPCR2,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xB00++0x03 line.long 0x00 "MGPCR3,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xC00++0x03 line.long 0x00 "MGPCR4,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xD00++0x03 line.long 0x00 "MGPCR5,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xE00++0x03 line.long 0x00 "MGPCR6,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." group.long 0xF00++0x03 line.long 0x00 "MGPCR7,Master General Purpose Control Register" bitfld.long 0x00 0.--2. " AULB ,Arbitrate on undefined length bursts" "No arbitration,Any time,After 4 beats,After 8 beats,After 16 beats,?..." endif width 0x0B tree.end tree "MPU (Memory Protection Unit)" base ad:0x4000D000 width 13. group.long 0x00++0x03 line.long 0x00 "CESR,Control/Error Status Register" eventfld.long 0x00 31. " SPERR[0] ,Slave port 0 error" "No error,Error" eventfld.long 0x00 30. " SPERR[1] ,Slave port 1 error" "No error,Error" newline eventfld.long 0x00 29. " SPERR[2] ,Slave port 2 error" "No error,Error" eventfld.long 0x00 28. " SPERR[3] ,Slave port 3 error" "No error,Error" newline sif !cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10") eventfld.long 0x00 27. " SPERR[4] ,Slave port 4 error" "No error,Error" newline endif sif cpuis("MK??F*")||cpuis("KK28FN2M0CAU15R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK20DN512*AB10R")&&!cpuis("MK21F*")&&!cpuis("MK22FX512*")&&!cpuis("MK24FN*")&&!cpuis("MK26FN*")&&!cpuis("MK10F*")&&!cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK65FN2M0CAC18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline sif !cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15") eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" newline endif elif cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") eventfld.long 0x00 26. " SPERR[5] ,Slave port 5 error" "No error,Error" sif !cpuis("MK63FN1M0VLQ12R") eventfld.long 0x00 25. " SPERR[6] ,Slave port 6 error" "No error,Error" newline eventfld.long 0x00 24. " SPERR[7] ,Slave port 7 error" "No error,Error" endif endif endif rbitfld.long 0x00 16.--19. " HRL ,Hardware revision level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK70F*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,6,7,?..." elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12*")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,?..." elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18*")||cpuis("MK66FN2M0VLQ18*") rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,Three MPU slave ports,?..." else newline rbitfld.long 0x00 12.--15. " NSP ,Number of slave ports" "0,1,2,3,4,5,?..." endif newline rbitfld.long 0x00 8.--11. " NRGD ,Number of region descriptors" "8,12,16,?..." bitfld.long 0x00 0. " VLD ,Valid (global enable/disable for the MPU)" "Disabled,Enabled" newline sif cpuis("MK70*") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." rgroup.long 0x48++0x07 line.long 0x00 "EAR7,Error Address Register" line.long 0x04 "EDR7,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." elif cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x40++0x07 line.long 0x00 "EAR6,Error Address Register" line.long 0x04 "EDR6,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x38++0x07 line.long 0x00 "EAR5,Error Address Register" line.long 0x04 "EDR5,Error Detail Register" hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK65FN2M0VMI18R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" else rgroup.long 0x10++0x07 line.long 0x00 "EAR0,Error Address Register" line.long 0x04 "EDR0,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x18++0x07 line.long 0x00 "EAR1,Error Address Register" line.long 0x04 "EDR1,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x20++0x07 line.long 0x00 "EAR2,Error Address Register" line.long 0x04 "EDR2,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x28++0x07 line.long 0x00 "EAR3,Error Address Register" line.long 0x04 "EDR3,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" rgroup.long 0x30++0x07 line.long 0x00 "EAR4,Error Address Register" line.long 0x04 "EDR4,Error Detail Register" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15") hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") hexmask.long.byte 0x04 8.--15. 1. " EPID ,Error process identification" endif newline bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline else hexmask.long.word 0x04 16.--31. 1. " EACD ,Error access control detail" bitfld.long 0x04 4.--7. " EMN ,Error master number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 1.--3. " EATTR ,Error attributes access" "User/Instruction,User/Data,Supervisor/Instruction,Supervisor/Data,?..." newline endif bitfld.long 0x04 0. " ERW ,Error read/write" "Read,Write" endif newline group.long 0x400++0x0F line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD0_WORD1,Region Descriptor 0 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD0_WORD2,Region Descriptor 0 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD0_WORD3,Region Descriptor 0 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x410++0x0F line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD1_WORD1,Region Descriptor 1 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD1_WORD2,Region Descriptor 1 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD1_WORD3,Region Descriptor 1 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x420++0x0F line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD2_WORD1,Region Descriptor 2 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD2_WORD2,Region Descriptor 2 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD2_WORD3,Region Descriptor 2 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x430++0x0F line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD3_WORD1,Region Descriptor 3 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD3_WORD2,Region Descriptor 3 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD3_WORD3,Region Descriptor 3 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x440++0x0F line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD4_WORD1,Region Descriptor 4 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD4_WORD2,Region Descriptor 4 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD4_WORD3,Region Descriptor 4 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x450++0x0F line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD5_WORD1,Region Descriptor 5 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD5_WORD2,Region Descriptor 5 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD5_WORD3,Region Descriptor 5 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x460++0x0F line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD6_WORD1,Region Descriptor 6 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD6_WORD2,Region Descriptor 6 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD6_WORD3,Region Descriptor 6 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x470++0x0F line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD7_WORD1,Region Descriptor 7 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD7_WORD2,Region Descriptor 7 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD7_WORD3,Region Descriptor 7 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x480++0x0F line.long 0x00 "RGD8_WORD0,Region Descriptor 8 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD8_WORD1,Region Descriptor 8 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD8_WORD2,Region Descriptor 8 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD8_WORD3,Region Descriptor 8 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x490++0x0F line.long 0x00 "RGD9_WORD0,Region Descriptor 9 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD9_WORD1,Region Descriptor 9 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD9_WORD2,Region Descriptor 9 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD9_WORD3,Region Descriptor 9 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4A0++0x0F line.long 0x00 "RGD10_WORD0,Region Descriptor 10 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD10_WORD1,Region Descriptor 10 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD10_WORD2,Region Descriptor 10 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD10_WORD3,Region Descriptor 10 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4B0++0x0F line.long 0x00 "RGD11_WORD0,Region Descriptor 11 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD11_WORD1,Region Descriptor 11 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD11_WORD2,Region Descriptor 11 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD11_WORD3,Region Descriptor 11 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4C0++0x0F line.long 0x00 "RGD12_WORD0,Region Descriptor 12 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD12_WORD1,Region Descriptor 12 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD12_WORD2,Region Descriptor 12 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD12_WORD3,Region Descriptor 12 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4D0++0x0F line.long 0x00 "RGD13_WORD0,Region Descriptor 13 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD13_WORD1,Region Descriptor 13 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD13_WORD2,Region Descriptor 13 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD13_WORD3,Region Descriptor 13 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4E0++0x0F line.long 0x00 "RGD14_WORD0,Region Descriptor 14 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD14_WORD1,Region Descriptor 14 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD14_WORD2,Region Descriptor 14 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD14_WORD3,Region Descriptor 14 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x4F0++0x0F line.long 0x00 "RGD15_WORD0,Region Descriptor 15 Word 0" hexmask.long 0x00 5.--31. 0x20 " SRTADDR ,Start address" line.long 0x04 "RGD15_WORD1,Region Descriptor 15 Word 1" hexmask.long 0x04 5.--31. 0x20 " ENDADDR ,End address" line.long 0x08 "RGD15_WORD2,Region Descriptor 15 Word 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x08 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x08 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x08 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x08 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x08 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x08 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x08 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x08 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x08 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x08 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x08 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x08 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 17. " M2PE ,DMA process identifier enable" "Disabled,Enabled" bitfld.long 0x08 15.--16. " M2SM ,DMA supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,DMA user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,DMA user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,DMA user mode execute access control" "No access,Access" newline else bitfld.long 0x08 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x08 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x08 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x08 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x08 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x08 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x08 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x08 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x08 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x08 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x08 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x08 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x08 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x08 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x08 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif line.long 0x0C "RGD15_WORD3,Region Descriptor 15 Word 3" sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x0C 24.--31. 1. " PID ,Process identifier" hexmask.long.byte 0x0C 16.--23. 1. " PIDMASK ,Process identifier mask" newline endif bitfld.long 0x0C 0. " VLD ,Signals the region descriptor" "Not valid,Valid" newline group.long 0x800++0x03 line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x804++0x03 line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x808++0x03 line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x80C++0x03 line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x810++0x03 line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x814++0x03 line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x818++0x03 line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x81C++0x03 line.long 0x00 "RGDAAC7,Region Descriptor Alternate Access Control 7" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x820++0x03 line.long 0x00 "RGDAAC8,Region Descriptor Alternate Access Control 8" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x824++0x03 line.long 0x00 "RGDAAC9,Region Descriptor Alternate Access Control 9" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x828++0x03 line.long 0x00 "RGDAAC10,Region Descriptor Alternate Access Control 10" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x82C++0x03 line.long 0x00 "RGDAAC11,Region Descriptor Alternate Access Control 11" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x830++0x03 line.long 0x00 "RGDAAC12,Region Descriptor Alternate Access Control 12" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x834++0x03 line.long 0x00 "RGDAAC13,Region Descriptor Alternate Access Control 13" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x838++0x03 line.long 0x00 "RGDAAC14,Region Descriptor Alternate Access Control 14" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif group.long 0x83C++0x03 line.long 0x00 "RGDAAC15,Region Descriptor Alternate Access Control 15" sif !cpuis("MK22FN1M0VMC10")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R") sif !cpuis("KK26FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 31. " M7RE ,Bus master 7 read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,Bus master 7 write enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " M7RE ,ENET read enable" "Disabled,Enabled" bitfld.long 0x00 30. " M7WE ,ENET write enable" "Disabled,Enabled" endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 29. " M6RE ,Bus master 6 read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,Bus master 6 write enable" "Disabled,Enabled" else bitfld.long 0x00 29. " M6RE ,USB HS read enable" "Disabled,Enabled" bitfld.long 0x00 28. " M6WE ,USB HS write enable" "Disabled,Enabled" endif newline endif sif !cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 27. " M5RE ,Bus master 5 read enable" "Disabled,Enabled" bitfld.long 0x00 26. " M5WE ,Bus master 5 write enable" "Disabled,Enabled" newline endif sif !cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 25. " M4RE ,Bus master 4 read enable" "Disabled,Enabled" bitfld.long 0x00 24. " M4WE ,Bus master 4 write enable" "Disabled,Enabled" newline endif sif !cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R") sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 23. " M3PE ,Bus master 3 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 23. " M3PE ,SDHC/NFC/USB FS identifier enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " M3SM ,SDHC/NFC/USB FS supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,SDHC/NFC/USB FS user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,SDHC/NFC/USB FS user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,SDHC/NFC/USB FS user mode execute access control" "No access,Access" newline else bitfld.long 0x00 21.--22. " M3SM ,Bus master 3 supervisor mode access control" "R/W/X,R/X,R/W,M3UM" bitfld.long 0x00 20. " M3UM[2] ,Bus master 3 user mode read access control" "No access,Access" bitfld.long 0x00 19. " M3UM[1] ,Bus master 3 user mode write access control" "No access,Access" bitfld.long 0x00 18. " M3UM[0] ,Bus master 3 user mode execute access control" "No access,Access" newline endif endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " M2PE ,Bus master 2 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M2PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M2SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M2UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M2UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M2UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 15.--16. " M2SM ,Bus master 2 supervisor mode access control" "R/W/X,R/X,R/W,M2UM" bitfld.long 0x00 14. " M2UM[2] ,Bus master 2 user mode read access control" "No access,Access" bitfld.long 0x00 13. " M2UM[1] ,Bus master 2 user mode write access control" "No access,Access" bitfld.long 0x00 12. " M2UM[0] ,Bus master 2 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 11. " M1PE ,Bus master 1 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 11. " M1PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 9.--10. " M1SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Debugger user mode execute access control" "No access,Access" newline else bitfld.long 0x00 9.--10. " M1SM ,Bus master 1 supervisor mode access control" "R/W/X,R/X,R/W,M1UM" bitfld.long 0x00 8. " M1UM[2] ,Bus master 1 user mode read access control" "No access,Access" bitfld.long 0x00 7. " M1UM[1] ,Bus master 1 user mode write access control" "No access,Access" bitfld.long 0x00 6. " M1UM[0] ,Bus master 1 user mode execute access control" "No access,Access" newline endif sif cpuis("MK?0*12")||cpuis("MK6?*12")||cpuis("MK6?*15")||cpuis("MK70*")||cpuis("MK21F*")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MKV58F1M0V??24")||cpuis("MKV58F512V??24")||cpuis("MKV56F1M0V??24")||cpuis("MKV58F512??24")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVLH12")||cpuis("MKL82Z*")||cpuis("MK60FN1M0VLQ15")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 5. " M0PE ,Bus master 0 process identifier enable" "Disabled,Enabled" newline elif cpuis("KK60FN1M0VLQ15")||cpuis("MK8?FN256V*") bitfld.long 0x00 5. " M0PE ,Debugger process identifier enable" "Disabled,Enabled" bitfld.long 0x00 3.--4. " M0SM ,Debugger supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Debugger user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Debugger user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Debugger user mode execute access control" "No access,Access" else bitfld.long 0x00 3.--4. " M0SM ,Bus master 0 supervisor mode access control" "R/W/X,R/X,R/W,M0UM" bitfld.long 0x00 2. " M0UM[2] ,Bus master 0 user mode read access control" "No access,Access" bitfld.long 0x00 1. " M0UM[1] ,Bus master 0 user mode write access control" "No access,Access" bitfld.long 0x00 0. " M0UM[0] ,Bus master 0 user mode execute access control" "No access,Access" endif width 0x0B tree.end tree.open "Peripheral Bridge" tree "AIPS-Lite 0" base ad:0x40000000 width 7. group.long 0x00++0x03 line.long 0x00 "MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 26. " MTR1 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW1 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 22. " MTR2 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL2 ,Master privilege level" "Not forced,Forced" sif (!cpuis("MK30DX256VLL7*")) textline " " bitfld.long 0x00 18. " MTR3 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW3 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL3 ,Master privilege level" "Not forced,Forced" sif !cpuis("MK?0D*7") textline " " bitfld.long 0x00 14. " MTR4 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW4 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL4 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 10. " MTR5 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW5 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL5 ,Master privilege level" "Not forced,Forced" sif !cpuis("MK?0D*10*")&&!cpuis("MK60DN512ZVLQ10R") textline " " bitfld.long 0x00 6. " MTR6 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 5. " MTW6 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 4. " MPL6 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 2. " MTR7 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 1. " MTW7 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 0. " MPL7 ,Master privilege level" "Not forced,Forced" endif endif endif textline " " group.long 0x20++0x07 line.long 0x00 "PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect (AIPS-Lite 0)" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect (AIPS-Lite 0)" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect (AIPS-Lite 0)" "Disabled,Enabled" sif !cpuis("MK11D*")&&!cpuis("MK12D*") textline " " bitfld.long 0x00 14. " SP4 ,Supervisor protect (Crossbar switch)" "Disabled,Enabled" bitfld.long 0x00 13. " WP4 ,Write protect (Crossbar switch)" "Disabled,Enabled" bitfld.long 0x00 12. " TP4 ,Trusted protect (Crossbar switch)" "Disabled,Enabled" endif line.long 0x04 "PACRB,Peripheral Access Control Register" bitfld.long 0x04 30. " SP8 ,Supervisor protect (DMA Controller)" "Disabled,Enabled" bitfld.long 0x04 29. " WP8 ,Write protect (DMA Controller)" "Disabled,Enabled" bitfld.long 0x04 28. " TP8 ,Trusted protect (DMA Controller)" "Disabled,Enabled" textline " " bitfld.long 0x04 26. " SP9 ,Supervisor protect (DMA controller transfer control descriptors)" "Disabled,Enabled" bitfld.long 0x04 25. " WP9 ,Write protect (DMA controller transfer control descriptors)" "Disabled,Enabled" bitfld.long 0x04 24. " TP9 ,Trusted protect (DMA controller transfer control descriptors)" "Disabled,Enabled" sif cpuis("MK10D*7")||cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*VLQ10")||cpuis("MK30D*VMD10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK40D*VLQ10")||cpuis("MK40D*VMD10")||cpuis("MK52D*")||cpuis("MK51D*CLQ10")||cpuis("MK51D*CMD10")||cpuis("MK50D*")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10") sif !cpuis("MK40*ZVLL10") textline " " bitfld.long 0x04 14. " SP12 ,Supervisor protect (Flexbus)" "Disabled,Enabled" bitfld.long 0x04 13. " WP12 ,Write protect (Flexbus)" "Disabled,Enabled" bitfld.long 0x04 12. " TP12 ,Trusted protect (Flexbus)" "Disabled,Enabled" endif endif sif cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*10")||cpuis("MK50D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK40D*10")||cpuis("MK52D*")||cpuis("MK51D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10") textline " " bitfld.long 0x04 10. " SP13 ,Supervisor protect (MPU)" "Disabled,Enabled" bitfld.long 0x04 9. " WP13 ,Write protect (MPU)" "Disabled,Enabled" bitfld.long 0x04 8. " TP13 ,Trusted protect (MPU)" "Disabled,Enabled" endif group.long 0x2C++0x03 line.long 0x00 "PACRD,Peripheral Access Control Register" bitfld.long 0x00 2. " SP31 ,Supervisor protect (Flash memory controller)" "Disabled,Enabled" bitfld.long 0x00 1. " WP31 ,Write protect (Flash memory controller)" "Disabled,Enabled" bitfld.long 0x00 0. " TP31 ,Trusted protect (Flash memory controller)" "Disabled,Enabled" group.long 0x40++0x1B line.long 0x00 "PACRE,Peripheral Access Control Register" bitfld.long 0x00 30. " SP32 ,Supervisor protect (Flash memory)" "Disabled,Enabled" bitfld.long 0x00 29. " WP32 ,Write protect (Flash memory)" "Disabled,Enabled" bitfld.long 0x00 28. " TP32 ,Trusted protect (Flash memory)" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " SP33 ,Supervisor protect (DMA channel multiplexer 0)" "Disabled,Enabled" bitfld.long 0x00 25. " WP33 ,Write protect (DMA channel multiplexer 0)" "Disabled,Enabled" bitfld.long 0x00 24. " TP33 ,Trusted protect (DMA channel multiplexer 0)" "Disabled,Enabled" sif cpuis("MK70*")||cpuis("MK10FN1M0VLQ12")||cpuis("MK10FN1M0VMD12")||cpuis("MK10FX512VLQ12")||cpuis("MK10FX512VMD12")||cpuis("MK6?F*") textline " " bitfld.long 0x00 22. " SP34 ,Supervisor protect (DMA channel multiplexer 1)" "Disabled,Enabled" bitfld.long 0x00 21. " WP34 ,Write protect (DMA channel multiplexer 1)" "Disabled,Enabled" bitfld.long 0x00 20. " TP34 ,Trusted protect (DMA channel multiplexer 1)" "Disabled,Enabled" endif sif cpuis("MK10D*7")||cpuis("MK10F*12")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK10D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") textline " " bitfld.long 0x00 14. " SP36 ,Supervisor protect (FlexCAN 0)" "Disabled,Enabled" bitfld.long 0x00 13. " WP36 ,Write protect (FlexCAN 0)" "Disabled,Enabled" bitfld.long 0x00 12. " TP36 ,Trusted protect (FlexCAN 0)" "Disabled,Enabled" endif line.long 0x04 "PACRF,Peripheral Access Control Register" bitfld.long 0x04 14. " SP44 ,Supervisor protect (SPI 0)" "Disabled,Enabled" bitfld.long 0x04 13. " WP44 ,Write protect (SPI 0)" "Disabled,Enabled" bitfld.long 0x04 12. " TP44 ,Trusted protect (SPI 0)" "Disabled,Enabled" sif cpuis("MK10D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK10D*7")||cpuis("MK10F*12")||cpuis("MK11D*")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK5?D*")||cpuis("MK6?*")||cpuis("MK70*") textline " " bitfld.long 0x04 10. " SP45 ,Supervisor protect (SPI 1)" "Disabled,Enabled" bitfld.long 0x04 9. " WP45 ,Write protect (SPI 1)" "Disabled,Enabled" bitfld.long 0x04 8. " TP45 ,Trusted protect (SPI 1)" "Disabled,Enabled" endif textline " " bitfld.long 0x04 2. " SP47 ,Supervisor protect (I2S 0)" "Disabled,Enabled" bitfld.long 0x04 1. " WP47 ,Write protect (I2S 0)" "Disabled,Enabled" bitfld.long 0x04 0. " TP47 ,Trusted protect (I2S 0)" "Disabled,Enabled" line.long 0x08 "PACRG,Peripheral Access Control Register" bitfld.long 0x08 22. " SP50 ,Supervisor protect (CRC)" "Disabled,Enabled" bitfld.long 0x08 21. " WP50 ,Write protect (CRC)" "Disabled,Enabled" bitfld.long 0x08 20. " TP50 ,Trusted protect (CRC)" "Disabled,Enabled" sif cpuis("MK6?*")||cpuis("MK70*") sif !cpuis("MK60*10") textline " " bitfld.long 0x08 14. " SP52 ,Supervisor protect (USB OTG)" "Disabled,Enabled" bitfld.long 0x08 13. " WP52 ,Write protect (USB OTG)" "Disabled,Enabled" bitfld.long 0x08 12. " TP52 ,Trusted protect (USB OTG)" "Disabled,Enabled" endif endif sif cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK40D*")||cpuis("MK5?*")||cpuis("MK6?*")||cpuis("MK70*") textline " " bitfld.long 0x08 10. " SP53 ,Supervisor protect (USB DCD)" "Disabled,Enabled" bitfld.long 0x08 9. " WP53 ,Write protect (USB DCD)" "Disabled,Enabled" bitfld.long 0x08 8. " TP53 ,Trusted protect (USB DCD)" "Disabled,Enabled" endif textline " " bitfld.long 0x08 6. " SP54 ,Supervisor protect (PDB)" "Disabled,Enabled" bitfld.long 0x08 5. " WP54 ,Write protect (PDB)" "Disabled,Enabled" bitfld.long 0x08 4. " TP54 ,Trusted protect (PDB)" "Disabled,Enabled" textline " " bitfld.long 0x08 2. " SP55 ,Supervisor protect (PIT)" "Disabled,Enabled" bitfld.long 0x08 1. " WP55 ,Write protect (PIT)" "Disabled,Enabled" bitfld.long 0x08 0. " TP55 ,Trusted protect (PIT)" "Disabled,Enabled" line.long 0x0C "PACRH,Peripheral Access Control Register" bitfld.long 0x0C 30. " SP56 ,Supervisor protect (Flex Timer FTM 0)" "Disabled,Enabled" bitfld.long 0x0C 29. " WP56 ,Write protect (Flex Timer FTM 0)" "Disabled,Enabled" bitfld.long 0x0C 28. " TP56 ,Trusted protect (Flex Timer FTM 0) " "Disabled,Enabled" textline " " bitfld.long 0x0C 26. " SP57 ,Supervisor protect (Flex Timer FTM 1)" "Disabled,Enabled" bitfld.long 0x0C 25. " WP57 ,Write protect (Flex Timer FTM 1)" "Disabled,Enabled" bitfld.long 0x0C 24. " TP57 ,Trusted protect (Flex Timer FTM 1) " "Disabled,Enabled" textline " " bitfld.long 0x0C 18. " SP59 ,Supervisor protect (ADC 0)" "Disabled,Enabled" bitfld.long 0x0C 17. " WP59 ,Write protect (ADC 0)" "Disabled,Enabled" bitfld.long 0x0C 16. " TP59 ,Trusted protect (ADC 0)" "Disabled,Enabled" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") textline " " bitfld.long 0x0C 14. " SP60 ,Supervisor protect (ADC 2)" "Disabled,Enabled" bitfld.long 0x0C 13. " WP60 ,Write protect (ADC 2)" "Disabled,Enabled" bitfld.long 0x0C 12. " TP60 ,Trusted protect (ADC 2)" "Disabled,Enabled" endif textline " " bitfld.long 0x0C 10. " SP61 ,Supervisor protect (RTC)" "Disabled,Enabled" bitfld.long 0x0C 9. " WP61 ,Write protect (RTC)" "Disabled,Enabled" bitfld.long 0x0C 8. " TP61 ,Trusted protect (RTC)" "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " SP62 ,Supervisor protect (VBAT)" "Disabled,Enabled" bitfld.long 0x0C 5. " WP62 ,Write protect (VBAT)" "Disabled,Enabled" bitfld.long 0x0C 4. " TP62 ,Trusted protect (VBAT)" "Disabled,Enabled" line.long 0x10 "PACRI,Peripheral Access Control Register" bitfld.long 0x10 30. " SP64 ,Supervisor protect (Low power Timer)" "Disabled,Enabled" bitfld.long 0x10 29. " WP64 ,Write protect (Low power Timer)" "Disabled,Enabled" bitfld.long 0x10 28. " TP64 ,Trusted protect (Low power Timer) " "Disabled,Enabled" textline " " bitfld.long 0x10 26. " SP65 ,Supervisor protect (System register)" "Disabled,Enabled" bitfld.long 0x10 25. " WP65 ,Write protect (System register)" "Disabled,Enabled" bitfld.long 0x10 24. " TP65 ,Trusted protect (System register) " "Disabled,Enabled" sif cpuis("MK61*")||cpuis("MK70*")||cpuis("MK40D*ZVLL10")||cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10") sif !cpuis("MK70FN1M0VMJ12")&&!cpuis("MK70FN1M0VMJ15") textline " " bitfld.long 0x10 22. " SP66 ,Supervisor protect (DryIce)" "Disabled,Enabled" bitfld.long 0x10 21. " WP66 ,Write protect (DryIce)" "Disabled,Enabled" bitfld.long 0x10 20. " TP66 ,Trusted protect (DryIce) " "Disabled,Enabled" textline " " bitfld.long 0x10 18. " SP67 ,Supervisor protect (DryIce secure storage)" "Disabled,Enabled" bitfld.long 0x10 17. " WP67 ,Write protect (DryIce secure storage)" "Disabled,Enabled" bitfld.long 0x10 16. " TP67 ,Trusted protect (DryIce secure storage) " "Disabled,Enabled" endif endif sif !cpuis("MK11D*")&&!cpuis("MK12D*") textline " " bitfld.long 0x10 10. " SP69 ,Supervisor protect (TSI)" "Disabled,Enabled" bitfld.long 0x10 9. " WP69 ,Write protect (TSI)" "Disabled,Enabled" bitfld.long 0x10 8. " TP69 ,Trusted protect (TSI)" "Disabled,Enabled" endif textline " " bitfld.long 0x10 2. " SP71 ,Supervisor protect (SIM low power logic)" "Disabled,Enabled" bitfld.long 0x10 1. " WP71 ,Write protect (SIM low power logic)" "Disabled,Enabled" bitfld.long 0x10 0. " TP71 ,Trusted protect (SIM low power logic) " "Disabled,Enabled" line.long 0x14 "PACRJ,Peripheral Access Control Register" bitfld.long 0x14 30. " SP72 ,Supervisor protect (SIM)" "Disabled,Enabled" bitfld.long 0x14 29. " WP72 ,Write protect (SIM)" "Disabled,Enabled" bitfld.long 0x14 28. " TP72 ,Trusted protect (SIM) " "Disabled,Enabled" textline " " bitfld.long 0x14 26. " SP73 ,Supervisor protect (Port A Control)" "Disabled,Enabled" bitfld.long 0x14 25. " WP73 ,Write protect (Port A Control)" "Disabled,Enabled" bitfld.long 0x14 24. " TP73 ,Trusted protect (Port A Control) " "Disabled,Enabled" textline " " bitfld.long 0x14 22. " SP74 ,Supervisor protect (Port B Control)" "Disabled,Enabled" bitfld.long 0x14 21. " WP74 ,Write protect (Port B Control)" "Disabled,Enabled" bitfld.long 0x14 20. " TP74 ,Trusted protect (Port B Control) " "Disabled,Enabled" textline " " bitfld.long 0x14 18. " SP75 ,Supervisor protect (Port C Control)" "Disabled,Enabled" bitfld.long 0x14 17. " WP75 ,Write protect (Port C Control)" "Disabled,Enabled" bitfld.long 0x14 16. " TP75 ,Trusted protect (Port C Control) " "Disabled,Enabled" textline " " bitfld.long 0x14 14. " SP76 ,Supervisor protect (Port D Control)" "Disabled,Enabled" bitfld.long 0x14 13. " WP76 ,Write protect (Port D Control)" "Disabled,Enabled" bitfld.long 0x14 12. " TP76 ,Trusted protect (Port D Control) " "Disabled,Enabled" textline " " bitfld.long 0x14 10. " SP77 ,Supervisor protect (Port E Control)" "Disabled,Enabled" bitfld.long 0x14 9. " WP77 ,Write protect (Port E Control)" "Disabled,Enabled" bitfld.long 0x14 8. " TP77 ,Trusted protect (Port E Control) " "Disabled,Enabled" sif cpuis("MK61*")||cpuis("MK70*")||cpuis("MK10FN1M0VLQ12")||cpuis("MK10FN1M0VMD12")||cpuis("MK10FX512VLQ12")||cpuis("MK10FX512VMD12")||cpuis("MK60F*") textline " " bitfld.long 0x14 6. " SP78 ,Supervisor protect (Port F Control)" "Disabled,Enabled" bitfld.long 0x14 5. " WP78 ,Write protect (Port F Control)" "Disabled,Enabled" bitfld.long 0x14 4. " TP78 ,Trusted protect (Port F Control) " "Disabled,Enabled" endif line.long 0x18 "PACRK,Peripheral Access Control Register" bitfld.long 0x18 22. " SP82 ,Supervisor protect (SW Watchdog)" "Disabled,Enabled" bitfld.long 0x18 21. " WP82 ,Write protect (SW Watchdog)" "Disabled,Enabled" bitfld.long 0x18 20. " TP82 ,Trusted protect (SW Watchdog) " "Disabled,Enabled" group.long 0x60++0x0F line.long 0x00 "PACRM,Peripheral Access Control Register" bitfld.long 0x00 26. " SP97 ,Supervisor protect (Ext Watchdog)" "Disabled,Enabled" bitfld.long 0x00 25. " WP97 ,Write protect (Ext Watchdog)" "Disabled,Enabled" bitfld.long 0x00 24. " TP97 ,Trusted protect (Ext Watchdog) " "Disabled,Enabled" sif !cpuis("MK11D*")&&!cpuis("MK12D*") textline " " bitfld.long 0x00 22. " SP98 ,Supervisor protect (CMT)" "Disabled,Enabled" bitfld.long 0x00 21. " WP98 ,Write protect (CMT)" "Disabled,Enabled" bitfld.long 0x00 20. " TP98 ,Trusted protect (CMT) " "Disabled,Enabled" endif textline " " bitfld.long 0x00 14. " SP100 ,Supervisor protect (MCG)" "Disabled,Enabled" bitfld.long 0x00 13. " WP100 ,Write protect (MCG)" "Disabled,Enabled" bitfld.long 0x00 12. " TP100 ,Trusted protect (MCG) " "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SP101 ,Supervisor protect (OSC)" "Disabled,Enabled" bitfld.long 0x00 9. " WP101 ,Write protect (OSC)" "Disabled,Enabled" bitfld.long 0x00 8. " TP101 ,Trusted protect (OSC) " "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SP102 ,Supervisor protect (I2C 0)" "Disabled,Enabled" bitfld.long 0x00 5. " WP102 ,Write protect (I2C 0)" "Disabled,Enabled" bitfld.long 0x00 4. " TP102 ,Trusted protect (I2C 0) " "Disabled,Enabled" sif cpuis("MK10D*7")||cpuis("MK10F*12")||cpuis("MK11D*")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK5?*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK10D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*") textline " " bitfld.long 0x00 2. " SP103 ,Supervisor protect (I2C 1)" "Disabled,Enabled" bitfld.long 0x00 1. " WP103 ,Write protect (I2C 1)" "Disabled,Enabled" bitfld.long 0x00 0. " TP103 ,Trusted protect (I2C 1)" "Disabled,Enabled" endif line.long 0x04 "PACRN,Peripheral Access Control Register" bitfld.long 0x04 22. " SP106 ,Supervisor protect (UART 0)" "Disabled,Enabled" bitfld.long 0x04 21. " WP106 ,Write protect (UART 0)" "Disabled,Enabled" bitfld.long 0x04 20. " TP106 ,Trusted protect (UART 0) " "Disabled,Enabled" textline " " bitfld.long 0x04 18. " SP107 ,Supervisor protect (UART 1)" "Disabled,Enabled" bitfld.long 0x04 17. " WP107 ,Write protect (UART 1)" "Disabled,Enabled" bitfld.long 0x04 16. " TP107 ,Trusted protect (UART 1) " "Disabled,Enabled" textline " " bitfld.long 0x04 14. " SP108 ,Supervisor protect (UART 2)" "Disabled,Enabled" bitfld.long 0x04 13. " WP108 ,Write protect (UART 2)" "Disabled,Enabled" bitfld.long 0x04 12. " TP108 ,Trusted protect (UART 2) " "Disabled,Enabled" sif cpuis("MK10D*7")||cpuis("MK10F*12")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK5?*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK10D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*") sif !cpuis("MK40D*VLH7")&&!cpuis("MK30D*VLH7")&&!cpuis("MK10D*VLH7")&&!cpuis("MK51D*CLH7")&&!cpuis("MK50D*CLH7") textline " " bitfld.long 0x04 10. " SP109 ,Supervisor protect (UART 3)" "Disabled,Enabled" bitfld.long 0x04 9. " WP109 ,Write protect (UART 3)" "Disabled,Enabled" bitfld.long 0x04 8. " TP109 ,Trusted protect (UART 3) " "Disabled,Enabled" endif endif line.long 0x08 "PACRO,Peripheral Access Control Register" sif cpuis("MK40D*")||cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK51D*")||cpuis("MK50D*")||cpuis("MK60*10")||cpuis("MK6?F*")||cpuis("MK70*") bitfld.long 0x08 22. " SP114 ,Supervisor protect (USB OTG FS/LS)" "Disabled,Enabled" bitfld.long 0x08 21. " WP114 ,Write protect (USB OTG FS/LS)" "Disabled,Enabled" bitfld.long 0x08 20. " TP114 ,Trusted protect (USB OTG FS/LS) " "Disabled,Enabled" textline " " endif bitfld.long 0x08 18. " SP115 ,Supervisor protect (CMP/DAC)" "Disabled,Enabled" bitfld.long 0x08 17. " WP115 ,Write protect (CMP/DAC)" "Disabled,Enabled" bitfld.long 0x08 16. " TP115 ,Trusted protect (CMP/DAC) " "Disabled,Enabled" sif !cpuis("MK10D*VFM5") textline " " bitfld.long 0x08 14. " SP116 ,Supervisor protect (VREF)" "Disabled,Enabled" bitfld.long 0x08 13. " WP116 ,Write protect (VREF)" "Disabled,Enabled" bitfld.long 0x08 12. " TP116 ,Trusted protect (VREF) " "Disabled,Enabled" endif line.long 0x0C "PACRP,Peripheral Access Control Register" bitfld.long 0x0C 14. " SP124 ,Supervisor protect (LLWU)" "Disabled,Enabled" bitfld.long 0x0C 13. " WP124 ,Write protect (LLWU)" "Disabled,Enabled" bitfld.long 0x0C 12. " TP124 ,Trusted protect (LLWU) " "Disabled,Enabled" textline " " bitfld.long 0x0C 10. " SP125 ,Supervisor protect (PMC)" "Disabled,Enabled" bitfld.long 0x0C 9. " WP125 ,Write protect (PMC)" "Disabled,Enabled" bitfld.long 0x0C 8. " TP125 ,Trusted protect (PMC) " "Disabled,Enabled" textline " " bitfld.long 0x0C 6. " SP126 ,Supervisor protect (MC)" "Disabled,Enabled" bitfld.long 0x0C 5. " WP126 ,Write protect (MC)" "Disabled,Enabled" bitfld.long 0x0C 4. " TP126 ,Trusted protect (MC) " "Disabled,Enabled" sif !cpuis("MK60*AB10")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK40D*Z*10")&&!cpuis("MK10DN512ZVLL10*")&&!cpuis("MK10DN512ZVLQ10")&&!cpuis("MK10DN512ZVMD10")&&!cpuis("MK10DN512ZVMC10")&&!cpuis("MK10DX256ZVLQ10*")&&!cpuis("MK10DX256ZVMD10")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10")&&cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10") textline " " bitfld.long 0x0C 2. " SP127 ,Supervisor protect (RCM)" "Disabled,Enabled" bitfld.long 0x0C 1. " WP127 ,Write protect (RCM)" "Disabled,Enabled" bitfld.long 0x0C 0. " TP127 ,Trusted protect (RCM) " "Disabled,Enabled" endif width 0x0B tree.end tree "AIPS-Lite 1" base ad:0x40080000 width 7. group.long 0x00++0x03 line.long 0x00 "MPRA,Master Privilege Register A" bitfld.long 0x00 30. " MTR0 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 29. " MTW0 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 28. " MPL0 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 26. " MTR1 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 25. " MTW1 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 24. " MPL1 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 22. " MTR2 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 21. " MTW2 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 20. " MPL2 ,Master privilege level" "Not forced,Forced" sif (!cpuis("MK30DX256VLL7*")) textline " " bitfld.long 0x00 18. " MTR3 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 17. " MTW3 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 16. " MPL3 ,Master privilege level" "Not forced,Forced" sif !cpuis("MK?0D*7") textline " " bitfld.long 0x00 14. " MTR4 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 13. " MTW4 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 12. " MPL4 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 10. " MTR5 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 9. " MTW5 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 8. " MPL5 ,Master privilege level" "Not forced,Forced" sif !cpuis("MK?0D*10*")&&!cpuis("MK60DN512ZVLQ10R") textline " " bitfld.long 0x00 6. " MTR6 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 5. " MTW6 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 4. " MPL6 ,Master privilege level" "Not forced,Forced" textline " " bitfld.long 0x00 2. " MTR7 ,Master trusted for read" "Not trusted,Trusted" bitfld.long 0x00 1. " MTW7 ,Master trusted for writes" "Not trusted,Trusted" bitfld.long 0x00 0. " MPL7 ,Master privilege level" "Not forced,Forced" endif endif endif textline " " group.long 0x20++0x03 line.long 0x00 "PACRA,Peripheral Access Control Register" bitfld.long 0x00 30. " SP0 ,Supervisor protect (AIPS-Lite 1)" "Disabled,Enabled" bitfld.long 0x00 29. " WP0 ,Write protect (AIPS-Lite 1)" "Disabled,Enabled" bitfld.long 0x00 28. " TP0 ,Trusted protect (AIPS-Lite 1)" "Disabled,Enabled" sif cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK40DN512VLL10")||cpuis("MK40DN512VMC10")||cpuis("MK40D*VLQ10")||cpuis("MK40D*VMD10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30D????ZVLQ*")||cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK60*10")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10")||cpu()==("MK51DN512ZCLL10")||cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10") sif !cpuis("MK30DN512VLK10")&&!cpuis("MK30DN512VMB10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN512ZCLL10") group.long 0x40++0x03 line.long 0x00 "PACRE,Peripheral Access Control Register" sif cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK60*10")||cpuis("MK6?F*")||cpuis("MK70*") bitfld.long 0x00 30. " SP32 ,Supervisor protect (RNGB 1)" "Disabled,Enabled" bitfld.long 0x00 29. " WP32 ,Write protect (RNGB 1)" "Disabled,Enabled" bitfld.long 0x00 28. " TP32 ,Trusted protect (RNGB 1)" "Disabled,Enabled" endif sif cpu()!=("MK52DN512ZCLQ10")&&cpu()!=("MK52DN512ZCMD10")&&cpu()!=("MK53DN512ZCLQ10")&&cpu()!=("MK53DN512ZCMD10")&&cpu()!=("MK53DX256ZCLQ10")&&cpu()!=("MK50DN512ZCLQ10")&&cpu()!=("MK50DX256ZCLQ10")&&cpu()!=("MK50DN512ZCLL10")&&cpu()!=("MK50DX256ZCLL10")&&cpu()!=("MK51DN512ZCLL10")&&cpu()!=("MK51DN512ZCMC10")&&cpu()!=("MK51DX256ZCMC10")&&cpu()!=("MK51DN256ZCMD10")&&cpu()!=("MK51DN512ZCLQ10") bitfld.long 0x00 14. " SP36 ,Supervisor protect (FlexCAN 1)" "Disabled,Enabled" bitfld.long 0x00 13. " WP36 ,Write protect (FlexCAN 1)" "Disabled,Enabled" bitfld.long 0x00 12. " TP36 ,Trusted protect (FlexCAN 1)" "Disabled,Enabled" endif endif endif sif cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10") group.long 0x44++0x03 line.long 0x00 "PACRF,Peripheral Access Control Register" bitfld.long 0x00 14. " SP44 ,Supervisor protect (SPI 2)" "Disabled,Enabled" bitfld.long 0x00 13. " WP44 ,Write protect (SPI 2)" "Disabled,Enabled" bitfld.long 0x00 12. " TP44 ,Trusted protect (SPI 2)" "Disabled,Enabled" else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40DN512VLL10")||cpuis("MK40DN512VMC10")||cpuis("MK40D*VLQ10")||cpuis("MK40D*VMD10")||cpuis("MK40D*Z*10")||cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10")||cpu()==("MK51DN512ZCLL10")||cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpuis("MK52D*")||cpuis("MK53D*")||cpuis("MK60*10")||cpuis("MK6?F*")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK70*") sif !cpuis("MK10D*10")&&!cpuis("*VLK10") sif cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512VLL10")||cpuis("MK10D*VLQ10")||cpuis("MK10D*VMD10")||cpuis("MK10D*VMC10")||cpuis("MK10F*12")||cpuis("MK30D????ZVLQ*")||cpuis("MK30D*10")||cpuis("MK40D*Z*10")||cpuis("MK40DN512VLL10")||cpuis("MK40DN512VMC10")||cpuis("MK40D*VLQ10")||cpuis("MK40D*VMD10")||cpuis("MK50D*10")||cpuis("MK51D*CLL10")||cpuis("MK51D*CMC10")||cpuis("MK51D*CLQ10")||cpuis("MK51D*CMD10")||cpuis("MK52D*")||cpuis("MK53D*")||cpuis("MK6?*")||cpuis("MK70*") group.long 0x44++0x03 line.long 0x00 "PACRF,Peripheral Access Control Register" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") bitfld.long 0x00 30. " SP40 ,Supervisor protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 29. " WP40 ,Write protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 28. " TP40 ,Trusted protect (NAND)" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " SP41 ,Supervisor protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 25. " WP41 ,Write protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 24. " TP41 ,Trusted protect (NAND)" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SP42 ,Supervisor protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 21. " WP42 ,Write protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 20. " TP42 ,Trusted protect (NAND)" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " SP43 ,Supervisor protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 17. " WP43 ,Write protect (NAND)" "Disabled,Enabled" bitfld.long 0x00 16. " TP43 ,Trusted protect (NAND)" "Disabled,Enabled" endif sif !cpuis("MK10D*10")&&!cpuis("*VLK10") sif cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512VLL10")||cpuis("MK10D*VLQ10")||cpuis("MK10D*VMD10")||cpuis("MK10D*VMC10")||cpuis("MK10F*12")||cpuis("MK30D*10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40DN512VLL10")||cpuis("MK40DN512VMC10")||cpuis("MK40D*VLQ10")||cpuis("MK40D*VMD10")||cpuis("MK40D*Z*10")||cpuis("MK50D*10")||cpuis("MK50D*10")||cpuis("MK51D*CLL10")||cpuis("MK51D*CMC10")||cpuis("MK51D*CLQ10")||cpuis("MK51D*CMD10")||cpuis("MK52D*")||cpuis("MK53D*")||cpuis("MK6?*")||cpuis("MK70*") sif !cpuis("MK30DN512VLK10")&&!cpuis("MK30DN512VMB10") textline " " bitfld.long 0x00 14. " SP44 ,Supervisor protect (SPI 2)" "Disabled,Enabled" bitfld.long 0x00 13. " WP44 ,Write protect (SPI 2)" "Disabled,Enabled" bitfld.long 0x00 12. " TP44 ,Trusted protect (SPI 2)" "Disabled,Enabled" endif endif endif sif cpuis("MK61F*VMJ12")||cpuis("MK61F*VMJ15")||cpuis("MK70*") textline " " bitfld.long 0x00 6. " SP46 ,Supervisor protect (DDR controller)" "Disabled,Enabled" bitfld.long 0x00 5. " WP46 ,Write protect (DDR controller)" "Disabled,Enabled" bitfld.long 0x00 4. " TP46 ,Trusted protect (DDR controller)" "Disabled,Enabled" endif sif cpuis("MK10FN1M0VLQ12")||cpuis("MK10FN1M0VMD12")||cpuis("MK10FX512VLQ12")||cpuis("MK10FX512VMD12")||cpuis("MK6?F*")||cpuis("MK70*") textline " " bitfld.long 0x00 2. " SP47 ,Supervisor protect (I2S 1)" "Disabled,Enabled" bitfld.long 0x00 1. " WP47 ,Write protect (I2S 1)" "Disabled,Enabled" bitfld.long 0x00 0. " TP47 ,Trusted protect (I2S 1)" "Disabled,Enabled" endif endif endif endif endif sif cpuis("MK10D*10")||cpuis("MK10F*12")||cpuis("MK30D*10")||cpuis("MK40D*10")||cpuis("MK50D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK51D*CLL10")||cpuis("MK51D*CMC10")||cpuis("MK51D*10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*") group.long 0x48++0x03 line.long 0x00 "PACRG,Peripheral Access Control Register" sif !cpuis("MK50DX256CLK10") bitfld.long 0x00 26. " SP49 ,Supervisor protect (SDHC)" "Disabled,Enabled" bitfld.long 0x00 25. " WP49 ,Write protect (SDHC)" "Disabled,Enabled" bitfld.long 0x00 24. " TP49 ,Trusted protect (SDHC)" "Disabled,Enabled" endif sif cpuis("MK7*") textline " " bitfld.long 0x00 6. " SP54 ,Supervisor protect (PDB)" "Disabled,Enabled" bitfld.long 0x00 5. " WP54 ,Write protect (PDB)" "Disabled,Enabled" bitfld.long 0x00 4. " TP54 ,Trusted protect (PDB)" "Disabled,Enabled" endif endif group.long 0x4C++0x03 line.long 0x00 "PACRH,Peripheral Access Control Register" bitfld.long 0x00 30. " SP56 ,Supervisor protect (FlexTimer FTM 2)" "Disabled,Enabled" bitfld.long 0x00 29. " WP56 ,Write protect (FlexTimer FTM 2)" "Disabled,Enabled" bitfld.long 0x00 28. " TP56 ,Trusted protect (FlexTimer FTM 2)" "Disabled,Enabled" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") textline " " bitfld.long 0x00 26. " SP57 ,Supervisor protect (FlexTimer FTM 3)" "Disabled,Enabled" bitfld.long 0x00 25. " WP57 ,Write protect (FlexTimer FTM 3)" "Disabled,Enabled" bitfld.long 0x00 24. " TP57 ,Trusted protect (FlexTimer FTM 3)" "Disabled,Enabled" endif textline " " bitfld.long 0x00 18. " SP59 ,Supervisor protect (ADC 1)" "Disabled,Enabled" bitfld.long 0x00 17. " WP59 ,Write protect (ADC 1)" "Disabled,Enabled" bitfld.long 0x00 16. " TP59 ,Trusted protect (ADC 1)" "Disabled,Enabled" sif cpuis("MK10F*12")||cpuis("MK6?F*")||cpuis("MK70*") textline " " bitfld.long 0x00 14. " SP60 ,Supervisor protect (ADC 3)" "Disabled,Enabled" bitfld.long 0x00 13. " WP60 ,Write protect (ADC 3)" "Disabled,Enabled" bitfld.long 0x00 12. " TP60 ,Trusted protect (ADC 3)" "Disabled,Enabled" endif sif cpuis("MK30D*")||cpuis("MK40D*")||cpuis("MK51*")||cpuis("MK53D*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") textline " " bitfld.long 0x00 6. " SP62 ,Supervisor protect (LCD)" "Disabled,Enabled" bitfld.long 0x00 5. " WP62 ,Write protect (LCD)" "Disabled,Enabled" bitfld.long 0x00 4. " TP62 ,Trusted protect (LCD)" "Disabled,Enabled" endif sif (cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK60*10")||cpuis("MK6?F*")||cpuis("MK70*")) group.long 0x50++0x03 line.long 0x00 "PACRI,Peripheral Access Control Register" bitfld.long 0x00 30. " SP64 ,Supervisor protect (Ethernet MAC and IEEE 1588 timers)" "Disabled,Enabled" bitfld.long 0x00 29. " WP64 ,Write protect (Ethernet MAC and IEEE 1588 timers)" "Disabled,Enabled" bitfld.long 0x00 28. " TP64 ,Trusted protect (Ethernet MAC and IEEE 1588 timers)" "Disabled,Enabled" endif group.long 0x54++0x03 line.long 0x00 "PACRJ,Peripheral Access Control Register" bitfld.long 0x00 14. " SP76 ,Supervisor protect (DAC 0)" "Disabled,Enabled" bitfld.long 0x00 13. " WP76 ,Write protect (DAC 0)" "Disabled,Enabled" bitfld.long 0x00 12. " TP76 ,Trusted protect (DAC 0)" "Disabled,Enabled" sif cpuis("MK?0D*VMC10")||cpuis("MK?0D*VLQ10")||cpuis("MK?0D*VMD10")||cpuis("MK10F*12")||cpuis("MK50D*10")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK53D*")||cpuis("MK52D*")||cpuis("MK51DX256CLK10")||cpuis("MK51D*CLL10")||cpuis("MK51D*CMC10")||cpuis("MK60*AB10")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10") sif !cpuis("MK40*ZVLL10")&&!cpuis("MK10DN512ZVLL10*")&&!cpuis("MK10DN512ZVLQ10")&&!cpuis("MK10DN512ZVMD10")&&!cpuis("MK10DN512ZVMC10")&&!cpuis("MK10DX256ZVLQ10*")&&!cpuis("MK10DX256ZVMD10") textline " " bitfld.long 0x00 10. " SP77 ,Supervisor protect (DAC 1)" "Disabled,Enabled" bitfld.long 0x00 9. " WP77 ,Write protect (DAC 1)" "Disabled,Enabled" bitfld.long 0x00 8. " TP77 ,Trusted protect (DAC 1)" "Disabled,Enabled" endif endif sif cpuis("MK10FN1M0VLQ12")||cpuis("MK10FN1M0VMD12")||cpuis("MK10FX512VLQ12")||cpuis("MK10FX512VMD12")||cpuis("MK6?F*")||cpuis("MK70*") group.long 0x60++0x03 line.long 0x00 "PACRM,Peripheral Access Control Register" bitfld.long 0x00 10. " SP101 ,Supervisor protect (OSC1)" "Disabled,Enabled" bitfld.long 0x00 9. " WP101 ,Write protect (OSC1)" "Disabled,Enabled" bitfld.long 0x00 8. " TP101 ,Trusted protect (OSC1)" "Disabled,Enabled" endif sif cpuis("MK?0D*VLL7")||cpuis("MK?0D*VMC7")||cpuis("MK30D*VLL10")||cpuis("MK?0D*VMC10")||cpuis("MK?0D*VLQ10")||cpuis("MK?0D*VMD10")||cpuis("MK10F*12")||cpuis("MK50D*10")||cpuis("MK6?*")||cpuis("MK70*")||cpuis("MK40DN512VLL10")||cpuis("MK10DN512VLL10")||cpuis("K53D*")||cpuis("MK52D*")||cpuis("MK51D*CMC10")||cpuis("MK51D*CLQ10")||cpuis("MK51D*CMD10")||cpuis("MK51D*CLL7")||cpuis("MK51D*CMC7")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLL10*")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK40D*Z*10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") sif !cpuis("MK50DX256CLK10") group.long 0x64++0x03 line.long 0x00 "PACRN,Peripheral Access Control Register" bitfld.long 0x00 22. " SP106 ,Supervisor protect (UART 4)" "Disabled,Enabled" bitfld.long 0x00 21. " WP106 ,Write protect (UART 4)" "Disabled,Enabled" bitfld.long 0x00 20. " TP106 ,Trusted protect (UART 4)" "Disabled,Enabled" endif endif sif cpuis("MK?0D*VMC10")||cpuis("MK?0D*VLQ10")||cpuis("MK?0D*VMD10")||cpuis("MK10F*12")||cpuis("MK50D*CMC10")||cpuis("MK50D*CLQ10")||cpuis("MK50D*CMD10")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("K53D*")||cpuis("MK52D*")||cpuis("MK51D*CMC10")||cpuis("MK51D*10")||cpuis("MK60*AB10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") sif !cpuis("MK51DN512ZCLL10")&&(!cpuis("MK40*ZVLL10")) textline " " bitfld.long 0x00 18. " SP107 ,Supervisor protect (UART 5)" "Disabled,Enabled" bitfld.long 0x00 17. " WP107 ,Write protect (UART 5)" "Disabled,Enabled" bitfld.long 0x00 16. " TP107 ,Trusted protect (UART 5)" "Disabled,Enabled" endif endif sif cpuis("MK5?*") group.long 0x68++0x03 line.long 0x00 "PACRO,Peripheral Access Control Register" bitfld.long 0x00 10. " SP117 ,Supervisor protect (Op-amp)" "Disabled,Enabled" bitfld.long 0x00 9. " WP117 ,Write protect (Op-amp)" "Disabled,Enabled" bitfld.long 0x00 8. " TP117 ,Trusted protect (Op-amp)" "Disabled,Enabled" group.long 0x6C++0x03 line.long 0x00 "PACRP,Peripheral Access Control Register" bitfld.long 0x00 30. " SP120 ,Supervisor protect (TRIAMP)" "Disabled,Enabled" bitfld.long 0x00 29. " WP120 ,Write protect (TRIAMP)" "Disabled,Enabled" bitfld.long 0x00 28. " TP120 ,Trusted protect (TRIAMP)" "Disabled,Enabled" endif width 0x0B tree.end tree.end tree.open "DMAMUX (Direct Memory Access Multiplexer)" tree "MUX0" base ad:0x40021000 width 22. sif cpuis("MK60F*") group.byte 0x0++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 3 trigger enable" "Disabled,Enabled" group.byte 0x1++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 2 trigger enable" "Disabled,Enabled" group.byte 0x2++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 1 trigger enable" "Disabled,Enabled" group.byte 0x3++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 0 trigger enable" "Disabled,Enabled" group.byte 0x4++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 7 enable" "Disabled,Enabled" group.byte 0x5++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 6 enable" "Disabled,Enabled" group.byte 0x6++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 5 enable" "Disabled,Enabled" group.byte 0x7++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 4 enable" "Disabled,Enabled" group.byte 0x8++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 11 enable" "Disabled,Enabled" group.byte 0x9++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 10 enable" "Disabled,Enabled" group.byte 0xA++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 9 enable" "Disabled,Enabled" group.byte 0xB++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 8 enable" "Disabled,Enabled" group.byte 0xC++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 15 enable" "Disabled,Enabled" group.byte 0xD++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 14 enable" "Disabled,Enabled" group.byte 0xE++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 13 enable" "Disabled,Enabled" group.byte 0xF++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 12 enable" "Disabled,Enabled" else group.byte 0x0++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 0 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x1++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 1 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x2++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 2 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x3++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_0 channel 3 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x4++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 4 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 4 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x5++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 5 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 5 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x6++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 6 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 6 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x7++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 7 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 7 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x8++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 8 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 8 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x9++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 9 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 9 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xA++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 10 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 10 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xB++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 11 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 11 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xC++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 12 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 12 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xD++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 13 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 13 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xE++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 14 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 14 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xF++0x00 line.byte 0x00 "DMAMUX_0_CHCFG_15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_0 channel 15 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH0,FTM0_CH1,FTM0_CH2,FTM0_CH3,FTM0_CH4,FTM0_CH5,FTM0_CH6,FTM0_CH7,FTM1_CH0,FTM1_CH1,FTM2_CH0,FTM2_CH1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_0 channel 15 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif endif width 0x0B tree.end tree "MUX1" base ad:0x40022000 width 22. sif cpuis("MK60F*") group.byte 0x0++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 3 trigger enable" "Disabled,Enabled" group.byte 0x1++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 2 trigger enable" "Disabled,Enabled" group.byte 0x2++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 1 trigger enable" "Disabled,Enabled" group.byte 0x3++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 0 trigger enable" "Disabled,Enabled" group.byte 0x4++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 7 enable" "Disabled,Enabled" group.byte 0x5++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 6 enable" "Disabled,Enabled" group.byte 0x6++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 5 enable" "Disabled,Enabled" group.byte 0x7++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 4 enable" "Disabled,Enabled" group.byte 0x8++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 11 enable" "Disabled,Enabled" group.byte 0x9++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 10 enable" "Disabled,Enabled" group.byte 0xA++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 9 enable" "Disabled,Enabled" group.byte 0xB++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 8 enable" "Disabled,Enabled" group.byte 0xC++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 15 enable" "Disabled,Enabled" group.byte 0xD++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 14 enable" "Disabled,Enabled" group.byte 0xE++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 13 enable" "Disabled,Enabled" group.byte 0xF++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 12 enable" "Disabled,Enabled" else group.byte 0x0++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_0,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 0 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 0 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 0 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x1++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_1,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 1 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 1 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 1 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x2++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_2,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 2 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 2 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 2 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x3++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_3,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 3 enable" "Disabled,Enabled" bitfld.byte 0x00 6. " TRIG ,DMA_1 channel 3 trigger enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 3 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x4++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_4,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 4 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 4 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x5++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_5,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 5 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 5 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x6++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_6,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 6 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 6 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x7++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_7,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 7 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 7 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x8++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_8,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 8 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 8 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0x9++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_9,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 9 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 9 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xA++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_10,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 10 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 10 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xB++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_11,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 11 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 11 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xC++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_12,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 12 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 12 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xD++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_13,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 13 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 13 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xE++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_14,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 14 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 14 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif group.byte 0xF++0x00 line.byte 0x00 "DMAMUX_1_CHCFG_15,Channel Configuration Register" bitfld.byte 0x00 7. " ENBL ,DMA_1 channel 15 enable" "Disabled,Enabled" sif cpuis("MK11*MC*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK70*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,Timer_0,Timer_1,Timer_2,Timer_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK11*LK*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,,CMP0,CMP1,,,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLK10*")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK30DN512ZVLK10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,,,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*ZVMD10")||cpuis("MK40D*ZVLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif cpuis("MK30DX256VLL7*") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,,,,,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpuis("MK10DN512ZVLL10*")||cpuis("MK40D*ZVLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK50DN512ZCLL10")||cpu()==("MK50DX256ZCLL10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,,,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()=="MK10DN512ZVMC10")||cpuis("MK10DX256ZV??10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpu()==("MK50DN512ZCLQ10")||cpu()==("MK50DX256ZCLQ10") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif (cpu()==("MK51DN512ZCMC10")||cpu()==("MK51DX256ZCMC10")||cpu()==("MK51DN256ZCMD10")||cpu()==("MK51DN512ZCLQ10")||cpu()==("MK52DN512ZCLQ10")||cpu()==("MK52DN512ZCMD10")||cpu()==("MK53DN512ZCLQ10")||cpu()==("MK53DN512ZCMD10")||cpu()==("MK53DX256ZCLQ10")) bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S0_Rx,I2S0_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,,,I2C0,I2C1,FTM0_CH_0,FTM0_CH_1,FTM0_CH_2,FTM0_CH_3,FTM0_CH_4,FTM0_CH_5,FTM0_CH_6,FTM0_CH_7,FTM1_CH_0,FTM1_CH_1,FTM2_CH_0,FTM2_CH_1,FTM3_CH_0,FTM3_CH_1,FTM3_CH_2,FTM1_CH_3,ADC0,ADC1,CMP0,CMP1,CMP2,DAC0,DAC1,CMT,PDB,Port A,Port B,Port C,Port D,Port E,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" elif CPUIS("MK20FN1M0VLQ12R") bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "Disabled,,UART0_Rx,UART0_Tx,UART1_Rx,UART1_Tx,UART2_Rx,UART2_Tx,UART3_Rx,UART3_Tx,UART4_Rx,UART4_Tx,UART5_Rx,UART5_Tx,I2S1_Rx,I2S1_Tx,SPI0_Rx,SPI0_Tx,SPI1_Rx,SPI1_Tx,SPI2_Rx,SPI2_Tx,,,FTM3_CH0,FTM3_CH1,FTM3_CH2,FTM3_CH3,FTM3_CH4,FTM3_CH5,FTM3_CH6,FTM3_CH7,,,,,,,,,ADC0,ADC1,ADC2,ADC3,,DAC0,DAC1,CMP0,CMP1,CMP2,CMP3,,,Port F,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled,Always enabled" else bitfld.byte 0x00 0.--5. " SOURCE ,DMA_1 channel 15 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif endif width 0x0B tree.end tree.end tree "eDMA (Enhanced Direct Memory Access)" base ad:0x40008000 width 6. tree "eDMA Control and Status Registers" group.long 0x00++0x03 line.long 0x00 "CR,Control Register" sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") sif cpuis("MK22FN128VLH10R") rbitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.long 0x00 31. " ACTIVE ,DMA active status" "Idle,Executing" newline endif endif bitfld.long 0x00 17. " CX ,Cancel transfer" "Not canceled,Canceled" bitfld.long 0x00 16. " ECX ,Error cancel transfer" "No error,Error" sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 10. " GRP1PRI ,Channel group 1 priority" "0,1" bitfld.long 0x00 8. " GRP0PRI ,Channel group 0 priority" "0,1" elif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK60FN1M0VLQ15") sif !cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 10.--11. " GRP1PRI ,Channel group 1 priority" "0,1,2,3" bitfld.long 0x00 8.--9. " GRP0PRI ,Channel group 0 priority" "0,1,2,3" endif endif newline bitfld.long 0x00 7. " EMLM ,Enable minor loop mapping" "Disabled,Enabled" bitfld.long 0x00 6. " CLM ,Continuous link mode" "Through channel arbitration,Not through channel arbitration" newline bitfld.long 0x00 5. " HALT ,Halt DMA operations" "Not halted,Halted" bitfld.long 0x00 4. " HOE ,Halt on error" "Not halted,Halted" newline sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 3. " ERGA ,Enable round robin group arbitration" "Disabled,Enabled" newline endif endif bitfld.long 0x00 2. " ERCA ,Enable round robin channel arbitration" "Disabled,Enabled" bitfld.long 0x00 1. " EDBG ,Enable debug" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "ES,Error Status Register" bitfld.long 0x00 31. " VLD ,Logical OR of all ERR status bits" "Cleared,Not cleared" bitfld.long 0x00 16. " ECX ,Transfer canceled" "Not canceled,Canceled" sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") newline bitfld.long 0x00 15. " GPE ,Group priority error" "No error,Error" endif endif sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--12. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--9. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3" else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else newline bitfld.long 0x00 14. " CPE ,Channel priority error" "No error,Error" bitfld.long 0x00 8.--11. " ERRCHN ,Error channel number or canceled channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 7. " SAE ,Source address error" "No error,Error" bitfld.long 0x00 6. " SOE ,Source offset error" "No error,Error" newline bitfld.long 0x00 5. " DAE ,Destination address error" "No error,Error" bitfld.long 0x00 4. " DOE ,Destination offset error" "No error,Error" bitfld.long 0x00 3. " NCE ,NBYTES/CITER configuration error" "No error,Error" newline bitfld.long 0x00 2. " SGE ,Scatter/gather configuration error" "No error,Error" bitfld.long 0x00 1. " SBE ,Source bus error" "No error,Error" bitfld.long 0x00 0. " DBE ,Destination bus error" "No error,Error" group.long 0x0C++0x03 line.long 0x00 "ERQ,Enable Request Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " ERQ[31] ,Enable DMA request 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable DMA request 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable DMA request 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable DMA request 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable DMA request 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable DMA request 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable DMA request 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable DMA request 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable DMA request 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable DMA request 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable DMA request 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable DMA request 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable DMA request 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable DMA request 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable DMA request 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable DMA request 16" "Disabled,Enabled" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20FX256VLH7")||cpuis("MK20FX128VLH7")||cpuis("MK20FX64VLH7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable DMA request 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " ERQ[15] ,Enable DMA request 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable DMA request 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable DMA request 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable DMA request 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable DMA request 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable DMA request 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable DMA request 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable DMA request 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable DMA request 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable DMA request 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable DMA request 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable DMA request 4" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " [3] ,Enable DMA request 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable DMA request 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable DMA request 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable DMA request 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "EEI,Enable Error Interrupt Register" sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " EEI[31] ,Enable error interrupt 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable error interrupt 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable error interrupt 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable error interrupt 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable error interrupt 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable error interrupt 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable error interrupt 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable error interrupt 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable error interrupt 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable error interrupt 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable error interrupt 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable error interrupt 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable error interrupt 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable error interrupt 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable error interrupt 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable error interrupt 16" "Disabled,Enabled" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK?0F*")||cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Enable error interrupt 15" "Disabled,Enabled" endif else bitfld.long 0x00 15. " EEI[15] ,Enable error interrupt 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable error interrupt 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable error interrupt 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable error interrupt 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable error interrupt 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable error interrupt 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable error interrupt 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable error interrupt 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable error interrupt 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable error interrupt 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable error interrupt 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable error interrupt 4" "Disabled,Enabled" newline endif bitfld.long 0x00 3. " [3] ,Enable error interrupt 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable error interrupt 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable error interrupt 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable error interrupt 0" "Disabled,Enabled" newline wgroup.byte 0x18++0x27 line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register" bitfld.byte 0x00 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x00 6. " CAEE ,Clear all enable error interrupts" "CEEI only,All EEI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 0.--4. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x00 0.--1. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--3. " CEEI ,Clear enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x00 4. " CEEI[4] ,Clear enable error interrupt 4 in EEI" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x00 3. " CEEI[3] ,Clear enable error interrupt 3 in EEI" "No effect,Clear" bitfld.byte 0x00 2. " CEEI[2] ,Clear enable error interrupt 2 in EEI" "No effect,Clear" newline endif bitfld.byte 0x00 1. " CEEI[1] ,Clear enable error interrupt 1 in EEI" "No effect,Clear" bitfld.byte 0x00 0. " CEEI[0] ,Clear enable error interrupt 0 in EEI" "No effect,Clear" endif line.byte 0x01 "SEEI,Set Enable Error Interrupt Register" bitfld.byte 0x01 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x01 6. " SAEE ,Sets all enable error interrupts" "SEEI only,All EEI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x01 0.--4. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x01 0.--1. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x01 0.--3. " SEEI ,Set enable error interrupt for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x01 4. " SEEI[4] ,Set enable error interrupt 4 in EEI" "No effect,Set" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x01 3. " SEEI[3] ,Set enable error interrupt 3 in EEI" "No effect,Set" bitfld.byte 0x01 2. " SEEI[2] ,Set enable error interrupt 2 in EEI" "No effect,Set" newline endif bitfld.byte 0x01 1. " SEEI[1] ,Set enable error interrupt 1 in EEI" "No effect,Set" bitfld.byte 0x01 0. " SEEI[0] ,Set enable error interrupt 0 in EEI" "No effect,Set" endif line.byte 0x02 "CERQ,Clear Enable Request Register" bitfld.byte 0x02 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x02 6. " CAER ,Clear all enable requests" "CER only,ALL ER" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x02 0.--4. " CERQ ,Clear enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x02 0.--1. " CERQ ,Clear enable request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x02 0.--3. " CERQ ,Clear enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x02 4. " CERQ[4] ,Clear enable request" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x02 3. " CERQ[3] ,Clear enable request" "No effect,Clear" bitfld.byte 0x02 2. " CERQ[2] ,Clear enable request" "No effect,Clear" newline endif bitfld.byte 0x02 1. " CERQ[1] ,Clear enable request" "No effect,Clear" bitfld.byte 0x02 0. " CERQ[0] ,Clear enable request" "No effect,Clear" endif line.byte 0x03 "SERQ,Set Enable Request Register" bitfld.byte 0x03 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x03 6. " SAER ,Set all enable requests" "SAER only,All ER" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x03 0.--4. " SERQ ,Set enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x03 0.--1. " SERQ ,Set enable request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x03 0.--3. " SERQ ,Set enable request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x03 4. " SERQ[4] ,Set enable request" "No effect,Set" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x03 3. " SERQ[3] ,Set enable request" "No effect,Set" bitfld.byte 0x03 2. " SERQ[2] ,Set enable request" "No effect,Set" newline endif bitfld.byte 0x03 1. " SERQ[1] ,Set enable request" "No effect,Set" bitfld.byte 0x03 0. " SERQ[0] ,Set enable request" "No effect,Set" endif line.byte 0x04 "CDNE,Clear DONE Status Bit Register" bitfld.byte 0x04 7. " NOP ,No operation bit" "Disabled,Enabled" bitfld.byte 0x04 6. " CADN ,Clear all done bits" "CADB only,All DB" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x04 0.--4. " CDNE ,Clear done bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x04 0.--1. " CDNE ,Clear done bit for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x04 0.--3. " CDNE ,Clear done bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x04 4. " CDNE[4] ,Clear done bit" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x04 3. " CDNE[3] ,Clear done bit" "No effect,Clear" bitfld.byte 0x04 2. " CDNE[2] ,Clear done bit" "No effect,Clear" newline endif bitfld.byte 0x04 1. " CDNE[1] ,Clear done bit" "No effect,Clear" bitfld.byte 0x04 0. " CDNE[0] ,Clear done bit" "No effect,Clear" endif line.byte 0x05 "SSRT,Set START Bit Register" bitfld.byte 0x05 7. " NOP ,No operation bit" "Disabled,Enabled" bitfld.byte 0x05 6. " SAST ,Set all start bits" "SASB only,All SB" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 0.--4. " SSRT ,Set start bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x05 0.--1. " SSRT ,Set start bit for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 0.--3. " SSRT ,Set start bit for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x05 4. " SSRT[4] ,Set start bit" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x05 3. " SSRT[3] ,Set start bit" "No effect,Clear" bitfld.byte 0x05 2. " SSRT[2] ,Set start bit" "No effect,Clear" newline endif bitfld.byte 0x05 1. " SSRT[1] ,Set start bit" "No effect,Clear" bitfld.byte 0x05 0. " SSRT[0] ,Set start bit" "No effect,Clear" endif line.byte 0x06 "CERR,Clear Error Register" bitfld.byte 0x06 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x06 6. " CAEI ,Clear all error indicators" "CAEI only,ALL EI" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x06 0.--4. " CERR ,Clear error indicator for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x06 0.--1. " CERR ,Clear error indicator for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x06 0.--3. " CERR ,Clear error indicator for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x06 4. " CERR[4] ,Clear error indicator" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x06 3. " CERR[3] ,Clear error indicator" "No effect,Clear" bitfld.byte 0x06 2. " CERR[2] ,Clear error indicator" "No effect,Clear" newline endif bitfld.byte 0x06 1. " CERR[1] ,Clear error indicator" "No effect,Clear" bitfld.byte 0x06 0. " CERR[0] ,Clear error indicator" "No effect,Clear" endif line.byte 0x07 "CINT,Clear Interrupt Request Register" bitfld.byte 0x07 7. " NOP ,No operation bit" "Disable,Enable" bitfld.byte 0x07 6. " CAIR ,Clear all interrupt request" "CAIR only,All IR" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x07 0.--4. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline elif cpuis("MK20DX64VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN32VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK22FN128VLH10R") bitfld.byte 0x07 0.--1. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3" newline elif cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VMB7")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VEX7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x07 0.--3. " CINT ,Clear interrupt request for DMA channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline else sif cpuis("MK6?F*")||cpuis("MK10F*12")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.byte 0x07 4. " CINT[4] ,Clear interrupt request" "No effect,Clear" newline endif endif sif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10") bitfld.byte 0x07 3. " CINT[3] ,Clear interrupt request" "No effect,Clear" bitfld.byte 0x07 2. " CINT[2] ,Clear interrupt request" "No effect,Clear" newline endif bitfld.byte 0x07 1. " CINT[1] ,Clear interrupt request" "No effect,Clear" bitfld.byte 0x07 0. " CINT[0] ,Clear interrupt request" "No effect,Clear" endif group.long 0x24++0x03 line.long 0x00 "INT,Interrupt Request Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") eventfld.long 0x00 31. " INT[31] ,Interrupt request 31" "No interrupt,Interrupt" eventfld.long 0x00 30. " [30] ,Interrupt request 30" "No interrupt,Interrupt" eventfld.long 0x00 29. " [29] ,Interrupt request 29" "No interrupt,Interrupt" newline eventfld.long 0x00 28. " [28] ,Interrupt request 28" "No interrupt,Interrupt" eventfld.long 0x00 27. " [27] ,Interrupt request 27" "No interrupt,Interrupt" eventfld.long 0x00 26. " [26] ,Interrupt request 26" "No interrupt,Interrupt" newline eventfld.long 0x00 25. " [25] ,Interrupt request 25" "No interrupt,Interrupt" eventfld.long 0x00 24. " [24] ,Interrupt request 24" "No interrupt,Interrupt" eventfld.long 0x00 23. " [23] ,Interrupt request 23" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " [22] ,Interrupt request 22" "No interrupt,Interrupt" eventfld.long 0x00 21. " [21] ,Interrupt request 21" "No interrupt,Interrupt" eventfld.long 0x00 20. " [20] ,Interrupt request 20" "No interrupt,Interrupt" newline eventfld.long 0x00 19. " [19] ,Interrupt request 19" "No interrupt,Interrupt" eventfld.long 0x00 18. " [18] ,Interrupt request 18" "No interrupt,Interrupt" eventfld.long 0x00 17. " [17] ,Interrupt request 17" "No interrupt,Interrupt" newline eventfld.long 0x00 16. " [16] ,Interrupt request 16" "No interrupt,Interrupt" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Interrupt request 15" "No interrupt,Interrupt" endif else bitfld.long 0x00 15. " INT[15] ,Interrupt request 15" "No interrupt,Interrupt" endif newline eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Interrupt request 15" "No interrupt,Interrupt" endif else bitfld.long 0x00 15. " INT[15] ,Interrupt request 15" "No interrupt,Interrupt" endif newline eventfld.long 0x00 14. " [14] ,Interrupt request 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Interrupt request 13" "No interrupt,Interrupt" newline eventfld.long 0x00 12. " [12] ,Interrupt request 12" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Interrupt request 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Interrupt request 10" "No interrupt,Interrupt" newline eventfld.long 0x00 9. " [9] ,Interrupt request 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Interrupt request 8" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Interrupt request 7" "No interrupt,Interrupt" newline eventfld.long 0x00 6. " [6] ,Interrupt request 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Interrupt request 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Interrupt request 4" "No interrupt,Interrupt" newline endif eventfld.long 0x00 3. " [3] ,Interrupt request 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Interrupt request 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Interrupt request 1" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " [0] ,Interrupt request 0" "No interrupt,Interrupt" group.long 0x2C++0x03 line.long 0x00 "ERR,Error Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") eventfld.long 0x00 31. " ERR[31] ,Error in channel 31" "No error,Error" eventfld.long 0x00 30. " [30] ,Error in channel 30" "No error,Error" eventfld.long 0x00 29. " [29] ,Error in channel 29" "No error,Error" newline eventfld.long 0x00 28. " [28] ,Error in channel 28" "No error,Error" eventfld.long 0x00 27. " [27] ,Error in channel 27" "No error,Error" eventfld.long 0x00 26. " [26] ,Error in channel 26" "No error,Error" newline eventfld.long 0x00 25. " [25] ,Error in channel 25" "No error,Error" eventfld.long 0x00 24. " [24] ,Error in channel 24" "No error,Error" eventfld.long 0x00 23. " [23] ,Error in channel 23" "No error,Error" newline eventfld.long 0x00 22. " [22] ,Error in channel 22" "No error,Error" eventfld.long 0x00 21. " [21] ,Error in channel 21" "No error,Error" eventfld.long 0x00 20. " [20] ,Error in channel 20" "No error,Error" newline eventfld.long 0x00 19. " [19] ,Error in channel 19" "No error,Error" eventfld.long 0x00 18. " [18] ,Error in channel 18" "No error,Error" eventfld.long 0x00 17. " [17] ,Error in channel 17" "No error,Error" newline eventfld.long 0x00 16. " [16] ,Error in channel 16" "No error,Error" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" endif else bitfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" endif newline eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" newline eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" newline eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" newline eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Error in channel 15" "No error,Error" endif else bitfld.long 0x00 15. " ERR[15] ,Error in channel 15" "No error,Error" endif newline eventfld.long 0x00 14. " [14] ,Error in channel 14" "No error,Error" eventfld.long 0x00 13. " [13] ,Error in channel 13" "No error,Error" newline eventfld.long 0x00 12. " [12] ,Error in channel 12" "No error,Error" eventfld.long 0x00 11. " [11] ,Error in channel 11" "No error,Error" eventfld.long 0x00 10. " [10] ,Error in channel 10" "No error,Error" newline eventfld.long 0x00 9. " [9] ,Error in channel 9" "No error,Error" eventfld.long 0x00 8. " [8] ,Error in channel 8" "No error,Error" eventfld.long 0x00 7. " [7] ,Error in channel 7" "No error,Error" newline eventfld.long 0x00 6. " [6] ,Error in channel 6" "No error,Error" eventfld.long 0x00 5. " [5] ,Error in channel 5" "No error,Error" eventfld.long 0x00 4. " [4] ,Error in channel 4" "No error,Error" newline endif eventfld.long 0x00 3. " [3] ,Error in channel 3" "No error,Error" eventfld.long 0x00 2. " [2] ,Error in channel 2" "No error,Error" eventfld.long 0x00 1. " [1] ,Error in channel 1" "No error,Error" newline eventfld.long 0x00 0. " [0] ,Error in channel 0" "No error,Error" sif cpuis("MK11*")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" elif cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK24*")||cpuis("MK21D*LK5")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21F*AVMC12")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22F*DC10")||(cpuis("MK22F*LL10")&&!cpuis("MK22FN1M0VLL10"))||cpuis("MK22F*MP10")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK24FN256VDC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK22FN128VLH10R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") rgroup.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " HRS[31] ,Hardware request status for channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status for channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status for channel 29" "Not present,Present" newline bitfld.long 0x00 28. " [28] ,Hardware request status for channel 28" "Not present,Present" bitfld.long 0x00 27. " [27] ,Hardware request status for channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status for channel 26" "Not present,Present" newline bitfld.long 0x00 25. " [25] ,Hardware request status for channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status for channel 24" "Not present,Present" bitfld.long 0x00 23. " [23] ,Hardware request status for channel 23" "Not present,Present" newline bitfld.long 0x00 22. " [22] ,Hardware request status for channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status for channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status for channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status for channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status for channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status for channel 17" "Not present,Present" newline bitfld.long 0x00 16. " [16] ,Hardware request status for channel 16" "Not present,Present" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline endif bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" else group.long 0x34++0x03 line.long 0x00 "HRS,Hardware Request Status Register" sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 31. " HRS[31] ,Hardware request status for channel 31" "Not present,Present" bitfld.long 0x00 30. " [30] ,Hardware request status for channel 30" "Not present,Present" bitfld.long 0x00 29. " [29] ,Hardware request status for channel 29" "Not present,Present" newline bitfld.long 0x00 28. " [28] ,Hardware request status for channel 28" "Not present,Present" bitfld.long 0x00 27. " [27] ,Hardware request status for channel 27" "Not present,Present" bitfld.long 0x00 26. " [26] ,Hardware request status for channel 26" "Not present,Present" newline bitfld.long 0x00 25. " [25] ,Hardware request status for channel 25" "Not present,Present" bitfld.long 0x00 24. " [24] ,Hardware request status for channel 24" "Not present,Present" bitfld.long 0x00 23. " [23] ,Hardware request status for channel 23" "Not present,Present" newline bitfld.long 0x00 22. " [22] ,Hardware request status for channel 22" "Not present,Present" bitfld.long 0x00 21. " [21] ,Hardware request status for channel 21" "Not present,Present" bitfld.long 0x00 20. " [20] ,Hardware request status for channel 20" "Not present,Present" newline bitfld.long 0x00 19. " [19] ,Hardware request status for channel 19" "Not present,Present" bitfld.long 0x00 18. " [18] ,Hardware request status for channel 18" "Not present,Present" bitfld.long 0x00 17. " [17] ,Hardware request status for channel 17" "Not present,Present" newline bitfld.long 0x00 16. " [16] ,Hardware request status for channel 16" "Not present,Present" newline endif endif sif cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLL10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline elif !cpuis("MK?0D*5")&&!cpuis("MK22*DC10")&&!cpuis("MK22*LL10")&&!cpuis("MK22*MP10")&&!cpuis("MK22*LH10")&&!cpuis("MK22FN128VLH10R") sif cpuis("MK6?F*")||cpuis("MK?0F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.long 0x00 15. " [15] ,Hardware request status for channel 15" "Not present,Present" endif else bitfld.long 0x00 15. " HRS[15] ,Hardware request status for channel 15" "Not present,Present" endif newline bitfld.long 0x00 14. " [14] ,Hardware request status for channel 14" "Not present,Present" bitfld.long 0x00 13. " [13] ,Hardware request status for channel 13" "Not present,Present" newline bitfld.long 0x00 12. " [12] ,Hardware request status for channel 12" "Not present,Present" bitfld.long 0x00 11. " [11] ,Hardware request status for channel 11" "Not present,Present" bitfld.long 0x00 10. " [10] ,Hardware request status for channel 10" "Not present,Present" newline bitfld.long 0x00 9. " [9] ,Hardware request status for channel 9" "Not present,Present" bitfld.long 0x00 8. " [8] ,Hardware request status for channel 8" "Not present,Present" bitfld.long 0x00 7. " [7] ,Hardware request status for channel 7" "Not present,Present" newline bitfld.long 0x00 6. " [6] ,Hardware request status for channel 6" "Not present,Present" bitfld.long 0x00 5. " [5] ,Hardware request status for channel 5" "Not present,Present" bitfld.long 0x00 4. " [4] ,Hardware request status for channel 4" "Not present,Present" newline endif bitfld.long 0x00 3. " [3] ,Hardware request status for channel 3" "Not present,Present" bitfld.long 0x00 2. " [2] ,Hardware request status for channel 2" "Not present,Present" bitfld.long 0x00 1. " [1] ,Hardware request status for channel 1" "Not present,Present" newline bitfld.long 0x00 0. " [0] ,Hardware request status for channel 0" "Not present,Present" endif sif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register" sif cpuis("MK26F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 31. " EDREQ[31] ,Enable asynchronous DMA request in stop for channel 31" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,Enable asynchronous DMA request in stop for channel 30" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,Enable asynchronous DMA request in stop for channel 29" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,Enable asynchronous DMA request in stop for channel 28" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,Enable asynchronous DMA request in stop for channel 27" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,Enable asynchronous DMA request in stop for channel 26" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,Enable asynchronous DMA request in stop for channel 25" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,Enable asynchronous DMA request in stop for channel 24" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,Enable asynchronous DMA request in stop for channel 23" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,Enable asynchronous DMA request in stop for channel 22" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,Enable asynchronous DMA request in stop for channel 21" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,Enable asynchronous DMA request in stop for channel 20" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,Enable asynchronous DMA request in stop for channel 19" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,Enable asynchronous DMA request in stop for channel 18" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,Enable asynchronous DMA request in stop for channel 17" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,Enable asynchronous DMA request in stop for channel 16" "Disabled,Enabled" newline endif sif cpuis("MK26F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 15. " [15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" else bitfld.long 0x00 15. " EDREQ[15] ,Enable asynchronous DMA request in stop for channel 15" "Disabled,Enabled" endif newline bitfld.long 0x00 14. " [14] ,Enable asynchronous DMA request in stop for channel 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Enable asynchronous DMA request in stop for channel 13" "Disabled,Enabled" newline bitfld.long 0x00 12. " [12] ,Enable asynchronous DMA request in stop for channel 12" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,Enable asynchronous DMA request in stop for channel 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Enable asynchronous DMA request in stop for channel 10" "Disabled,Enabled" newline bitfld.long 0x00 9. " [9] ,Enable asynchronous DMA request in stop for channel 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Enable asynchronous DMA request in stop for channel 8" "Disabled,Enabled" bitfld.long 0x00 7. " [7] ,Enable asynchronous DMA request in stop for channel 7" "Disabled,Enabled" newline bitfld.long 0x00 6. " [6] ,Enable asynchronous DMA request in stop for channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Enable asynchronous DMA request in stop for channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Enable asynchronous DMA request in stop for channel 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" elif cpuis("MK26F*MD18")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10") group.long 0x44++0x03 line.long 0x00 "EARS,Enable Asynchronous Request In Stop Register" bitfld.long 0x00 3. " EDREQ[3] ,Enable asynchronous DMA request in stop for channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Enable asynchronous DMA request in stop for channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Enable asynchronous DMA request in stop for channel 1" "Disabled,Enabled" newline bitfld.long 0x00 0. " [0] ,Enable asynchronous DMA request in stop for channel 0" "Disabled,Enabled" endif endif tree.end width 11. tree "DMA Channel Priority Registers" sif cpuis("MK20D*5")||cpuis("MK10D*5")||cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--1. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,Highest" else group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif elif cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x10)++0x00 line.byte 0x00 "DCHPRI_19,Channel 19 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 19 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 19 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 19 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 19 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x11)++0x00 line.byte 0x00 "DCHPRI_18,Channel 18 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 18 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 18 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 18 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 18 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x12)++0x00 line.byte 0x00 "DCHPRI_17,Channel 17 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 17 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 17 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 17 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 17 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x13)++0x00 line.byte 0x00 "DCHPRI_16,Channel 16 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 16 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 16 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 16 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 16 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x14)++0x00 line.byte 0x00 "DCHPRI_23,Channel 23 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 23 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 23 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 23 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 23 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x15)++0x00 line.byte 0x00 "DCHPRI_22,Channel 22 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 22 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 22 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 22 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 22 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x16)++0x00 line.byte 0x00 "DCHPRI_21,Channel 21 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 21 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 21 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 21 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 21 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x17)++0x00 line.byte 0x00 "DCHPRI_20,Channel 20 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 20 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 20 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 20 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 20 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x18)++0x00 line.byte 0x00 "DCHPRI_27,Channel 27 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 27 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 27 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 27 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 27 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x19)++0x00 line.byte 0x00 "DCHPRI_26,Channel 26 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 26 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 26 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 26 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 26 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1A)++0x00 line.byte 0x00 "DCHPRI_25,Channel 25 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 25 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 25 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 25 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 25 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1B)++0x00 line.byte 0x00 "DCHPRI_24,Channel 24 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 24 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 24 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 24 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 24 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1C)++0x00 line.byte 0x00 "DCHPRI_31,Channel 31 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 31 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 31 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 31 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 31 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1D)++0x00 line.byte 0x00 "DCHPRI_30,Channel 30 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 30 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 30 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 30 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 30 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1E)++0x00 line.byte 0x00 "DCHPRI_29,Channel 29 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 29 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 29 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 29 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 29 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1F)++0x00 line.byte 0x00 "DCHPRI_28,Channel 28 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 28 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 28 preempt ability" "No,Yes" rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 28 current group priority" "0,1,2,3" bitfld.byte 0x00 0.--3. " CHPRI ,Channel 28 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" else group.byte (0x100+0x0)++0x00 line.byte 0x00 "DCHPRI_3,Channel 3 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 3 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 3 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 3 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 3 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x1)++0x00 line.byte 0x00 "DCHPRI_2,Channel 2 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 2 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 2 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 2 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 2 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x2)++0x00 line.byte 0x00 "DCHPRI_1,Channel 1 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 1 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 1 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 1 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 1 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x3)++0x00 line.byte 0x00 "DCHPRI_0,Channel 0 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 0 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 0 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 0 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 0 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x4)++0x00 line.byte 0x00 "DCHPRI_7,Channel 7 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 7 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 7 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 7 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 7 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x5)++0x00 line.byte 0x00 "DCHPRI_6,Channel 6 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 6 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 6 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 6 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 6 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x6)++0x00 line.byte 0x00 "DCHPRI_5,Channel 5 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 5 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 5 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 5 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 5 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x7)++0x00 line.byte 0x00 "DCHPRI_4,Channel 4 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 4 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 4 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 4 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 4 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x8)++0x00 line.byte 0x00 "DCHPRI_11,Channel 11 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 11 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 11 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 11 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 11 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0x9)++0x00 line.byte 0x00 "DCHPRI_10,Channel 10 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 10 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 10 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 10 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 10 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xA)++0x00 line.byte 0x00 "DCHPRI_9,Channel 9 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 9 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 9 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 9 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 9 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xB)++0x00 line.byte 0x00 "DCHPRI_8,Channel 8 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 8 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 8 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 8 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 8 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xC)++0x00 line.byte 0x00 "DCHPRI_15,Channel 15 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 15 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 15 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 15 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 15 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xD)++0x00 line.byte 0x00 "DCHPRI_14,Channel 14 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 14 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 14 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 14 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 14 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xE)++0x00 line.byte 0x00 "DCHPRI_13,Channel 13 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 13 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 13 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 13 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 13 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" group.byte (0x100+0xF)++0x00 line.byte 0x00 "DCHPRI_12,Channel 12 Priority Register" bitfld.byte 0x00 7. " ECP ,Enable channel 12 preemption" "Disabled,Enabled" bitfld.byte 0x00 6. " DPA ,Disable channel 12 preempt ability" "No,Yes" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK20FN1M0VLQ12R") sif !cpuis("MK63F*")&&!cpuis("MK64F*") rbitfld.byte 0x00 4.--5. " GRPPRI ,Channel 12 current group priority" "0,1,2,3" newline endif endif bitfld.byte 0x00 0.--3. " CHPRI ,Channel 12 arbitration priority" "Lowest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Highest" endif sif cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") group.byte (0x140+0x0)++0x00 line.byte 0x00 "DCHMID_3,Channel 3 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x1)++0x00 line.byte 0x00 "DCHMID_2,Channel 2 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x2)++0x00 line.byte 0x00 "DCHMID_1,Channel 1 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x3)++0x00 line.byte 0x00 "DCHMID_0,Channel 0 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x4)++0x00 line.byte 0x00 "DCHMID_7,Channel 7 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x5)++0x00 line.byte 0x00 "DCHMID_6,Channel 6 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x6)++0x00 line.byte 0x00 "DCHMID_5,Channel 5 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x7)++0x00 line.byte 0x00 "DCHMID_4,Channel 4 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x8)++0x00 line.byte 0x00 "DCHMID_11,Channel 11 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0x9)++0x00 line.byte 0x00 "DCHMID_10,Channel 10 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xA)++0x00 line.byte 0x00 "DCHMID_9,Channel 9 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xB)++0x00 line.byte 0x00 "DCHMID_8,Channel 8 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xC)++0x00 line.byte 0x00 "DCHMID_15,Channel 15 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xD)++0x00 line.byte 0x00 "DCHMID_14,Channel 14 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xE)++0x00 line.byte 0x00 "DCHMID_13,Channel 13 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.byte (0x140+0xF)++0x00 line.byte 0x00 "DCHMID_12,Channel 12 Master ID Register" bitfld.byte 0x00 7. " EMI ,Enable master ID replication" "Disabled,Enabled" sif cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4") rbitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" rbitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 6. " PAL ,Privileged access level" "Not privileged,Privileged" bitfld.byte 0x00 0.--3. " MID ,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline endif tree.end base ad:0x40009000 tree "Transfer Control Descriptor Registers" tree "Channel 0" width 23. group.long 0x0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x0+0x08))&0xC0000000)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x0+0x16))&0x8000)==0x00) group.word (0x0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x0+0x1C))&0x80)==0x00) group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x0+0x1C))&0x80)==0x00) group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x0+0x1E))&0x8000)==0x00) group.word (0x0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 1" width 23. group.long 0x20++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x20+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x20+0x08))&0xC0000000)==0x00) group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x20+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x20+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x20+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x20+0x16))&0x8000)==0x00) group.word (0x20+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x20+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x20+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x20+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x20+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x20+0x1C))&0x80)==0x00) group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x20+0x1C))&0x80)==0x00) group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x20+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x20+0x1E))&0x8000)==0x00) group.word (0x20+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x20+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 2" width 23. group.long 0x40++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x40+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x40+0x08))&0xC0000000)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x40+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x40+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x40+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x40+0x16))&0x8000)==0x00) group.word (0x40+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x40+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x40+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x40+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x40+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x40+0x1C))&0x80)==0x00) group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x40+0x1C))&0x80)==0x00) group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x40+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x40+0x1E))&0x8000)==0x00) group.word (0x40+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x40+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 3" width 23. group.long 0x60++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x60+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x60+0x08))&0xC0000000)==0x00) group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x60+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x60+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x60+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x60+0x16))&0x8000)==0x00) group.word (0x60+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x60+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x60+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x60+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x60+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x60+0x1C))&0x80)==0x00) group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x60+0x1C))&0x80)==0x00) group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x60+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x60+0x1E))&0x8000)==0x00) group.word (0x60+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x60+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 4" width 23. group.long 0x80++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x80+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x80+0x08))&0xC0000000)==0x00) group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x80+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x80+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x80+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x80+0x16))&0x8000)==0x00) group.word (0x80+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x80+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x80+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x80+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x80+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x80+0x1C))&0x80)==0x00) group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x80+0x1C))&0x80)==0x00) group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x80+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x80+0x1E))&0x8000)==0x00) group.word (0x80+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x80+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 5" width 23. group.long 0xA0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xA0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xA0+0x08))&0xC0000000)==0x00) group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xA0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xA0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xA0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xA0+0x16))&0x8000)==0x00) group.word (0xA0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xA0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xA0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xA0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xA0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xA0+0x1C))&0x80)==0x00) group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xA0+0x1C))&0x80)==0x00) group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xA0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xA0+0x1E))&0x8000)==0x00) group.word (0xA0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xA0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 6" width 23. group.long 0xC0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xC0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xC0+0x08))&0xC0000000)==0x00) group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xC0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xC0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xC0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xC0+0x16))&0x8000)==0x00) group.word (0xC0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xC0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xC0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xC0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xC0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xC0+0x1C))&0x80)==0x00) group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xC0+0x1C))&0x80)==0x00) group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xC0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xC0+0x1E))&0x8000)==0x00) group.word (0xC0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xC0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 7" width 23. group.long 0xE0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0xE0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0xE0+0x08))&0xC0000000)==0x00) group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0xE0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0xE0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0xE0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0xE0+0x16))&0x8000)==0x00) group.word (0xE0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0xE0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0xE0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0xE0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0xE0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0xE0+0x1C))&0x80)==0x00) group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0xE0+0x1C))&0x80)==0x00) group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0xE0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0xE0+0x1E))&0x8000)==0x00) group.word (0xE0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0xE0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 8" width 23. group.long 0x100++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x100+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x100+0x08))&0xC0000000)==0x00) group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x100+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x100+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x100+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x100+0x16))&0x8000)==0x00) group.word (0x100+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x100+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x100+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x100+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x100+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x100+0x1C))&0x80)==0x00) group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x100+0x1C))&0x80)==0x00) group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x100+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x100+0x1E))&0x8000)==0x00) group.word (0x100+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x100+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 9" width 23. group.long 0x120++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x120+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x120+0x08))&0xC0000000)==0x00) group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x120+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x120+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x120+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x120+0x16))&0x8000)==0x00) group.word (0x120+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x120+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x120+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x120+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x120+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x120+0x1C))&0x80)==0x00) group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x120+0x1C))&0x80)==0x00) group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x120+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x120+0x1E))&0x8000)==0x00) group.word (0x120+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x120+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 10" width 23. group.long 0x140++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x140+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x140+0x08))&0xC0000000)==0x00) group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x140+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x140+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x140+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x140+0x16))&0x8000)==0x00) group.word (0x140+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x140+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x140+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x140+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x140+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x140+0x1C))&0x80)==0x00) group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x140+0x1C))&0x80)==0x00) group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x140+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x140+0x1E))&0x8000)==0x00) group.word (0x140+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x140+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 11" width 23. group.long 0x160++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x160+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x160+0x08))&0xC0000000)==0x00) group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x160+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x160+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x160+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x160+0x16))&0x8000)==0x00) group.word (0x160+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x160+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x160+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x160+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x160+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x160+0x1C))&0x80)==0x00) group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x160+0x1C))&0x80)==0x00) group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x160+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x160+0x1E))&0x8000)==0x00) group.word (0x160+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x160+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 12" width 23. group.long 0x180++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x180+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x180+0x08))&0xC0000000)==0x00) group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x180+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x180+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x180+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x180+0x16))&0x8000)==0x00) group.word (0x180+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x180+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x180+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x180+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x180+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x180+0x1C))&0x80)==0x00) group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x180+0x1C))&0x80)==0x00) group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x180+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x180+0x1E))&0x8000)==0x00) group.word (0x180+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x180+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 13" width 23. group.long 0x1A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1A0+0x08))&0xC0000000)==0x00) group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1A0+0x16))&0x8000)==0x00) group.word (0x1A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1A0+0x1C))&0x80)==0x00) group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1A0+0x1C))&0x80)==0x00) group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1A0+0x1E))&0x8000)==0x00) group.word (0x1A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 14" width 23. group.long 0x1C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1C0+0x08))&0xC0000000)==0x00) group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1C0+0x16))&0x8000)==0x00) group.word (0x1C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1C0+0x1C))&0x80)==0x00) group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1C0+0x1C))&0x80)==0x00) group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1C0+0x1E))&0x8000)==0x00) group.word (0x1C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 15" width 23. group.long 0x1E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x1E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x1E0+0x08))&0xC0000000)==0x00) group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x1E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x1E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x1E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x1E0+0x16))&0x8000)==0x00) group.word (0x1E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x1E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x1E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x1E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x1E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x1E0+0x1C))&0x80)==0x00) group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x1E0+0x1C))&0x80)==0x00) group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x1E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x1E0+0x1E))&0x8000)==0x00) group.word (0x1E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x1E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 16" width 23. group.long 0x200++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x200+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x200+0x08))&0xC0000000)==0x00) group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x200+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x200+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x200+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x200+0x16))&0x8000)==0x00) group.word (0x200+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x200+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x200+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x200+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x200+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x200+0x1C))&0x80)==0x00) group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x200+0x1C))&0x80)==0x00) group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x200+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x200+0x1E))&0x8000)==0x00) group.word (0x200+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x200+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 17" width 23. group.long 0x220++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x220+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x220+0x08))&0xC0000000)==0x00) group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x220+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x220+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x220+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x220+0x16))&0x8000)==0x00) group.word (0x220+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x220+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x220+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x220+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x220+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x220+0x1C))&0x80)==0x00) group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x220+0x1C))&0x80)==0x00) group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x220+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x220+0x1E))&0x8000)==0x00) group.word (0x220+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x220+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 18" width 23. group.long 0x240++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x240+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x240+0x08))&0xC0000000)==0x00) group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x240+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x240+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x240+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x240+0x16))&0x8000)==0x00) group.word (0x240+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x240+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x240+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x240+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x240+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x240+0x1C))&0x80)==0x00) group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x240+0x1C))&0x80)==0x00) group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x240+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x240+0x1E))&0x8000)==0x00) group.word (0x240+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x240+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 19" width 23. group.long 0x260++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x260+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x260+0x08))&0xC0000000)==0x00) group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x260+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x260+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x260+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x260+0x16))&0x8000)==0x00) group.word (0x260+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x260+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x260+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x260+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x260+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x260+0x1C))&0x80)==0x00) group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x260+0x1C))&0x80)==0x00) group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x260+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x260+0x1E))&0x8000)==0x00) group.word (0x260+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x260+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 20" width 23. group.long 0x280++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x280+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x280+0x08))&0xC0000000)==0x00) group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x280+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x280+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x280+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x280+0x16))&0x8000)==0x00) group.word (0x280+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x280+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x280+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x280+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x280+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x280+0x1C))&0x80)==0x00) group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x280+0x1C))&0x80)==0x00) group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x280+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x280+0x1E))&0x8000)==0x00) group.word (0x280+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x280+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 21" width 23. group.long 0x2A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2A0+0x08))&0xC0000000)==0x00) group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2A0+0x16))&0x8000)==0x00) group.word (0x2A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2A0+0x1C))&0x80)==0x00) group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2A0+0x1C))&0x80)==0x00) group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2A0+0x1E))&0x8000)==0x00) group.word (0x2A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 22" width 23. group.long 0x2C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2C0+0x08))&0xC0000000)==0x00) group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2C0+0x16))&0x8000)==0x00) group.word (0x2C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2C0+0x1C))&0x80)==0x00) group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2C0+0x1C))&0x80)==0x00) group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2C0+0x1E))&0x8000)==0x00) group.word (0x2C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 23" width 23. group.long 0x2E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x2E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x2E0+0x08))&0xC0000000)==0x00) group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x2E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x2E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x2E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x2E0+0x16))&0x8000)==0x00) group.word (0x2E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x2E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x2E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x2E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x2E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x2E0+0x1C))&0x80)==0x00) group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x2E0+0x1C))&0x80)==0x00) group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x2E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x2E0+0x1E))&0x8000)==0x00) group.word (0x2E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x2E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 24" width 23. group.long 0x300++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x300+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x300+0x08))&0xC0000000)==0x00) group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x300+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x300+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x300+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x300+0x16))&0x8000)==0x00) group.word (0x300+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x300+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x300+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x300+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x300+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x300+0x1C))&0x80)==0x00) group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x300+0x1C))&0x80)==0x00) group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x300+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x300+0x1E))&0x8000)==0x00) group.word (0x300+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x300+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 25" width 23. group.long 0x320++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x320+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x320+0x08))&0xC0000000)==0x00) group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x320+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x320+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x320+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x320+0x16))&0x8000)==0x00) group.word (0x320+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x320+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x320+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x320+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x320+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x320+0x1C))&0x80)==0x00) group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x320+0x1C))&0x80)==0x00) group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x320+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x320+0x1E))&0x8000)==0x00) group.word (0x320+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x320+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 26" width 23. group.long 0x340++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x340+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x340+0x08))&0xC0000000)==0x00) group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x340+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x340+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x340+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x340+0x16))&0x8000)==0x00) group.word (0x340+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x340+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x340+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x340+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x340+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x340+0x1C))&0x80)==0x00) group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x340+0x1C))&0x80)==0x00) group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x340+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x340+0x1E))&0x8000)==0x00) group.word (0x340+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x340+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 27" width 23. group.long 0x360++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x360+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x360+0x08))&0xC0000000)==0x00) group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x360+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x360+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x360+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x360+0x16))&0x8000)==0x00) group.word (0x360+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x360+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x360+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x360+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x360+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x360+0x1C))&0x80)==0x00) group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x360+0x1C))&0x80)==0x00) group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x360+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x360+0x1E))&0x8000)==0x00) group.word (0x360+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x360+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 28" width 23. group.long 0x380++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x380+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x380+0x08))&0xC0000000)==0x00) group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x380+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x380+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x380+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x380+0x16))&0x8000)==0x00) group.word (0x380+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x380+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x380+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x380+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x380+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x380+0x1C))&0x80)==0x00) group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x380+0x1C))&0x80)==0x00) group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x380+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x380+0x1E))&0x8000)==0x00) group.word (0x380+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x380+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 29" width 23. group.long 0x3A0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3A0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3A0+0x08))&0xC0000000)==0x00) group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3A0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3A0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3A0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3A0+0x16))&0x8000)==0x00) group.word (0x3A0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3A0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3A0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3A0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3A0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3A0+0x1C))&0x80)==0x00) group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3A0+0x1C))&0x80)==0x00) group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3A0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3A0+0x1E))&0x8000)==0x00) group.word (0x3A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3A0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 30" width 23. group.long 0x3C0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3C0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3C0+0x08))&0xC0000000)==0x00) group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3C0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3C0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3C0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3C0+0x16))&0x8000)==0x00) group.word (0x3C0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3C0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3C0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3C0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3C0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3C0+0x1C))&0x80)==0x00) group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3C0+0x1C))&0x80)==0x00) group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3C0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3C0+0x1E))&0x8000)==0x00) group.word (0x3C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3C0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree "Channel 31" width 23. group.long 0x3E0++0x03 line.long 0x00 "SADDR,TCD Source Address" newline group.word (0x3E0+0x04)++0x03 line.word 0x00 "SOFF,TCD Signed Source Address Offset Register" line.word 0x02 "ATTR,TCD Transfer Attributes Register" bitfld.word 0x02 11.--15. " SMOD ,Source address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK60DX256ZVMD10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline else bitfld.word 0x02 8.--10. " SSIZE ,Source data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif bitfld.word 0x02 3.--7. " DMOD ,Destination address modulo" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline sif cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte burst,?..." newline elif cpuis("MK40D*Z*10")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK30DX256VLL7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,?..." newline elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,32 byte burst,?..." newline elif cpuis("MAC57D54H-CA5")||cpuis("MAC57D53M-CA5")||cpuis("MAC57D52L-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D53M-CM0")||cpuis("MAC57D52L-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MAC57D53M-CM4")||cpuis("MAC57D52L-CM4") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,64 bit,,32 byte burst,?..." newline elif cpuis("KK60FN1M0VLQ15") bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte burst,?..." newline else bitfld.word 0x02 0.--2. " DSIZE ,Destination data transfer size" "8 bit,16 bit,32 bit,,16 byte,32 byte,?..." newline endif newline if (((per.l(ad:0x40008000))&0x80)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLNO,TCD Minor Byte Count" elif (((per.l(ad:0x40009000+0x3E0+0x08))&0xC0000000)==0x00) group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFNO,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long 0x00 0.--29. 1. " NBYTES ,Minor byte transfer count" else group.long (0x3E0+0x08)++0x03 line.long 0x00 "NBYTES_MLOFFYES,TCD Signed Minor Loop Offset" bitfld.long 0x00 31. " SMLOE ,Source minor loop offset enable" "Disabled,Enabled" bitfld.long 0x00 30. " DMLOE ,Destination minor loop offset enable" "Disabled,Enabled" newline hexmask.long.tbyte 0x00 10.--29. 0x4 " MLOFF ,Sign extended offset applied to the source/destination address" hexmask.long.word 0x00 0.--9. 1. " NBYTES ,Minor byte transfer count" endif group.long (0x3E0+0x0C)++0x07 line.long 0x00 "SLAST,TCD Last Source Address Adjustment" line.long 0x04 "DADDR,TCD Destination Address" newline group.word (0x3E0+0x14)++0x01 line.word 0x00 "DOFF,TCD Signed Destination Address Offset" if (((per.w(ad:0x40009000+0x3E0+0x16))&0x8000)==0x00) group.word (0x3E0+0x16)++0x01 line.word 0x00 "CITER_ELINKNO,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " CITER ,Current major iteration count" else group.word (0x3E0+0x16)++0x01 line.word 0x00 "CITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63F*")&&!cpuis("MK64F*") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else bitfld.word 0x00 9.--12. " LINKCH ,Minor loop ink channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " CITER ,Current major iteration count" endif newline group.long (0x3E0+0x18)++0x03 line.long 0x00 "DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address" newline if ((((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x00)&&(((per.w(ad:0x40009000+0x3E0+0x1E))&0x7FFF)==0x01))||((((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x8000)&&(((per.w(ad:0x40009000+0x3E0+0x1E))&0x1FF)==0x01)) if (((per.w(ad:0x40009000+0x3E0+0x1C))&0x80)==0x00) group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif else if (((per.w(ad:0x40009000+0x3E0+0x1C))&0x80)==0x00) group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif bitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" bitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" else group.word (0x3E0+0x1C)++0x01 line.word 0x00 "CSR,TCD Control And Status" sif cpuis("MK6?F*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline endif sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60D*") bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" newline sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" else bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--9. " MAJORLINKCH ,Link channel number" "0,1,2,3" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline elif cpuis("MK70*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" newline bitfld.word 0x00 8.--12. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40D*Z*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MKS2?FN???V??12") bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 8 cycles" else bitfld.word 0x00 14.--15. " BWC ,Bandwidth control" "Not stalled,,Stalled for 4 cycles,Stalled for 4 cycles" endif newline bitfld.word 0x00 8.--11. " MAJORLINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 7. " DONE ,Channel done" "Not completed,Completed" newline endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MAC57D54H-CA5")||cpuis("MAC57D54H-CM0")||cpuis("MAC57D54H-CM4")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MKS2?FN???V??12")||cpuis("MK63FN1M0VLQ12R") rbitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline else bitfld.word 0x00 6. " ACTIVE ,Channel active" "Not active,Active" newline endif rbitfld.word 0x00 5. " MAJORELINK ,Enable channel-to-channel linking on major loop complete" "Disabled,Enabled" rbitfld.word 0x00 4. " ESG ,Enable scatter/gather processing" "Disabled,Enabled" newline bitfld.word 0x00 3. " DREQ ,Disable request" "No,Yes" bitfld.word 0x00 2. " INTHALF ,Enable an interrupt when major counter is half complete" "Disabled,Enabled" newline bitfld.word 0x00 1. " INTMAJOR ,Enable an interrupt when major iteration count completes" "Disabled,Enabled" bitfld.word 0x00 0. " START ,Channel start" "Not started,Started" endif endif if (((per.w(ad:0x40009000+0x3E0+0x1E))&0x8000)==0x00) group.word (0x3E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKNO,TCD Beginning Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" hexmask.word 0x00 0.--14. 1. " BITER ,Starting major iteration count" else group.word (0x3E0+0x1E)++0x01 line.word 0x00 "BITER_ELINKYES,TCD Current Minor Loop Link (Major Loop Count)" bitfld.word 0x00 15. " ELINK ,Enable channel-to-channel linking on minor-loop complete" "Disabled,Enabled" newline sif cpuis("MK6?F*")||cpuis("MK70*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10*")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK63F*")&&!cpuis("MK64F*")&&!cpuis("MK60D*")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.word 0x00 9.--13. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" elif cpuis("MK22*DC10")||cpuis("MK22*LL10")||cpuis("MK22*MP10")||cpuis("MK22*LH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") bitfld.word 0x00 9.--10. " LINKCH ,Link channel number" "0,1,2,3" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif else bitfld.word 0x00 9.--12. " LINKCH ,Link channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.word 0x00 0.--8. 1. " BITER ,Starting major iteration count" endif endif tree.end tree.end width 0x0B tree.end tree "EWM (External Watchdog Monitor)" base ad:0x40061000 width 14. group.byte 0x00++0x00 line.byte 0x00 "CTRL,Control Register" sif !cpuis("MK60*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 3. " INTEN ,Interrupt enable" "Disabled,Enabled" endif bitfld.byte 0x00 2. " INEN ,Enables the EWM_in port" "Disabled,Enabled" bitfld.byte 0x00 1. " ASSIN ,Inverts the assert state to a logic one" "Not inverted,Inverted" bitfld.byte 0x00 0. " EWMEN ,EWM module enable" "Disabled,Enabled" wgroup.byte 0x01++0x00 line.byte 0x00 "SERV,Service Register" group.byte 0x02++0x01 line.byte 0x00 "CMPL,Compare Low Register" line.byte 0x01 "CMPH,Compare High Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") group.byte 0x04++0x00 line.byte 0x00 "CLKCTRL,Clock Control Register" bitfld.byte 0x00 0.--1. " CLKSEL ,Low power clock source select" "lpo_clk[0],lpo_clk[1],lpo_clk[2],lpo_clk[3]" endif sif !cpuis("MK40D*Z*10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") sif cpuis("MK40D*10")||cpuis("MK5?D*10")||cpuis("MK60D*10")||cpuis("MK02*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK20DN512VLK10R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK60DN512VMC10*")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK20DX256VLK10R") group.byte 0x05++0x00 line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register" endif endif width 0x0B tree.end tree "WDOG (Watchdog Timer)" base ad:0x40052000 width 9. group.word 0x00++0x17 line.word 0x00 "STCTRLH,Watchdog Status And Control Register High" bitfld.word 0x00 14. " DISTESTWDOG ,WDOG functional test mode disable" "No,Yes" bitfld.word 0x00 12.--13. " BYTESEL ,Select the byte to be tested" "Byte 0,Byte 1,Byte 2,Byte 3" bitfld.word 0x00 11. " TESTSEL ,Selects the test to be run on the watchdog timer" "Quick test,Byte test" newline bitfld.word 0x00 10. " TESTWDOG ,Functional test mode enable" "Disabled,Enabled" sif cpuis("MK20DN512*AB10R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.word 0x00 8. " STNDBYEN ,Enables WDOG in standby mode" "Disabled,Enabled" endif newline bitfld.word 0x00 7. " WAIT_EN ,Enables WDOG in wait mode" "Disabled,Enabled" bitfld.word 0x00 6. " STOPEN ,Enables WDOG in stop mode" "Disabled,Enabled" bitfld.word 0x00 5. " DBGEN ,Enables WDOG in debug mode" "Disabled,Enabled" newline bitfld.word 0x00 4. " ALLOWUPDATE ,Enables updates to watchdog write once registers" "Disabled,Enabled" bitfld.word 0x00 3. " WINEN ,Enable windowing mode" "Disabled,Enabled" bitfld.word 0x00 2. " IRQRSTEN ,Enable the debug breadcrumbs feature" "Disabled,Enabled" newline bitfld.word 0x00 1. " CLKSRC ,Selects clock source for the WDOG timer and other internal timing operations" "LPO Osc,Alternate" bitfld.word 0x00 0. " WDOGEN ,Enables the WDOG operation" "Disabled,Enabled" line.word 0x02 "STCTRLL,Watchdog Status And Control Register Low" eventfld.word 0x02 15. " INTFLG ,Interrupt flag" "No interrupt,Interrupt" line.word 0x04 "TOVALH,Watchdog Time-out Value Register High" line.word 0x06 "TOVALL,Watchdog Time-out Value Register Low" line.word 0x08 "WINH,Watchdog Window Register High" line.word 0x0A "WINL,Watchdog Window Register Low" line.word 0x0C "REFRESH,Watchdog Refresh Register" line.word 0x0E "UNLOCK,Watchdog Unlock Register" line.word 0x10 "TMROUTH,Watchdog Timer Output Register High" line.word 0x12 "TMROUTL,Watchdog Timer Output Register Low" line.word 0x14 "RSTCNT,Watchdog Reset Count Register" line.word 0x16 "PRESC,Watchdog Prescaler Register" bitfld.word 0x16 8.--10. " PRESCVAL ,3-bit prescaler for the watchdog clock source" "/1,/2,/3,/4,/5,/6,/7,/8" width 0x0B tree.end tree.end tree.open "Clock Modules" tree "MCG (Multipurpose Clock Generator)" base ad:0x40064000 width 7. if (((per.b(ad:0x40064000+0x001))&0x30)==0x00||((per.b(ad:0x40064000+0x00C))&0x01)==0x01) group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" sif cpuis("MK11DN512AVLK5*") bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" ",Internal ref clk,External ref clk,?..." newline else bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." newline endif bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" else group.byte 0x00++0x00 line.byte 0x00 "C1,MCG Control 1 Register" bitfld.byte 0x00 6.--7. " CLKS ,Clock source select" "Out FLL/PLL,Internal ref clk,External ref clk,?..." sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK63FN1M0VLQ12")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0VMI18")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK66FN2M0VLQ18") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" elif cpuis("MK40D*Z*10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK??F*")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,?..." else bitfld.byte 0x00 3.--5. " FRDIV ,FLL external reference divider" "/32,/64,/128,/256,/512,/1024,/1280,/1536" endif newline bitfld.byte 0x00 2. " IREFS ,Internal reference select" "External,Internal" bitfld.byte 0x00 1. " IRCLKEN ,Internal reference clock enable" "Disabled,Enabled" bitfld.byte 0x00 0. " IREFSTEN ,Internal reference stop enable" "Disabled,Enabled" endif group.byte 0x01++0x01 line.byte 0x00 "C2,MCG Control 2 Register" sif !cpuis("MK20D*AB10")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " LOCRE0 ,Loss of clock reset enable" "Interrupt,Reset" newline endif sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5"))||cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60D*") sif !cpuis("MK60D*")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 6. " FCFTRIM ,Fast internal reference clock fine trim" "Increased,Decreased" endif bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline else sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-39kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline elif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "32kHz-40kHz,3MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline else bitfld.byte 0x00 4.--5. " RANGE ,Frequency range select" "1kHz-32kHz,1MHz-8MHz,8MHz-32MHz,8MHz-32MHz" newline endif bitfld.byte 0x00 3. " HGO ,High gain oscillator select" "Low-power,High-gain" newline endif bitfld.byte 0x00 2. " EREFS ,External reference select" "Ext ref,Osc" bitfld.byte 0x00 1. " LP ,Low power select" "FLL||PLL enabled,FLL||PLL disabled" bitfld.byte 0x00 0. " IRCS ,Internal reference clock select" "Slow,Fast" line.byte 0x01 "C3,MCG Control 3 Register" if (((per.b(ad:0x40064000+0x003))&0x60)==0x00) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "20 - 25 MHz,24 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x20) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,Dco maximum frequency with 32.768 kHz reference" "40 - 50 MHz,48 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" elif (((per.b(ad:0x40064000+0x03))&0x60)==0x40) group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "60 - 75 MHz,72 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" else group.byte 0x03++0x00 line.byte 0x00 "C4,MCG Control 4 Register" bitfld.byte 0x00 7. " DMX32 ,DCO maximum frequency with 32.768 kHz reference" "80 - 100 MHz,96 MHz" bitfld.byte 0x00 5.--6. " DRST_DRS ,DCO range select" "Low range,Mid range,Mid-high range,High range" bitfld.byte 0x00 1.--4. " FCTRIM ,Fast internal reference clock trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.byte 0x00 0. " SCFTRIM ,Slow internal reference clock fine trim" "Decrease the period,Increase th period" endif sif !cpuis("MK02*") sif cpuis("MK??F*")||cpuis("MK60D*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. "PLLREFSEL0,PLL0 external reference select" "OSC0,OSC1" endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif !cpuis("MK21F*") group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK63FN1M0VLQ12R") newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*") bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "OSC0,OSC1" else bitfld.byte 0x00 7. " PLLREFSEL ,PLL0 external reference select" "Disabled,Enabled" endif endif bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" sif CPUIS("MK20FN1M0VLQ12R") newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" elif cpuis("MK20F*")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." else newline bitfld.byte 0x00 0.--2. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" endif else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" else group.byte 0x04++0x00 line.byte 0x00 "C5,MCG Control 5 Register" bitfld.byte 0x00 6. " PLLCLKEN ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x00 5. " PLLSTEN ,PLL stop enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " PRDIV ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,?..." endif group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 7. " LOLIE ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " PLLS ,PLL select" "FLL,PLL" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM14Z64CHH5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*") sif !cpuis("MK20F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK70F*")&&!cpuis("MK8?FN256V*")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10") newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") newline bitfld.byte 0x00 0.--4. " CHGPMP_BIAS ,PLL charge pump current" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else newline bitfld.byte 0x00 0.--4. " VDIV ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif endif else group.byte 0x05++0x00 line.byte 0x00 "C6,MCG Control 6 Register" bitfld.byte 0x00 5. " CME ,Clock monitor enable" "Disabled,Enabled" endif rgroup.byte 0x06++0x00 line.byte 0x00 "S,MCG Status Register" sif !cpuis("MK02*") bitfld.byte 0x00 7. " LOLS ,Loss of lock status" "Not lost,Lost" bitfld.byte 0x00 6. " LOCK ,Lock status" "Not locked,Locked" bitfld.byte 0x00 5. " PLLST ,PLL select status" "FLL,PLL" newline bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,Out PLL" bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline else bitfld.byte 0x00 4. " IREFST ,Internal reference status" "External,Internal" bitfld.byte 0x00 2.--3. " CLKST ,Clock mode status" "Out FLL,Internal ref,External ref,?..." bitfld.byte 0x00 1. " OSCINIT ,OSC initialization" "Not completed,Completed" newline endif bitfld.byte 0x00 0. " IRCST ,Internal reference clock status" "Slow clock,Fast clock" sif cpuis("MK20D*AB10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" elif cpuis("KK60DN512ZCAB10R") group.byte 0x08++0x00 line.byte 0x00 "ATC,MCG Auto Trim Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else group.byte 0x08++0x00 line.byte 0x00 "SC,MCG Status And Control Register" bitfld.byte 0x00 7. " ATME ,Automatic trim machine enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATMS ,Automatic trim machine select" "32kHz,4MHz" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" else eventfld.byte 0x00 5. " ATMF ,Automatic trim machine fail flag" "Not occurred,Occurred" endif newline bitfld.byte 0x00 4. " FLTPRSRV ,FLL filter preserve enable" "Disabled,Enabled" bitfld.byte 0x00 1.--3. " FCIRDIV ,Fast clock internal reference divider" "/1,/2,/4,/8,/16,/32,/64,/128" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") rbitfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" else eventfld.byte 0x00 0. " LOCS ,OSC0 loss of clock status" "Not occurred,Occurred" endif endif group.byte 0x0A++0x01 line.byte 0x00 "ATCVH,MCG Auto Trim Compare Value High Register" line.byte 0x01 "ATCVL,MCG Auto Trim Compare Value Low Register" sif !cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30DN512ZVLQ10")&&!cpuis("MK30DN512ZVLQ10R")&&!cpuis("MK30DX256ZVLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5*")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5*")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 6.--7. " PLL32KREFSEL ,MCG PLL 32kHz reference clock select" "32kHz RTC,32kHz IRC,FLL FRDIV,?..." sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")||cpuis("MKM33Z128CLH5*") newline bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" else newline bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." endif elif cpuis("MK02*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512CAP12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0.--1. " OSCSEL ,MCG OSC clock select" "OSCCLK0,32kHz RTC,OSCCLK1,?..." else group.byte 0x0C++0x00 line.byte 0x00 "C7,MCG Control 7 Register" bitfld.byte 0x00 0. " OSCSEL ,MCG OSC clock select" "OSCCLK,32kHz RTC" endif sif !cpuis("MK70*")&&!cpuis("MK02*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK60FN1M0VLQ15") group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 6. " LOLRE ,PLL loss of lock reset enable" "Interrupt,Reset" endif bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" else group.byte 0x0D++0x00 line.byte 0x00 "C8,MCG Control 8 Register" bitfld.byte 0x00 7. " LOCRE1 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 5. " CME1 ,Clock monitor enable" "Disabled,Enabled" newline sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x00 4. " COARSE_LOLIE ,Loss of coarse lock interrupt enable" "No interrupt,Interrupt" newline endif eventfld.byte 0x00 0. " LOCS1 ,RTC loss of clock status" "Not occurred,Occurred" endif sif !cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK30DX256VLL7R")&&!cpuis("MK02F*")&&!cpuis("MK63FN1M0VLQ12R") sif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5*")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) rgroup.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 7. " COARSE_LOLS ,Coarse loss of lock status" "Not occurred,Occurred" bitfld.byte 0x00 6. " COARSE_LOCK ,Coarse lock status" "Unlocked,Locked" elif cpuis("MK66*")||cpuis("MK65*")||cpuis("KK65FN2M0CAC18R")||cpuis("MK63FN1M0VLQ12R") group.byte 0x0E++0x00 line.byte 0x00 "C9,MCG Control 9 Register" bitfld.byte 0x00 5. " PLL_CME ,MCG external PLL clock monitor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " PLL_LOCRE ,MCG external PLL loss of clock reset enable" "Interrupt,Sys. reset" eventfld.byte 0x00 0. " EXT_PLL_LOCS ,External PLL loss of clock status" "Not occurred,Occurred" elif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("MK10F*")&&!cpuis("MK10D*5")&&!cpuis("MK70*")&&!cpuis("MK11*")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60DN512ZCAB10R") hgroup.byte 0x0E++0x00 hide.byte 0x00 "C9,MCG Control 9 Register" endif sif !cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM33Z128CLH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MK11DN512AVLK5")&&!cpuis("MK11DN512VLK5*") sif cpuis("MK??F*")||cpuis("KK60FN1M0VLQ15") sif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("KK65FN2M0CAC18R") group.byte 0x0F++0x02 line.byte 0x00 "C10,MCG Control 10 Register" bitfld.byte 0x00 7. " LOCRE2 ,Loss of clock reset enable" "Interrupt,Reset" bitfld.byte 0x00 4.--5. " RANGE1 ,Frequency range select" "Encoding 0,Encoding 1,Encoding 2,Encoding 2" bitfld.byte 0x00 3. " HGO1 ,High gain oscillator select" "Low-power,High-gain" newline bitfld.byte 0x00 2. " EREFS1 ,External reference select" "Ext ref,Osc" line.byte 0x01 "C11,MCG Control 11 Register" sif cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "OSC0,OSC1" else bitfld.byte 0x01 7. " PLLREFSEL1 ,PLL1 external reference select" "Disabled,Enabled" endif newline bitfld.byte 0x01 6. " PLLCLKEN1 ,PLL clock enable" "Disabled,Enabled" bitfld.byte 0x01 5. " PLLSTEN1 ,PLL stop enable" "Disabled,Enabled" newline bitfld.byte 0x01 4. " PLLCS ,PLL clock select" "PLL0,PLL1" bitfld.byte 0x01 0.--2. " PRDIV1 ,PLL external reference divider" "/1,/2,/3,/4,/5,/6,/7,/8" line.byte 0x02 "C12,MCG Control 12 Register" bitfld.byte 0x02 7. " LOLIE1 ,Loss of lock interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " CME2 ,Clock monitor enable" "Disabled,Enabled" newline sif !cpuis("MK20F*")&&!cpuis("MK21F*")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55" else bitfld.byte 0x02 0.--4. " VDIV1 ,VCO divider" "/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47" endif rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status Register" sif !cpuis("KK60FN1M0VLQ15") bitfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" else eventfld.byte 0x00 7. " LOLS1 ,Loss of lock status" "Not lost,Lost" endif bitfld.byte 0x00 6. " LOCK1 ,Lock status" "Not locked,Locked" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL1" newline bitfld.byte 0x00 1. " OSCINIT1 ,OSC initialization" "Not completed,Completed" bitfld.byte 0x00 0. " LOCS2 ,OSC1 loss of clock status" "No loss of OSC1,Loss of OSC1" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" endif elif cpuis("MK66*")||cpuis("MK65*") group.byte 0x10++0x00 line.byte 0x00 "C11,MCG Control 11 Register" bitfld.byte 0x00 4. " PLLCS ,PLL clock select" "PLL0,PLL_EXT" hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" rgroup.byte 0x12++0x00 line.byte 0x00 "S2,MCG Status 2 Register" bitfld.byte 0x00 4. " PLLCST ,PLL clock select status" "PLL0,PLL_EXT" hgroup.byte 0x13++0x00 hide.byte 0x00 "T3,MCG Test 3 Register" elif !cpuis("MK10D*5")&&!cpuis("MK64*")&&!cpuis("MK63*") hgroup.byte 0x0F++0x00 hide.byte 0x00 "C10,MCG Control 10 Register" elif cpuis("MK63FN1M0VLQ12R") hgroup.byte 0x11++0x00 hide.byte 0x00 "C12,MCG Control 12 Register" endif endif endif endif width 0x0B tree.end tree.open "OSC (Oscillator)" tree "OSC1" base ad:0x40065000 width 4. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKV5*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18*") width 9. newline group.byte 0x02++0x00 line.byte 0x00 "OSC_DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree "OSC2" base ad:0x400E5000 width 4. group.byte 0x00++0x00 line.byte 0x00 "CR,OSC Control Register" bitfld.byte 0x00 7. " ERCLKEN ,External reference enable" "Disabled,Enabled" bitfld.byte 0x00 5. " EREFSTEN ,External reference stop enable" "Disabled,Enabled" bitfld.byte 0x00 3. " SC2P ,Oscillator 2 pF capacitor load configure" "Disabled,Enabled" newline bitfld.byte 0x00 2. " SC4P ,Oscillator 4 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 1. " SC8P ,Oscillator 8 pF capacitor load configure" "Disabled,Enabled" bitfld.byte 0x00 0. " SC16P ,Oscillator 16 pF capacitor load configure" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MKV5*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18*") width 9. newline group.byte 0x02++0x00 line.byte 0x00 "OSC_DIV,OSC Clock Divider Register" bitfld.byte 0x00 6.--7. " ERPS ,ERCLK prescaler" "/1,/2,/4,/8" endif width 0x0B tree.end tree.end tree.end tree.open "Memories and Memory Interfaces" tree "LMEM (Local Memory Controller)" base ad:0xE0082000 width 8. group.long 0x00++0x03 line.long 0x00 "PCCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Disabled,Enabled" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "Disabled,Enabled" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "Disabled,Enabled" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "Disabled,Enabled" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "Disabled,Enabled" newline sif cpuis("MK65*")||cpuis("MK66*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK65FN2M0CAC18*") bitfld.long 0x00 3. " PCCR3 ,Forces no allocation on cache misses (must also have PCCR2 asserted)" "Not forced,Forced" bitfld.long 0x00 2. " PCCR2 ,Forces all cacheable spaces to write through" "Not forced,Forced" newline endif bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" sif cpuis("MK65*")||cpuis("MK66*")||cpuis("MK26*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK65FN2M0CAC18*")||cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x00) group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " CSAR ,CCSAR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" else group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "Way 0,Way 1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "No effect/Not active,Initiated/Active" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.byte 0x04 4.--11. 0x10 " CSAR ,CSAR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" endif if (((per.l(ad:0xE0082000+0x04))&0x10000)==0x00) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" elif (((per.l(ad:0xE0082000+0x04))&0x8010000)==0x0010000) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " CCVR ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " CCVR ,CCVR bits are used for tag set address on reads" newline bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "0,1" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "0,1" elif (((per.l(ad:0xE0082000+0x04))&0x8010000)==0x8010000) group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " CCVR ,Tag array R/W value" newline bitfld.long 0x00 1. " CCVR[1] ,Tag modify bit" "0,1" bitfld.long 0x00 0. " CCVR[0] ,Tag valid bit" "0,1" endif else group.long 0x04++0x07 line.long 0x00 "PCCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "Way 0,Way 1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" newline hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR[11:2] ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "0,1" line.long 0x04 "PCCSAR,Cache Search Address Register" hexmask.long 0x04 2.--31. 0x04 " PHYADDR ,Physical address" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "0,1" group.long 0x0C++0x03 line.long 0x00 "PCCCVR,Cache Read/Write Value Register" endif sif cpuis("MK65*")||cpuis("MK66*")||cpuis("KK65FN2M0CAC18*")||cpuis("KK60FN1M0VLQ15") group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" sif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" ",,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" ",,Write-through,?..." newline bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (external memory - write-back)" ",,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (external memory - write-through)" ",,Write-through,?..." elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" ",,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" ",,Write-through,?..." newline bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" ",,Write-through,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (external memory - write-back)" ",,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,DRAM Controller" ",,Write-through,Write-back" endif elif cpuis("MK20FN1M0VLQ12R") group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,Flexbus (External memory - Write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 10.--11. " R10 ,FlexBus (external peripheral)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 8.--9. " R11 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 6.--7. " R12 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 4.--5. " R13 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." else group.long 0x20++0x03 line.long 0x00 "PCCRMR,Cache Regions Mode Register" bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 28.--29. " R1 ,Region 1 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 18.--19. " R6 ,Region 6 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,Region 7 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 14.--15. " R8 ,Region 8 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,Region 9 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 10.--11. " R10 ,Region 10 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 8.--9. " R11 ,Region 11 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 6.--7. " R12 ,Region 12 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 4.--5. " R13 ,Region 13 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 2.--3. " R14 ,Region 14 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 0.--1. " R15 ,Region 15 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" endif sif !cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("MK26*")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("KK65FN2M0CAC18*") group.long 0x800++0x03 line.long 0x00 "PSCCR,Cache Control Register" bitfld.long 0x00 31. " GO ,Initiate cache command" "Disabled,Enabled" bitfld.long 0x00 27. " PUSHW1 ,Push way 1" "Disabled,Enabled" bitfld.long 0x00 26. " INVW1 ,Invalidate way 1" "Disabled,Enabled" newline bitfld.long 0x00 25. " PUSHW0 ,Push way 0" "Disabled,Enabled" bitfld.long 0x00 24. " INVW0 ,Invalidate way 0" "Disabled,Enabled" bitfld.long 0x00 1. " ENWRBUF ,Enable write buffer" "Disabled,Enabled" newline bitfld.long 0x00 0. " ENCACHE ,Cache enable" "Disabled,Enabled" if (((per.l(ad:0xE0082000+0x804))&0x10000)==0x00) group.long 0x804++0x07 line.long 0x00 "PSCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.word 0x00 2.--11. 0x04 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PSCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.word 0x04 2.--11. 0x04 " CSAR ,CCSAR bits are used to access the data arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" else group.long 0x804++0x07 line.long 0x00 "PSCLCR,Cache Line Control Register" bitfld.long 0x00 27. " LACC ,Line access type" "Read,Write" bitfld.long 0x00 26. " LADSEL ,Line address select" "Cache address,Physical address" bitfld.long 0x00 24.--25. " LCMD ,Line command" "Search and R/W,Invalidate,Push,Clear" newline rbitfld.long 0x00 22. " LCWAY ,Line command way" "0,1" rbitfld.long 0x00 21. " LCIMB ,Line command initial modified bit" "0,1" rbitfld.long 0x00 20. " LCIVB ,Line command initial valid bit" "0,1" newline bitfld.long 0x00 16. " TDSEL ,Tag/Data select" "Data,Tag" bitfld.long 0x00 14. " WSEL ,Way select" "Way 0,Way 1" hexmask.long.byte 0x00 4.--11. 0x10 " CACHEADDR ,Cache address" bitfld.long 0x00 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" line.long 0x04 "PSCSAR,Cache Search Address Register" hexmask.long.tbyte 0x04 12.--31. 0x10 " CSAR ,CSAR bits are used for tag compare" hexmask.long.byte 0x04 4.--11. 0x10 " CSAR ,CCSAR bits are used to access the tag arrays" bitfld.long 0x04 0. " LGO ,Initiate cache line command" "Not initiated,Initiated" sif cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0xE0082000+0x804))&0x8000000)==0x00) group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " TAG_ADDR ,Tag set address" else group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" endif else group.long 0x80C++0x03 line.long 0x00 "PSCCVR,Cache Read/Write Value Register" hexmask.long.tbyte 0x00 12.--31. 1. " TAG_VALUE ,Tag array R/W value" hexmask.long.byte 0x00 4.--11. 0x10 " TAG_ADDR ,Tag set address" endif endif group.long 0x820++0x03 line.long 0x00 "PSCRMR,Cache Regions Mode Register" sif cpuis("MK20FN1M0VLQ12R") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (Aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,Flexbus (External memory - Write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 10.--11. " R10 ,FlexBus (external peripheral)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 8.--9. " R11 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 6.--7. " R12 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 4.--5. " R13 ,FlexBus (External memory - Write-through)" "Non-cacheable,Non-cacheable,?..." elif cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 30.--31. " R0 ,Program flash and read-only data" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 28.--29. " R1 ,DRAM Controller (aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 26.--27. " R2 ,FlexNVM" "Non-cacheable,Non-cacheable,Write-through,?..." bitfld.long 0x00 24.--25. " R3 ,FlexBus (aliased Area)" "Non-cacheable,Non-cacheable,Write-through,?..." newline bitfld.long 0x00 22.--23. " R4 ,SRAM_L: Lower SRAM (ICODE/DCODE)" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 20.--21. " R5 ,SRAM_U: Upper SRAM" "Non-cacheable,Non-cacheable,?..." bitfld.long 0x00 18.--19. " R6 ,FlexBus (extermal memory - write-back)" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,FlexBus (external memory - write-through)" "Non-cacheable,Non-cacheable,Write-through,?..." else bitfld.long 0x00 30.--31. " R0 ,Region 0 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 28.--29. " R1 ,Region 1 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 26.--27. " R2 ,Region 2 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 24.--25. " R3 ,Region 3 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 22.--23. " R4 ,Region 4 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 20.--21. " R5 ,Region 5 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 18.--19. " R6 ,Region 6 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 16.--17. " R7 ,Region 7 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 14.--15. " R8 ,Region 8 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 12.--13. " R9 ,Region 9 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 10.--11. " R10 ,Region 10 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 8.--9. " R11 ,Region 11 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" newline bitfld.long 0x00 6.--7. " R12 ,Region 12 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 4.--5. " R13 ,Region 13 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 2.--3. " R14 ,Region 14 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" bitfld.long 0x00 0.--1. " R15 ,Region 15 mode" "Non-cacheable,Non-cacheable,Write-through,Write-back" endif endif width 0x0B tree.end tree "FMC (Flash Memory Controller)" base ad:0x4001f000 width 9. sif cpuis("MK02*")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MK20FN1M0VLQ12R") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" newline bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MK66*")||cpuis("MK65*") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" endif bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" newline bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" endif bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("?K26*") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MK64*")||cpuis("MK63*") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" endif bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" newline bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" endif bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MK21F*MC12")||cpuis("MK24F*LL12")||cpuis("MK24F*DC12")||cpuis("MK24F*LQ12")||cpuis("MK22F*LQ12")||cpuis("MK22F*MD12")||cpuis("MK21F*LQ")||cpuis("MK21F*MD")||cpuis("MK20DN512ZCAB10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" elif cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12") group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" else group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" sif !cpuis("MK?0D*5")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN256VDC12") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline endif bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" newline bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline sif !cpuis("MK?0D*5")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN256VDC12") bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline endif bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" endif else group.long 0x00++0x03 line.long 0x00 "PFAPR,Flash Access Protection Register" sif !cpuis("MK?0D*5")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN256VDC12") bitfld.long 0x00 23. " M7PFD ,Master 7 prefetch disable" "No,Yes" bitfld.long 0x00 22. " M6PFD ,Master 6 prefetch disable" "No,Yes" newline bitfld.long 0x00 21. " M5PFD ,Master 5 prefetch disable" "No,Yes" bitfld.long 0x00 20. " M4PFD ,Master 4 prefetch disable" "No,Yes" newline endif bitfld.long 0x00 19. " M3PFD ,Master 3 prefetch disable" "No,Yes" bitfld.long 0x00 18. " M2PFD ,Master 2 prefetch disable" "No,Yes" newline bitfld.long 0x00 17. " M1PFD ,Master 1 prefetch disable" "No,Yes" bitfld.long 0x00 16. " M0PFD ,Master 0 prefetch disable" "No,Yes" newline sif !cpuis("MK?0D*5")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN256VDC12") bitfld.long 0x00 14.--15. " M7AP ,Master 7 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 12.--13. " M6AP ,Master 6 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 10.--11. " M5AP ,Master 5 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 8.--9. " M4AP ,Master 4 access protection" "No access,RO accesses,WO accesses,RW accesses" newline endif bitfld.long 0x00 6.--7. " M3AP ,Master 3 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 4.--5. " M2AP ,Master 2 access protection" "No access,RO accesses,WO accesses,RW accesses" newline bitfld.long 0x00 2.--3. " M1AP ,Master 1 access protection" "No access,RO accesses,WO accesses,RW accesses" bitfld.long 0x00 0.--1. " M0AP ,Master 0 access protection" "No access,RO accesses,WO accesses,RW accesses" endif sif cpuis("MK65*")||cpuis("MK66*")||cpuis("?K26*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long 0x04++0x03 line.long 0x00 "PFB01CR,Flash Bank 0-1 Control Register" rbitfld.long 0x00 28.--31. " B01RWSC ,Bank 0-1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 27. " CLCK_WAY[3] ,Cache lock way 3" "Not locked,Locked" bitfld.long 0x00 26. " [2] ,Cache lock way 2" "Not locked,Locked" bitfld.long 0x00 25. " [1] ,Cache lock way 1" "Not locked,Locked" bitfld.long 0x00 24. " [0] ,Cache lock way 0" "Not locked,Locked" newline bitfld.long 0x00 23. " CINV_WAY[3] ,Cache invalidate way 3" "Not invalidated,Invalidated" bitfld.long 0x00 22. " [2] ,Cache invalidate way 2" "Not invalidated,Invalidated" bitfld.long 0x00 21. " [1] ,Cache invalidate way 1" "Not invalidated,Invalidated" bitfld.long 0x00 20. " [0] ,Cache invalidate way 0" "Not invalidated,Invalidated" newline bitfld.long 0x00 19. " S_B_INV ,Invalidate prefetch speculation buffer" "Not invalidated,Invalidated" rbitfld.long 0x00 17.--18. " B01MW ,Bank 0-1 memory width" "32 bits,64 bits,128 bits,?..." bitfld.long 0x00 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline bitfld.long 0x00 4. " B01DCE ,Bank 0-1 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B01ICE ,Bank 0-1 instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 2. " B01DPE ,Bank 0-1 data prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " B01IPE ,Bank 0-1 instruction prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0. " B01SEBE ,Bank 0-1 single entry buffer enable" "Disabled,Enabled" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") group.long 0x08++0x03 line.long 0x00 "PFB1CR,Flash Bank 1 Control Register" rbitfld.long 0x00 28.--31. " B1RWSC ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..." newline bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B1SEBE ,Bank 1 single entry buffer enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "PFB23CR,Flash Bank 2-3 Control Register" rbitfld.long 0x00 28.--31. " B23RWSC ,Bank 2-3 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rbitfld.long 0x00 17.--18. " B23MW ,Bank 2-3 memory width" "32 bits,64 bits,128 bits,?..." newline bitfld.long 0x00 4. " B23DCE ,Bank 2-3 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B23ICE ,Bank 2-3 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B23DPE ,Bank 2-3 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B23IPE ,Bank 2-3 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B23SEBE ,Bank 2-3 single entry buffer enable" "Disabled,Enabled" endif else group.long 0x04++0x03 line.long 0x00 "PFB0CR,Flash Bank 0 Control Register" rbitfld.long 0x00 28.--31. " B0RWSC ,Bank 0 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" newline bitfld.long 0x00 27. " CLCK_WAY[3] ,Cache lock way 3" "Not locked,Locked" bitfld.long 0x00 26. " [2] ,Cache lock way 2" "Not locked,Locked" bitfld.long 0x00 25. " [1] ,Cache lock way 1" "Not locked,Locked" bitfld.long 0x00 24. " [0] ,Cache lock way 0" "Not locked,Locked" newline bitfld.long 0x00 23. " CINV_WAY[3] ,Cache invalidate way 3" "Not invalidated,Invalidated" bitfld.long 0x00 22. " [2] ,Cache invalidate way 2" "Not invalidated,Invalidated" bitfld.long 0x00 21. " [1] ,Cache invalidate way 1" "Not invalidated,Invalidated" bitfld.long 0x00 20. " [0] ,Cache invalidate way 0" "Not invalidated,Invalidated" newline sif cpuis("MK2?D*")||cpuis("MK1?D*")||cpuis("MK02*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS2?FN???V??12")||cpuis("KK20DN512ZCAB10R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512V??12*")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12") bitfld.long 0x00 19. " S_B_INV ,Invalidate prefetch speculation buffer" "Not invalidated,Invalidated" rbitfld.long 0x00 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,?..." bitfld.long 0x00 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline else bitfld.long 0x00 19. " S_B_INV ,Invalidate prefetch speculation buffer" "Not invalidated,Invalidated" rbitfld.long 0x00 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..." bitfld.long 0x00 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline endif else bitfld.long 0x00 19. " S_B_INV ,Invalidate prefetch speculation buffer" "Not invalidated,Invalidated" rbitfld.long 0x00 17.--18. " B0MW ,Bank 0 memory width" "32 bits,64 bits,128 bits,?..." bitfld.long 0x00 5.--7. " CRC ,Cache replacement control" "LRU per 4 ways,,LRU with 0-1 ways,LRU with 0-2 ways,?..." newline endif bitfld.long 0x00 4. " B0DCE ,Bank 0 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B0ICE ,Bank 0 instruction cache enable" "Disabled,Enabled" bitfld.long 0x00 2. " B0DPE ,Bank 0 data prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " B0IPE ,Bank 0 instruction prefetch enable" "Disabled,Enabled" bitfld.long 0x00 0. " B0SEBE ,Bank 0 single entry buffer enable" "Disabled,Enabled" sif !cpuis("MK?0D*5")&&!cpuis("MK02*")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MKS2?FN???V??12")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12") group.long 0x08++0x03 line.long 0x00 "PFB1CR,Flash Bank 1 Control Register" rbitfld.long 0x00 28.--31. " B1RWSC ,Bank 1 read wait state control" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" sif cpuis("MK2?D*")||cpuis("MK1?D*")||cpuis("MK02*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("KK20DN512ZCAB10R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512V??12*") rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,?..." newline else rbitfld.long 0x00 17.--18. " B1MW ,Bank 1 memory width" "32 bits,64 bits,128 bits,?..." newline endif sif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 4. " B23DCE ,Bank 2-3 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B23ICE ,Bank 2-3 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B23DPE ,Bank 2-3 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B23IPE ,Bank 2-3 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B23SEBE ,Bank 23 single entry buffer enable" "Disabled,Enabled" elif !cpuis("MK?0D*7")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK30DX256VLL7R")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7") bitfld.long 0x00 4. " B1DCE ,Bank 1 data cache enable" "Disabled,Enabled" bitfld.long 0x00 3. " B1ICE ,Bank 1 instruction cache enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " B1DPE ,Bank 1 data prefetch enable" "Disabled,Enabled" bitfld.long 0x00 1. " B1IPE ,Bank 1 instruction prefetch enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " B1SEBE ,Bank 1 single entry buffer enable" "Disabled,Enabled" endif endif endif width 13. tree "Cache Directory Storage Registers" sif cpuis("MK22D*")||cpuis("MK21D*")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*5")||cpuis("MK20D*5") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*10")||cpuis("MK10D*10R")||cpuis("MK10D*7")||cpuis("MK20D*7")||cpuis("MK20D*10*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("KK20DN512ZCAB10R") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW0S_4,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW0S_5,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW0S_6,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW0S_7,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK02*")||cpuis("MK22F*DC10")||cpuis("MKS2?FN???V??12")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK26*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK63*")||cpuis("MK64*")||cpuis("MK24*")||cpuis("MK22FN128VLH10R")||cpuis("MK22F*LQ12")||cpuis("MK22F*MD12") sif !cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVMD12") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R") group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW0S_4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW0S_5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW0S_6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW0S_7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x0+0x100)++0x03 line.long 0x00 "TAGVDW0S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x100)++0x03 line.long 0x00 "TAGVDW0S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW0S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW0S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif sif cpuis("MK22D*")||cpuis("MK21D*")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK21D*LK5")||cpuis("MK21D*MC5") group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*5")||cpuis("MK20D*5") group.long (0x8+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*10")||cpuis("MK10D*10R")||cpuis("MK10D*7")||cpuis("MK20D*7")||cpuis("MK20D*10*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("KK20DN512ZCAB10R") group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW1S_4,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW1S_5,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW1S_6,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW1S_7,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK02*")||cpuis("MK22F*DC12")||cpuis("MKS2?FN???V??12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R") sif !cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK26*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK63*")||cpuis("MK64*")||cpuis("MK24*")||cpuis("MK22FN128VLH10R") group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R") group.long (0x0+0x120)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x120)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x120)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x120)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x10+0x120)++0x03 line.long 0x00 "TAGVDW1S_4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x120)++0x03 line.long 0x00 "TAGVDW1S_5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x120)++0x03 line.long 0x00 "TAGVDW1S_6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x120)++0x03 line.long 0x00 "TAGVDW1S_7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW1S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW1S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW1S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW1S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif sif cpuis("MK22D*")||cpuis("MK21D*")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5") group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*5")||cpuis("MK20D*5") group.long (0x10+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*10")||cpuis("MK10D*10R")||cpuis("MK10D*7")||cpuis("MK20D*7")||cpuis("MK20D*10*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("KK20DN512ZCAB10R") group.long (0x40+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x44+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x48+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x50+0x100)++0x03 line.long 0x00 "TAGVDW2S_4,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x54+0x100)++0x03 line.long 0x00 "TAGVDW2S_5,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x58+0x100)++0x03 line.long 0x00 "TAGVDW2S_6,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x5C+0x100)++0x03 line.long 0x00 "TAGVDW2S_7,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK02*")||cpuis("MK22F*DC10")||cpuis("MKS2?FN???V??12")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||(cpuis("MK22F*LL12"))||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12") group.long (0x40+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x44+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x48+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK26*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK63*")||cpuis("MK64*")||cpuis("MK24*")||cpuis("MK22FN128VLH10R")||cpuis("MK22F*LQ12")||cpuis("MK22F*MD12") sif !cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVMD12") group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R") group.long (0x0+0x140)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x140)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x140)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x140)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x10+0x140)++0x03 line.long 0x00 "TAGVDW2S_4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x140)++0x03 line.long 0x00 "TAGVDW2S_5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x140)++0x03 line.long 0x00 "TAGVDW2S_6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x140)++0x03 line.long 0x00 "TAGVDW2S_7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x20+0x100)++0x03 line.long 0x00 "TAGVDW2S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x24+0x100)++0x03 line.long 0x00 "TAGVDW2S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x28+0x100)++0x03 line.long 0x00 "TAGVDW2S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x2C+0x100)++0x03 line.long 0x00 "TAGVDW2S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif sif cpuis("MK22D*")||cpuis("MK21D*")||cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK21D*MC5")||cpuis("MK21D*LK5") group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 4.--18. 1. " TAG ,15-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*5")||cpuis("MK20D*5") group.long (0x18+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK10D*10")||cpuis("MK10D*10R")||cpuis("MK10D*7")||cpuis("MK20D*7")||cpuis("MK20D*10*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("KK20DN512ZCAB10R") group.long (0x60+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x64+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x68+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x6C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x70+0x100)++0x03 line.long 0x00 "TAGVDW3S_4,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x74+0x100)++0x03 line.long 0x00 "TAGVDW3S_5,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x78+0x100)++0x03 line.long 0x00 "TAGVDW3S_6,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x7C+0x100)++0x03 line.long 0x00 "TAGVDW3S_7,Cache Directory Storage" hexmask.long.word 0x00 6.--18. 1. " TAG ,13-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK02*")||cpuis("MK22F*DC10")||cpuis("MKS2?FN???V??12")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R") sif !cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12") group.long (0x60+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x64+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x68+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x6C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK26*")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--21. 1. " TAG ,16-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" elif cpuis("MK63*")||cpuis("MK64*")||cpuis("MK24*")||cpuis("MK22FN128VLH10R")||cpuis("MK22F*LQ12")||cpuis("MK22F*MD12") sif !cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVMD12") group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif elif cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R") group.long (0x0+0x160)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x4+0x160)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x8+0x160)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0xC+0x160)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x10+0x160)++0x03 line.long 0x00 "TAGVDW3S_4,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x14+0x160)++0x03 line.long 0x00 "TAGVDW3S_5,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x18+0x160)++0x03 line.long 0x00 "TAGVDW3S_6,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x1C+0x160)++0x03 line.long 0x00 "TAGVDW3S_7,Cache Directory Storage" hexmask.long.word 0x00 5.--18. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" else group.long (0x30+0x100)++0x03 line.long 0x00 "TAGVDW3S_0,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x34+0x100)++0x03 line.long 0x00 "TAGVDW3S_1,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x38+0x100)++0x03 line.long 0x00 "TAGVDW3S_2,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" group.long (0x3C+0x100)++0x03 line.long 0x00 "TAGVDW3S_3,Cache Directory Storage" hexmask.long.word 0x00 6.--19. 1. " TAG ,14-bit tag for cache entry" bitfld.long 0x00 0. " VALID ,1-bit valid for cache entry" "Not valid,Valid" endif tree.end tree "Cache Data Storage Registers" sif cpuis("MK11D*")||cpuis("MK12D*")||cpuis("MK22D*")||cpuis("MK21D*")||cpuis("MK21D*LK5")||cpuis("MK21D*MC5") group.long 0x200++0x3F line.long 0x00 "DATAW0S_0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" line.long 0x08 "DATAW0S_1U,Cache Data Storage (Upper Word)" line.long 0x0C "DATAW0S1L,Cache Data Storage (Lower Word)" line.long 0x10 "DATAW1S_0U,Cache Data Storage (Upper Word)" line.long 0x14 "DATAW1S0L,Cache Data Storage (Lower Word)" line.long 0x18 "DATAW1S_1U,Cache Data Storage (Upper Word)" line.long 0x1C "DATAW1S1L,Cache Data Storage (Lower Word)" line.long 0x20 "DATAW2S_0U,Cache Data Storage (Upper Word)" line.long 0x24 "DATAW2S0L,Cache Data Storage (Lower Word)" line.long 0x28 "DATAW2S_1U,Cache Data Storage (Upper Word)" line.long 0x2C "DATAW2S1L,Cache Data Storage (Lower Word)" line.long 0x30 "DATAW3S_0U,Cache Data Storage (Upper Word)" line.long 0x34 "DATAW3S0L,Cache Data Storage (Lower Word)" line.long 0x38 "DATAW3S_1U,Cache Data Storage (Upper Word)" line.long 0x3C "DATAW3S1L,Cache Data Storage (Lower Word)" elif cpuis("MK10D*5")||cpuis("MK20D*5") group.long 0x200++0x1F line.long 0x00 "DATAW0S0,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S1,Cache Data Storage (Lower Word)" group.long 0x208++0x1F line.long 0x00 "DATAW1S0,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S1,Cache Data Storage (Lower Word)" group.long 0x210++0x1F line.long 0x00 "DATAW2S0,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S1,Cache Data Storage (Lower Word)" group.long 0x218++0x1F line.long 0x00 "DATAW3S0,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S1,Cache Data Storage (Lower Word)" elif cpuis("MK02*")||cpuis("MK20DN512ZCAB10R")||cpuis("MK22F*DC12")||cpuis("MK22F*LL12")||cpuis("MK22F*MP12")||cpuis("MK22F*LH12")||cpuis("MK22F*DC10")||cpuis("MK22F*LL10")||cpuis("MK22F*MP10")||cpuis("MK22F*LH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK10D*10")||cpuis("MK10D*10R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DN512ZVLQ10")||cpuis("MK30DN512ZVLQ10R")||cpuis("MK30DX256VLL7R")||cpuis("MK30DX256ZVLQ10")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN128CAH12R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R") sif !cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0VLH10") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW1S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S4L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW1S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S5L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW1S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S6L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW1S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S7L,Cache Data Storage (Lower Word)" group.long 0x280++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x288++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x290++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x298++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x2A0++0x07 line.long 0x00 "DATAW2S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S4L,Cache Data Storage (Lower Word)" group.long 0x2A8++0x07 line.long 0x00 "DATAW2S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S5L,Cache Data Storage (Lower Word)" group.long 0x2B0++0x07 line.long 0x00 "DATAW2S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S6L,Cache Data Storage (Lower Word)" group.long 0x2B8++0x07 line.long 0x00 "DATAW2S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S7L,Cache Data Storage (Lower Word)" group.long 0x2C0++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x2C8++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x2D0++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x2D8++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" group.long 0x2E0++0x07 line.long 0x00 "DATAW3S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S4L,Cache Data Storage (Lower Word)" group.long 0x2E8++0x07 line.long 0x00 "DATAW3S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S5L,Cache Data Storage (Lower Word)" group.long 0x2F0++0x07 line.long 0x00 "DATAW3S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S6L,Cache Data Storage (Lower Word)" group.long 0x2F8++0x07 line.long 0x00 "DATAW3S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S7L,Cache Data Storage (Lower Word)" else group.long 0x200++0xFF line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)" group.long 0x210++0xFF line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)" group.long 0x220++0xFF line.long 0x00 "DATAW0S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S2LM,Cache Data Storage (Lowermost Word)" group.long 0x230++0xFF line.long 0x00 "DATAW0S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S3LM,Cache Data Storage (Lowermost Word)" group.long 0x240++0xFF line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)" group.long 0x250++0xFF line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)" group.long 0x260++0xFF line.long 0x00 "DATAW1S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S2LM,Cache Data Storage (Lowermost Word)" group.long 0x270++0xFF line.long 0x00 "DATAW1S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S3LM,Cache Data Storage (Lowermost Word)" group.long 0x280++0xFF line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)" group.long 0x290++0xFF line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)" group.long 0x2A0++0xFF line.long 0x00 "DATAW2S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S2LM,Cache Data Storage (Lowermost Word)" group.long 0x2B0++0xFF line.long 0x00 "DATAW2S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S3LM,Cache Data Storage (Lowermost Word)" group.long 0x2C0++0xFF line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)" group.long 0x2D0++0xFF line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)" group.long 0x2E0++0xFF line.long 0x00 "DATAW3S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S2LM,Cache Data Storage (Lowermost Word)" group.long 0x2F0++0xFF line.long 0x00 "DATAW3S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S3LM,Cache Data Storage (Lowermost Word)" endif elif cpuis("MK64*")||cpuis("MK63*")||cpuis("MK24*")||cpuis("MK22FN128VLH10R") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" elif cpuis("MKS2?FN???V??12")||cpuis("MK20D????ZVLL10")||cpuis("MK20DN???ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10*")||cpuis("MK10DN512ZVMD10*")||cpuis("MK10DN512ZVMC10*")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10*") group.long 0x200++0x07 line.long 0x00 "DATAW0S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S0L,Cache Data Storage (Lower Word)" group.long 0x208++0x07 line.long 0x00 "DATAW0S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S1L,Cache Data Storage (Lower Word)" group.long 0x210++0x07 line.long 0x00 "DATAW0S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S2L,Cache Data Storage (Lower Word)" group.long 0x218++0x07 line.long 0x00 "DATAW0S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S3L,Cache Data Storage (Lower Word)" group.long 0x220++0x07 line.long 0x00 "DATAW0S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S4L,Cache Data Storage (Lower Word)" group.long 0x228++0x07 line.long 0x00 "DATAW0S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S5L,Cache Data Storage (Lower Word)" group.long 0x230++0x07 line.long 0x00 "DATAW0S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S6L,Cache Data Storage (Lower Word)" group.long 0x238++0x07 line.long 0x00 "DATAW0S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW0S7L,Cache Data Storage (Lower Word)" group.long 0x240++0x07 line.long 0x00 "DATAW1S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S0L,Cache Data Storage (Lower Word)" group.long 0x248++0x07 line.long 0x00 "DATAW1S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S1L,Cache Data Storage (Lower Word)" group.long 0x250++0x07 line.long 0x00 "DATAW1S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S2L,Cache Data Storage (Lower Word)" group.long 0x258++0x07 line.long 0x00 "DATAW1S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S3L,Cache Data Storage (Lower Word)" group.long 0x260++0x07 line.long 0x00 "DATAW1S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S4L,Cache Data Storage (Lower Word)" group.long 0x268++0x07 line.long 0x00 "DATAW1S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S5L,Cache Data Storage (Lower Word)" group.long 0x270++0x07 line.long 0x00 "DATAW1S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S6L,Cache Data Storage (Lower Word)" group.long 0x278++0x07 line.long 0x00 "DATAW1S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW1S7L,Cache Data Storage (Lower Word)" group.long 0x280++0x07 line.long 0x00 "DATAW2S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S0L,Cache Data Storage (Lower Word)" group.long 0x288++0x07 line.long 0x00 "DATAW2S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S1L,Cache Data Storage (Lower Word)" group.long 0x290++0x07 line.long 0x00 "DATAW2S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S2L,Cache Data Storage (Lower Word)" group.long 0x298++0x07 line.long 0x00 "DATAW2S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S3L,Cache Data Storage (Lower Word)" group.long 0x2A0++0x07 line.long 0x00 "DATAW2S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S4L,Cache Data Storage (Lower Word)" group.long 0x2A8++0x07 line.long 0x00 "DATAW2S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S5L,Cache Data Storage (Lower Word)" group.long 0x2B0++0x07 line.long 0x00 "DATAW2S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S6L,Cache Data Storage (Lower Word)" group.long 0x2B8++0x07 line.long 0x00 "DATAW2S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW2S7L,Cache Data Storage (Lower Word)" group.long 0x2C0++0x07 line.long 0x00 "DATAW3S0U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S0L,Cache Data Storage (Lower Word)" group.long 0x2C8++0x07 line.long 0x00 "DATAW3S1U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S1L,Cache Data Storage (Lower Word)" group.long 0x2D0++0x07 line.long 0x00 "DATAW3S2U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S2L,Cache Data Storage (Lower Word)" group.long 0x2D8++0x07 line.long 0x00 "DATAW3S3U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S3L,Cache Data Storage (Lower Word)" group.long 0x2E0++0x07 line.long 0x00 "DATAW3S4U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S4L,Cache Data Storage (Lower Word)" group.long 0x2E8++0x07 line.long 0x00 "DATAW3S5U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S5L,Cache Data Storage (Lower Word)" group.long 0x2F0++0x07 line.long 0x00 "DATAW3S6U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S6L,Cache Data Storage (Lower Word)" group.long 0x2F8++0x07 line.long 0x00 "DATAW3S7U,Cache Data Storage (Upper Word)" line.long 0x04 "DATAW3S7L,Cache Data Storage (Lower Word)" else group.long 0x200++0xFF line.long 0x00 "DATAW0S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S0LM,Cache Data Storage (Lowermost Word)" group.long 0x210++0xFF line.long 0x00 "DATAW0S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S1LM,Cache Data Storage (Lowermost Word)" group.long 0x220++0xFF line.long 0x00 "DATAW0S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S2LM,Cache Data Storage (Lowermost Word)" group.long 0x230++0xFF line.long 0x00 "DATAW0S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW0S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW0S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW0S3LM,Cache Data Storage (Lowermost Word)" group.long 0x240++0xFF line.long 0x00 "DATAW1S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S0LM,Cache Data Storage (Lowermost Word)" group.long 0x250++0xFF line.long 0x00 "DATAW1S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S1LM,Cache Data Storage (Lowermost Word)" group.long 0x260++0xFF line.long 0x00 "DATAW1S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S2LM,Cache Data Storage (Lowermost Word)" group.long 0x270++0xFF line.long 0x00 "DATAW1S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW1S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW1S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW1S3LM,Cache Data Storage (Lowermost Word)" group.long 0x280++0xFF line.long 0x00 "DATAW2S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S0LM,Cache Data Storage (Lowermost Word)" group.long 0x290++0xFF line.long 0x00 "DATAW2S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S1LM,Cache Data Storage (Lowermost Word)" group.long 0x2A0++0xFF line.long 0x00 "DATAW2S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S2LM,Cache Data Storage (Lowermost Word)" group.long 0x2B0++0xFF line.long 0x00 "DATAW2S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW2S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW2S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW2S3LM,Cache Data Storage (Lowermost Word)" group.long 0x2C0++0xFF line.long 0x00 "DATAW3S0UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S0MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S0ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S0LM,Cache Data Storage (Lowermost Word)" group.long 0x2D0++0xFF line.long 0x00 "DATAW3S1UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S1MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S1ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S1LM,Cache Data Storage (Lowermost Word)" group.long 0x2E0++0xFF line.long 0x00 "DATAW3S2UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S2MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S2ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S2LM,Cache Data Storage (Lowermost Word)" group.long 0x2F0++0xFF line.long 0x00 "DATAW3S3UM,Cache Data Storage (Uppermost Word)" line.long 0x04 "DATAW3S3MU,Cache Data Storage (Mid Upper)" line.long 0x08 "DATAW3S3ML,Cache Data Storage (Mid Lower)" line.long 0x0C "DATAW3S3LM,Cache Data Storage (Lowermost Word)" endif tree.end width 0x0B tree.end tree "FTFE (Flash Memory Module)" base ad:0x40020000 width 7. group.byte 0x00++0x01 line.byte 0x00 "FSTAT,Flash Status Register" eventfld.byte 0x00 7. " CCIF ,Command complete interrupt flag" "Not completed,Completed" eventfld.byte 0x00 6. " RDCOLERR ,Flash read collision error flag" "No error,Error" newline eventfld.byte 0x00 5. " ACCERR ,Flash access error flag" "No error,Error" eventfld.byte 0x00 4. " FPVIOL ,Flash protection violation flag" "Not detected,Detected" newline rbitfld.byte 0x00 0. " MGSTAT0 ,Memory controller command completion status flag" "No error,Error" line.byte 0x01 "FCNFG,Flash Configuration Register" bitfld.byte 0x01 7. " CCIE ,Command complete interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " RDCOLLIE ,Read collision error interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x01 5. " ERSAREQ ,Erase all request" "Not erased,Erased" bitfld.byte 0x01 4. " ERSSUSP ,Erase suspend" "Not suspended,Suspended" sif cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK11DN512VLK5R")||cpuis("MK11DN512AVLK5R")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R") sif !cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMC10R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" else newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK21D*AVMC5R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",4 flash blocks" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" elif cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") newline rbitfld.byte 0x01 3. " SWAP ,Indicates which half of program flash space is located at relative address 0x0000" "0/1 blocks,2/3 blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK84FN2M0CAU15R")||cpuis("KK60DN512ZCAB10R") newline rbitfld.byte 0x01 3. " SWAP ,Indicates which half of program flash space is located at relative address 0x0000" "0/1 blocks,2/3 blocks" rbitfld.byte 0x01 2. " PFLSH ,FTFE configuration (number of supported blocks)" ",4 flash blocks" newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not ready,Ready" elif cpuis("MK???X*")||cpuis("MK22FN1M0VMC10")||cpuis("MK53DN512ZCMD10")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DN512ZVMC10*") sif !cpuis("MK02*") sif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "Flash and/or EEPROM,?..." elif cpuis("MK20DN512ZVMC10*")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLQ10R")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK40D*Z*10")||cpuis("MK50DX256ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DX256ZVLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DX256ZCMC10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20D????ZVLL10") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "Flash and/or EEPROM,?..." elif cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." elif !cpuis("MK10D?128V??5")&&!cpuis("MK10D?64V??5")&&!cpuis("MK10D?32V??5")&&!cpuis("MK10*7")&&!cpuis("MK30DX256VLL7R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." else newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" "2 flash and 2 FlexNVM blocks,?..." endif newline rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "FlexRAM not available,FlexRAM available" sif !cpuis("MK20DX256VLK10R") newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif endif elif cpuis("MK???N*")||cpuis("KK26FN2M0CAC18R") sif !cpuis("MK02*")&&!cpuis("MK22FN256*")&&!cpuis("MK22FN128*")&&!cpuis("MK8?FN256V*")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK22FN512VDC12R")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R") sif (cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK40D*Z*10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VMC10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,1 block at 0x0000" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70FN1M0VMJ12R")||cpuis("MK70FN1M0VMJ15R")||cpuis("KK26FN2M0CAC18R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0/1 block at 0x0000,2/3 block at 0x0000" elif !cpuis("MK10D?128V??5")&&!cpuis("MK10D?64V??5")&&!cpuis("MK10D?32V??5")&&!cpuis("MK10DN512ZVLK10")&&!cpuis("MK10DN512ZVLK10R")&&!cpuis("MK10DN512ZVLL10")&&!cpuis("MK10DN512ZVLL10R")&&!cpuis("MK10DN512ZVMC10")&&!cpuis("MK11DN512VLK5R")&&!cpuis("MK11DN512AVLK5R")&&!cpuis("MK10*7")&&!cpuis("MK70FN1M0VMJ12R")&&!cpuis("MK70FN1M0VMJ15R") newline rbitfld.byte 0x01 3. " SWAP ,Swap" "0 block at 0x0000,?..." endif sif cpuis("MK21D*AVLK5")||cpuis("MK21D*AVMC5")||cpuis("MK20DX256VLK10R")||cpuis("MK60DN512ZCAB10R") newline bitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",Program flash only" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" elif cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R") newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",2 flash blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" else newline rbitfld.byte 0x01 2. " PFLSH ,Flash configuration" ",4 flash blocks" rbitfld.byte 0x01 1. " RAMRDY ,RAM ready" "Not available,Available" endif sif (cpuis("MK10F????VLQ12")||cpuis("MK10F????VMD12"))||(cpuis("MK10D?128V??5")||cpuis("MK10D?64V??5")||cpuis("MK10D?32V??5"))||cpuis("MK10DN512VLQ10")||cpuis("MK10DN512VMD10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R") newline rbitfld.byte 0x01 0. " EEERDY ,EEPROM ready" "Not available,Available" endif endif endif rgroup.byte 0x02++0x01 line.byte 0x00 "FSEC,Flash Security Register" bitfld.byte 0x00 6.--7. " KEYEN ,Backdoor key security enable" "Disabled,Disabled,Enabled,Disabled" bitfld.byte 0x00 4.--5. " MEEN ,Mass erase enable bits" "Enabled,Enabled,Disabled,Enabled" newline bitfld.byte 0x00 2.--3. " FSLACC ,Freescale failure analysis access code" "Granted,Denied,Denied,Granted" bitfld.byte 0x00 0.--1. " SEC ,Flash security" "Secure,Secure,Unsecure,Secure" line.byte 0x01 "FOPT,Flash Option Register" sif cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.byte 0x01 6.--7. " BOOTSRC_SEL ,Boot source selection" "Internal flash,,ROM/QSPI0,ROM/boot loader mode" newline endif sif cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") bitfld.byte 0x01 5. " FAST_INIT ,Select initialization speed on POR\VLLSx and any system reset" "Slower initialization,Fast initialization" newline endif sif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK70*")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK63FN1M0VLQ12")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18")||cpuis("MK66FN2M0VLQ18") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK70*")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10*")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10*")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") bitfld.byte 0x01 2. " NMI_DIS ,Enable/disable control for the NMI function" "Disabled,Enabled" newline endif sif !cpuis("MKS20FN128VFT12")&&!cpuis("MKS20FN128VLH12")&&!cpuis("MKS20FN128VLL12")&&!cpuis("MKS20FN256VFT12")&&!cpuis("MKS20FN256VLH12")&&!cpuis("MKS20FN256VLL12")&&!cpuis("MKS22FN128VFT12")&&!cpuis("MKS22FN128VLH12")&&!cpuis("MKS22FN128VLL12")&&!cpuis("MKS22FN256VFT12")&&!cpuis("MKS22FN256VLH12")&&!cpuis("MKS22FN256VLL12") bitfld.byte 0x01 1. " EZPORT_DIS ,Enable/disable EzPort function" "Disabled,Enabled" newline endif bitfld.byte 0x01 0. " LPBOOT ,Control the reset value of OUTDIVx values in SIM_CLKDIV1 register" "Low-power boot,Normal boot" endif width 9. newline sif cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK21FX512VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN128CAH12R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") if (((per.b(ad:0x40020000))&0x80)==0x0)||(((per.b(ad:0x40020000+0x01))&0x10)==0x10) rgroup.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" rgroup.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" rgroup.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" rgroup.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" rgroup.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" rgroup.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" rgroup.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" rgroup.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" rgroup.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" rgroup.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" rgroup.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" rgroup.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" rgroup.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" newline else group.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" group.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" group.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" group.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" group.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" group.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" group.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" group.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" group.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" group.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" group.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" group.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" group.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [24] ,Program flash region protect" "Protected,Not protected" newline endif else if (((per.b(ad:0x40020000))&0x80)==0x0)||(((per.b(ad:0x40020000+0x01))&0x10)==0x10) rgroup.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" rgroup.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" rgroup.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" rgroup.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" rgroup.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" rgroup.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" rgroup.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" rgroup.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" rgroup.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" rgroup.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" rgroup.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" rgroup.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" rgroup.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [24] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [0] ,Program flash region protect" "Protected,Not protected" newline else group.byte (0x04+0x0)++0x00 line.byte 0x00 "FCCOB3,Flash Common Command Object Register" group.byte (0x04+0x1)++0x00 line.byte 0x00 "FCCOB2,Flash Common Command Object Register" group.byte (0x04+0x2)++0x00 line.byte 0x00 "FCCOB1,Flash Common Command Object Register" group.byte (0x04+0x3)++0x00 line.byte 0x00 "FCCOB0,Flash Common Command Object Register" group.byte (0x04+0x4)++0x00 line.byte 0x00 "FCCOB7,Flash Common Command Object Register" group.byte (0x04+0x5)++0x00 line.byte 0x00 "FCCOB6,Flash Common Command Object Register" group.byte (0x04+0x6)++0x00 line.byte 0x00 "FCCOB5,Flash Common Command Object Register" group.byte (0x04+0x7)++0x00 line.byte 0x00 "FCCOB4,Flash Common Command Object Register" group.byte (0x04+0x8)++0x00 line.byte 0x00 "FCCOBB,Flash Common Command Object Register" group.byte (0x04+0x9)++0x00 line.byte 0x00 "FCCOBA,Flash Common Command Object Register" group.byte (0x04+0xA)++0x00 line.byte 0x00 "FCCOB9,Flash Common Command Object Register" group.byte (0x04+0xB)++0x00 line.byte 0x00 "FCCOB8,Flash Common Command Object Register" group.byte 0x10++0x03 line.byte 0x00 "FPROT_3,Program Flash Protection Register 3" bitfld.byte 0x00 7. " PROT_[31] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [30] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [29] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [28] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [27] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [26] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [25] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [24] ,Program flash region protect" "Protected,Not protected" line.byte 0x01 "FPROT_2,Program Flash Protection Register 2" bitfld.byte 0x01 7. " [23] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [22] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [21] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [20] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [19] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [18] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [17] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [16] ,Program flash region protect" "Protected,Not protected" line.byte 0x02 "FPROT_1,Program Flash Protection Register 1" bitfld.byte 0x02 7. " [15] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 6. " [14] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 5. " [13] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 4. " [12] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x02 3. " [11] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 2. " [10] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 1. " [9] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x02 0. " [8] ,Program flash region protect" "Protected,Not protected" line.byte 0x03 "FPROT_0,Program Flash Protection Register 0" bitfld.byte 0x03 7. " [7] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 6. " [6] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 5. " [5] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 4. " [4] ,Program flash region protect" "Protected,Not protected" newline bitfld.byte 0x03 3. " [3] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 2. " [2] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 1. " [1] ,Program flash region protect" "Protected,Not protected" bitfld.byte 0x03 0. " [0] ,Program flash region protect" "Protected,Not protected" newline endif endif sif !cpuis("MK8?FN256V*")&&!cpuis("MK02*")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK40D*ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MKS20FN128V??12")&&!cpuis("MKS22FN128V??12")&&!cpuis("MKS20FN256V??12")&&!cpuis("MKS22FN256V??12")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK10DN512ZV??10*")&&!cpuis("MK10DX256ZV??10*")&&!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")&&!cpuis("MK20DN512VLK10")&&!cpuis("MK22FN128VLH10")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN256VLL12")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0x40020000))&0x80)==0x0)||(((per.l(ad:0x40020000+0x01))&0x10)==0x10) sif cpuis("MK???X*") rgroup.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT_[7] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region protect" "Protected,Not protected" else hgroup.byte 0x16++0x0 hide.byte 0x00 "FEPROT,EEPROM Protection Register" rgroup.byte 0x17++0x00 line.byte 0x00 "FDPROT,Data Flash Protection Register" bitfld.byte 0x00 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Data flash region protect" "Protected,Not protected" endif else sif cpuis("MK???X*") group.byte 0x16++0x01 line.byte 0x00 "FEPROT,EEPROM Protection Register" bitfld.byte 0x00 7. " EPROT_[7] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,EEPROM region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,EEPROM region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,EEPROM region protect" "Protected,Not protected" line.byte 0x01 "FDPROT,Data Flash Protection Register" bitfld.byte 0x01 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x01 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x01 0. " [0] ,Data flash region protect" "Protected,Not protected" else hgroup.byte 0x16++0x0 hide.byte 0x00 "FEPROT,EEPROM Protection Register" group.byte 0x17++0x00 line.byte 0x00 "FDPROT,Data Flash Protection Register" bitfld.byte 0x00 7. " DPROT_[7] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 6. " [6] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 5. " [5] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 4. " [4] ,Data flash region protect" "Protected,Not protected" newline bitfld.byte 0x00 3. " [3] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 2. " [2] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 1. " [1] ,Data flash region protect" "Protected,Not protected" bitfld.byte 0x00 0. " [0] ,Data flash region protect" "Protected,Not protected" endif endif newline endif sif cpuis("MK02*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MKS20FN128V??12")||cpuis("MKS22FN128V??12")||cpuis("MKS20FN256V??12")||cpuis("MKS22FN256V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") sif !cpuis("MK22FN128CAH12R") rgroup.byte 0x18++0x03 line.byte 0x00 "XACCH3,Execute-only Access Register 3" bitfld.byte 0x00 7. " XA_[39] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 6. " [38] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 5. " [37] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 4. " [36] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x00 3. " [35] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 2. " [34] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 1. " [33] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 0. " [32] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x01 "XACCH2,Execute-only Access Register 2" bitfld.byte 0x01 7. " [47] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 6. " [46] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 5. " [45] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 4. " [44] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x01 3. " [43] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 2. " [42] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 1. " [41] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 0. " [40] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x02 "XACCH1,Execute-only Access Register 1" bitfld.byte 0x02 7. " [55] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 6. " [54] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 5. " [53] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 4. " [52] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x02 3. " [51] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 2. " [50] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 1. " [49] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 0. " [48] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x03 "XACCH0,Execute-only Access Register 0" bitfld.byte 0x03 7. " [63] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 6. " [62] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 5. " [61] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 4. " [60] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x03 3. " [59] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 2. " [58] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 1. " [57] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 0. " [56] ,Execute-only access control" "Execute-only,Execute/Data" endif rgroup.byte 0x1C++0x03 line.byte 0x00 "XACCL3,Execute-only Access Register 3" sif cpuis("MK22FN128CAH12R") bitfld.byte 0x00 7. " XA_[7] ,Execute-only access control" "Execute-only,Execute/Data" else bitfld.byte 0x00 7. " [7] ,Execute-only access control" "Execute-only,Execute/Data" endif bitfld.byte 0x00 6. " [6] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 5. " [5] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 4. " [4] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x00 3. " [3] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 2. " [2] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 1. " [1] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x00 0. " [0] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x01 "XACCL2,Execute-only Access Register 2" bitfld.byte 0x01 7. " [15] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 6. " [14] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 5. " [13] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 4. " [12] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x01 3. " [11] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 2. " [10] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 1. " [9] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x01 0. " [8] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x02 "XACCL1,Execute-only Access Register 1" bitfld.byte 0x02 7. " [23] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 6. " [22] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 5. " [21] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 4. " [20] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x02 3. " [19] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 2. " [18] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 1. " [17] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x02 0. " [16] ,Execute-only access control" "Execute-only,Execute/Data" line.byte 0x03 "XACCL0,Execute-only Access Register 0" bitfld.byte 0x03 7. " [31] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 6. " [30] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 5. " [29] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 4. " [28] ,Execute-only access control" "Execute-only,Execute/Data" newline bitfld.byte 0x03 3. " [27] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 2. " [26] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 1. " [25] ,Execute-only access control" "Execute-only,Execute/Data" bitfld.byte 0x03 0. " [24] ,Execute-only access control" "Execute-only,Execute/Data" newline sif !cpuis("MK22FN128CAH12R") rgroup.byte 0x20++0x03 line.byte 0x00 "SACCH3,Supervisor-only Access Register 3" bitfld.byte 0x00 7. " SA_[39] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 6. " [38] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 5. " [37] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 4. " [36] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x00 3. " [35] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 2. " [34] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 1. " [33] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 0. " [32] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x01 "SACCH2,Supervisor-only Access Register 2" bitfld.byte 0x01 7. " [47] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 6. " [46] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 5. " [45] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 4. " [44] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x01 3. " [43] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 2. " [42] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 1. " [41] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 0. " [40] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x02 "SACCH1,Supervisor-only Access Register 1" bitfld.byte 0x02 7. " [55] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 6. " [54] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 5. " [53] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 4. " [52] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x02 3. " [51] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 2. " [50] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 1. " [49] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 0. " [48] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x03 "SACCH0,Supervisor-only Access Register 0" bitfld.byte 0x03 7. " [63] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 6. " [62] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 5. " [61] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 4. " [60] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x03 3. " [59] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 2. " [58] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 1. " [57] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 0. " [56] ,Supervisor-only access control" "Supervisor,User/Supervisor" endif rgroup.byte 0x24++0x03 line.byte 0x00 "SACCL3,Supervisor-only Access Register 3" sif cpuis("MK22FN128CAH12R") bitfld.byte 0x00 7. " SA_[7] ,Supervisor-only access control" "Supervisor,User/Supervisor" else bitfld.byte 0x00 7. " [7] ,Supervisor-only access control" "Supervisor,User/Supervisor" endif bitfld.byte 0x00 6. " [6] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 5. " [5] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 4. " [4] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x00 3. " [3] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 2. " [2] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 1. " [1] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x00 0. " [0] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x01 "SACCL2,Supervisor-only Access Register 2" bitfld.byte 0x01 7. " [15] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 6. " [14] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 5. " [13] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 4. " [12] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x01 3. " [11] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 2. " [10] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 1. " [9] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x01 0. " [8] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x02 "SACCL1,Supervisor-only Access Register 1" bitfld.byte 0x02 7. " [23] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 6. " [22] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 5. " [21] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 4. " [20] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x02 3. " [19] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 2. " [18] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 1. " [17] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x02 0. " [16] ,Supervisor-only access control" "Supervisor,User/Supervisor" line.byte 0x03 "SACCL0,Supervisor-only Access Register 0" bitfld.byte 0x03 7. " [31] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 6. " [30] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 5. " [29] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 4. " [28] ,Supervisor-only access control" "Supervisor,User/Supervisor" newline bitfld.byte 0x03 3. " [27] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 2. " [26] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 1. " [25] ,Supervisor-only access control" "Supervisor,User/Supervisor" bitfld.byte 0x03 0. " [24] ,Supervisor-only access control" "Supervisor,User/Supervisor" rgroup.byte 0x28++0x00 line.byte 0x00 "FACSS,Flash Access Segment Size Register" rgroup.byte 0x2B++0x00 line.byte 0x00 "FACSN,Flash Access Segment Number Register" endif width 0x0B tree.end tree "NFC (NAND Flash Controller)" base ad:0x400A8000 width 12. group.long 0x00++0x17 line.long 0x00 "CMD1,Flash Command 1 Register" hexmask.long.byte 0x00 24.--31. 1. " BYTE2 ,Second command byte" hexmask.long.byte 0x00 16.--23. 1. " BYTE3 ,Third command byte" line.long 0x04 "CMD2,Flash Command 2 Register" hexmask.long.byte 0x04 24.--31. 1. " BYTE1 ,First command byte" hexmask.long.word 0x04 8.--23. 1. " CODE ,User-defined flash operation sequencer" bitfld.long 0x04 1.--2. " BUFNO ,Internal buffer number" "0,1,2,3" bitfld.long 0x04 0. " BUSY_START ,Busy indicator and start command" "Idle,Busy" line.long 0x08 "CAR,Column Address Register" hexmask.long.byte 0x08 8.--15. 0x01 " BYTE2 ,Second byte of column address" hexmask.long.byte 0x08 0.--7. 0x01 " BYTE1 ,First byte of column address" line.long 0x0C "RAR,Row Address Register" sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x0C 29. " RB1 ,Ready/busy 1 enable" "Disabled,Enabled" bitfld.long 0x0C 28. " RB0 ,Ready/busy 0 enable" "Disabled,Enabled" bitfld.long 0x0C 25. " CS1 ,Chip select 1 enable" "Disabled,Enabled" bitfld.long 0x0C 24. " CS0 ,Chip select 0 enable" "Disabled,Enabled" else bitfld.long 0x0C 29. " CS1 ,Chip select 1 enable" "Disabled,Enabled" bitfld.long 0x0C 28. " CS0 ,Chip select 0 enable" "Disabled,Enabled" bitfld.long 0x0C 25. " RB1 ,Ready/busy 1 enable" "Disabled,Enabled" bitfld.long 0x0C 24. " RB0 ,Ready/busy 0 enable" "Disabled,Enabled" endif newline hexmask.long.byte 0x0C 16.--23. 0x01 " BYTE3 ,Third byte of row address" hexmask.long.byte 0x0C 8.--15. 0x01 " BYTE2 ,Second byte of row address" hexmask.long.byte 0x0C 0.--7. 0x01 " BYTE1 ,First byte of row address" line.long 0x10 "RPT,Flash Command Repeat Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,16-bit repeat count" line.long 0x14 "RAI,Row Address Increment Register" hexmask.long.byte 0x14 16.--23. 0x01 " INC3 ,Increment for the third byte of row address" hexmask.long.byte 0x14 8.--15. 0x01 " INC2 ,Increment for the second byte of row address" hexmask.long.byte 0x14 0.--7. 0x01 " INC1 ,Increment for the first byte of row address" rgroup.long 0x18++0x07 line.long 0x00 "SR1,Flash Status 1 Register" hexmask.long.byte 0x00 24.--31. 1. " ID1 ,First byte returned by read ID command" hexmask.long.byte 0x00 16.--23. 1. " ID2 ,Second byte returned by read ID command" hexmask.long.byte 0x00 8.--15. 1. " ID3 ,Third byte returned by read ID command" hexmask.long.byte 0x00 0.--7. 1. " ID4 ,Fourth byte returned by read ID command" line.long 0x04 "SR2,Flash Status 2 Register" hexmask.long.byte 0x04 24.--31. 1. " ID5 ,Fifth byte returned by read ID command" hexmask.long.byte 0x04 0.--7. 1. " STATUS1 ,Byte returned by read status command" group.long 0x20++0x1B line.long 0x00 "DMA1,DMA Channel 1 Address Register" line.long 0x04 "DMACFG,DMA Configuration Register" hexmask.long.word 0x04 20.--31. 1. " COUNT1 ,Number of bytes to be transferred by DMA channel 1" hexmask.long.byte 0x04 13.--19. 1. " COUNT2 ,Number of bytes to be transferred by DMA channel 2" bitfld.long 0x04 9.--12. " OFFSET2 ,256-byte offset for DMA channel 2" "0x00,0x100,0x200,0x300,0x400,0x500,0x600,0x700,0x800,0x900,0xA00,0xB00,0xC00,0xD00,0xE00,0xF00" bitfld.long 0x04 1. " ACT1 ,DMA channel 1 status" "Not active,Active" newline bitfld.long 0x04 0. " ACT2 ,DMA channel 2 status" "Not active,Active" line.long 0x08 "SWAP,Cache Swap Register" hexmask.long.word 0x08 17.--27. 0x02 " ADDR1 ,Lower swap address" hexmask.long.word 0x08 1.--11. 0x02 " ADDR2 ,Upper swap address" line.long 0x0C "SECSZ,Sector Size Register" hexmask.long.word 0x0C 0.--12. 1. " SIZE ,Size of transfer unit" line.long 0x10 "CFG,Flash Configuration Register" bitfld.long 0x10 31. " STOPWERR ,Stop on write error" "Not stopped,Stopped" hexmask.long.word 0x10 22.--30. 0x40 " ECCAD ,Byte address in SRAM" bitfld.long 0x10 21. " ECCSRAM ,Write ECC status to SRAM" "Not written,Written" bitfld.long 0x10 20. " DMAREQ ,Transfer sector after ECC done" "Not transferred,Transferred" newline bitfld.long 0x10 17.--19. " ECCMODE ,ECC mode" "ECC bypass,4-error correction,6-error correction,8-error correction,12-error correction,16-error correction,24-error correction,32-error correction" bitfld.long 0x10 16. " FAST ,Fast flash configuration for EDO" "Slow,Fast" bitfld.long 0x10 13.--15. " IDCNT ,Number of bytes that are read for the read id command" "0,1,2,3,4,5,6,7" bitfld.long 0x10 8.--12. " TIMEOUT ,Number of flash_clk cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x10 7. " BITWIDTH ,Bit width" "8-bit,16-bit" newline sif !cpuis("MK70*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("KK60FN1M0VLQ15") bitfld.long 0x10 6. " BTMD ,Boot mode" "Normal,Boot" newline endif bitfld.long 0x10 5. " AIAD ,Auto-increment flash row address" "Disabled,Enabled" bitfld.long 0x10 4. " AIBN ,Auto-increment buffer number" "Disabled,Enabled" bitfld.long 0x10 0.--3. " PAGECNT ,Number of virtual pages to be programmed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "DMA2,DMA Channel 2 Address Register" line.long 0x18 "ISR,Interrupt Status Register" sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") rbitfld.long 0x18 31. " WERR ,Write error interrupt" "No interrupt,Interrupt" rbitfld.long 0x18 30. " DONE ,Done interrupt" "No interrupt,Interrupt" rbitfld.long 0x18 29. " IDLE ,Command idle interrupt" "No interrupt,Interrupt" rbitfld.long 0x18 27. " WERRNS ,Write error status" "Not detected,Detected" newline rbitfld.long 0x18 26. " CMDBUSY ,Command busy" "Not busy,Busy" rbitfld.long 0x18 25. " RESBUSY ,Residue engine busy" "Not busy,Busy" rbitfld.long 0x18 24. " ECCBUSY ,ECC engine busy" "Not busy,Busy" rbitfld.long 0x18 23. " DMABUSY ,DMA engine busy" "Not busy,Busy" else bitfld.long 0x18 31. " WERR ,Write error interrupt" "No interrupt,Interrupt" bitfld.long 0x18 30. " DONE ,Done interrupt" "No interrupt,Interrupt" bitfld.long 0x18 29. " IDLE ,Command idle interrupt" "No interrupt,Interrupt" bitfld.long 0x18 27. " WERRNS ,Write error status" "Not detected,Detected" newline bitfld.long 0x18 26. " CMDBUSY ,Command busy" "Not busy,Busy" bitfld.long 0x18 25. " RESBUSY ,Residue engine busy" "Not busy,Busy" bitfld.long 0x18 24. " ECCBUSY ,ECC engine busy" "Not busy,Busy" bitfld.long 0x18 23. " DMABUSY ,DMA engine busy" "Not busy,Busy" endif newline bitfld.long 0x18 22. " WERREN ,Enable bit for ISR[WERR]" "Disabled,Enabled" bitfld.long 0x18 21. " DONEEN ,Enable bit for ISR[DONE]" "Disabled,Enabled" bitfld.long 0x18 20. " IDLEEN ,Enable bit for ISR[IDLE]" "Disabled,Enabled" eventfld.long 0x18 19. " WERRCLR ,Clear bit for ISR[WERR]" "Not cleared,Cleared" newline eventfld.long 0x18 18. " DONECLR ,Clear bit for ISR[DONE]" "Not cleared,Cleared" eventfld.long 0x18 17. " IDLECLR ,Clear bit for ISR[IDLE]" "Not cleared,Cleared" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*")||cpuis("KK60FN1M0VLQ15") rbitfld.long 0x18 4.--5. " RESBN ,Residue buffer number" "0,1,2,3" rbitfld.long 0x18 2.--3. " ECCBN ,ECC buffer number" "0,1,2,3" rbitfld.long 0x18 0.--1. " DMABN ,DMA buffer number" "0,1,2,3" else bitfld.long 0x18 4.--5. " RESBN ,Residue buffer number" "0,1,2,3" bitfld.long 0x18 2.--3. " ECCBN ,ECC buffer number" "0,1,2,3" bitfld.long 0x18 0.--1. " DMABN ,DMA buffer number" "0,1,2,3" endif width 0x0B tree.end sif cpuis("?????X*")||cpuis("MK70FN1M0VMJ15")||cpuis("MK70FN1M0VMJ12") tree "FLEXBUS (External Bus Interface)" base ad:0x4000c000 width 8. tree "Chip Select 0" group.long 0x0++0x07 line.long 0x00 "CSAR0,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR0,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0x0+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0x0+0x08)&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0x0+0x08)&0x100)==0x00) group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x0+0x08)++0x03 line.long 0x00 "CSCR0,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 1" group.long 0xC++0x07 line.long 0x00 "CSAR1,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR1,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0xC+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0xC+0x08)&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0xC+0x08)&0x100)==0x00) group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0xC+0x08)++0x03 line.long 0x00 "CSCR1,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 2" group.long 0x18++0x07 line.long 0x00 "CSAR2,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR2,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0x18+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0x18+0x08)&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0x18+0x08)&0x100)==0x00) group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x18+0x08)++0x03 line.long 0x00 "CSCR2,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 3" group.long 0x24++0x07 line.long 0x00 "CSAR3,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR3,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0x24+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0x24+0x08)&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0x24+0x08)&0x100)==0x00) group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x24+0x08)++0x03 line.long 0x00 "CSCR3,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 4" group.long 0x30++0x07 line.long 0x00 "CSAR4,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR4,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0x30+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0x30+0x08)&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0x30+0x08)&0x100)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x30+0x08)++0x03 line.long 0x00 "CSCR4,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end tree "Chip Select 5" group.long 0x3C++0x07 line.long 0x00 "CSAR5,Chip Select Address Register" hexmask.long.word 0x00 16.--31. 0x01 " BA ,Base address" line.long 0x04 "CSMR5,Chip Select Mask Register" bitfld.long 0x04 31. " BAM_[15] ,Base address bit 15 mask" "Not masked,Masked" bitfld.long 0x04 30. " [14] ,Base address bit 14 mask" "Not masked,Masked" bitfld.long 0x04 29. " [13] ,Base address bit 13 mask" "Not masked,Masked" bitfld.long 0x04 28. " [12] ,Base address bit 12 mask" "Not masked,Masked" newline bitfld.long 0x04 27. " [11] ,Base address bit 11 mask" "Not masked,Masked" bitfld.long 0x04 26. " [10] ,Base address bit 10 mask" "Not masked,Masked" bitfld.long 0x04 25. " [9] ,Base address bit 9 mask" "Not masked,Masked" bitfld.long 0x04 24. " [8] ,Base address bit 8 mask" "Not masked,Masked" newline bitfld.long 0x04 23. " [7] ,Base address bit 7 mask" "Not masked,Masked" bitfld.long 0x04 22. " [6] ,Base address bit 6 mask" "Not masked,Masked" bitfld.long 0x04 21. " [5] ,Base address bit 5 mask" "Not masked,Masked" bitfld.long 0x04 20. " [4] ,Base address bit 4 mask" "Not masked,Masked" newline bitfld.long 0x04 19. " [3] ,Base address bit 3 mask" "Not masked,Masked" bitfld.long 0x04 18. " [2] ,Base address bit 2 mask" "Not masked,Masked" bitfld.long 0x04 17. " [1] ,Base address bit 1 mask" "Not masked,Masked" bitfld.long 0x04 16. " [0] ,Base address bit 0 mask" "Not masked,Masked" newline bitfld.long 0x04 8. " WP ,Write protect" "Allowed,Not allowed" bitfld.long 0x04 0. " V ,Valid bit" "Invalid,Valid" if ((per.l(ad:0x4000c000+0x3C+0x08)&0x800000)==0x800000) if ((per.l(ad:0x4000c000+0x3C+0x08)&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" bitfld.long 0x00 26.--31. " SWS ,Secondary wait state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif else if ((per.l(ad:0x4000c000+0x3C+0x08)&0x100)==0x00) group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" else group.long (0x3C+0x08)++0x03 line.long 0x00 "CSCR5,Chip Select Control Register" newline bitfld.long 0x00 23. " SWSEN ,Secondary wait state enable" "Disabled,Enabled" bitfld.long 0x00 22. " EXTS ,Extended transfer start/extended address latch enable" "Disabled,Enabled" bitfld.long 0x00 20.--21. " ASET ,Address setup" "1st rising edge,2nd rising edge,3rd rising edge,4th rising edge" newline sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ12")||cpuis("MK70FN1M0VMJ15")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" newline else bitfld.long 0x00 18.--19. " RDAH ,Read address hold or deselect" "0 cycles,1 cycle,2 cycles,3 cycles" newline endif bitfld.long 0x00 16.--17. " WRAH ,Write address hold or deselect" "1 cycle,2 cycles,3 cycles,4 cycles" bitfld.long 0x00 10.--15. " WS ,Wait states" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 9. " BLS ,Byte-lane shift" "Not shifted,Shifted" bitfld.long 0x00 8. " AA ,Auto-acknowledge enable" "Disabled,Enabled" newline bitfld.long 0x00 6.--7. " PS ,Port size" "32 bit,8 bit,16 bit,16 bit" bitfld.long 0x00 5. " BEM ,Byte-enable mode" "Write only,Read/write" bitfld.long 0x00 4. " BSTR ,Burst-read enable" "Disabled,Enabled" bitfld.long 0x00 3. " BSTW ,Burst-write enable" "Disabled,Enabled" endif endif tree.end newline sif cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLL10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if ((per.l(ad:0x4000c000+0x44)&0x100)==0x0) group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,?..." else group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,/FB_CS3,/FB_BE_7_0,?..." endif else group.long 0x60++0x03 line.long 0x00 "CSPMCR,Chip Select Port Multiplexing Control Register" bitfld.long 0x00 28.--31. " GROUP_1 ,FlexBus signal group 1 multiplex control" "FB_ALE,/FB_CS1,/FB_TS,?..." bitfld.long 0x00 24.--27. " GROUP_2 ,FlexBus signal group 2 multiplex control" "/FB_CS4,FB_TSIZ0,/FB_BE_31_24,?..." bitfld.long 0x00 20.--23. " GROUP_3 ,FlexBus signal group 3 multiplex control" "/FB_CS5,FB_TSIZ1,/FB_BE_23_16,?..." bitfld.long 0x00 16.--19. " GROUP_4 ,FlexBus signal group 4 multiplex control" "/FB_TBST,/FB_CS2,/FB_BE_15_8,?..." newline bitfld.long 0x00 12.--15. " GROUP_5 ,FlexBus signal group 5 multiplex control" "/FB_TA,/FB_CS3,/FB_BE_7_0,?..." endif width 0x0B tree.end endif tree "DDRMC (DDR1/2/LP SDRAM Memory Controller)" base ad:0x400AE000 width 10. group.long 0x00++0x3 line.long 0x00 "DDR_CR00,DDR Control 0 Register" hexmask.long.word 0x00 16.--31. 1. " VERSION ,Version of memory controller" bitfld.long 0x00 8.--11. " DDRCLS ,DRAM Class" "DDR,LPDDR,,,DDR2,?..." bitfld.long 0x00 0. " START ,Start processing in the memory controller" "Not started,Started" rgroup.long 0x04++0x3 line.long 0x00 "DDR_CR01,DDR Control 1 Register" bitfld.long 0x00 16.--17. " CSMAX ,Chip Select Maximum" "0,1,2,?..." bitfld.long 0x00 8.--11. " MAXCOL ,Maximum Column" "0,1,2,3,4,5,6,7,8,9,10,11,?..." bitfld.long 0x00 0.--4. " MAXROW ,Maximum Row" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x08++0x2f line.long 0x00 "DDR_CR02,DDR Control 2 Register" bitfld.long 0x00 24.--27. " INITAREF ,Number of auto-refresh commands to execute during DRAM initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--23. 1. " TINIT ,Define the DRAM initialization time in cycles" line.long 0x04 "DDR_CR03,DDR Control 3 Register" bitfld.long 0x04 24.--28. " TCCD ,DRAM CAS-to-CAS parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16.--19. " WRLAT ,DRAM write latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " LATGATE ,Latency Gate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " LATLIN ,CAS latency linear value" ",,1 cycle,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles" line.long 0x08 "DDR_CR04,DDR Control 4 Register" hexmask.long.byte 0x08 24.--31. 1. " TRASMIN ,Time RAS Minimum" bitfld.long 0x08 16.--21. " TRC ,DRAM period between active commands for the same bank" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x08 8.--10. " TRRD ,DRAM activate-to-activate delay for different banks" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " TBINT ,Time Burst Interrupt Interval" "0,1,2,3,4,5,6,7" line.long 0x0c "DDR_CR05,DDR Control 5 Register" bitfld.long 0x0C 24.--28. " TMRD ,TMRD parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 16.--18. " TRTP ,Time Read-To-Precharge(cycles)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 8.--11. " TRP ,DRAM precharge command time(cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 0.--3. " TWTR ,Time Write-To-Read(cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "DDR_CR06,DDR Control 6 Register" bitfld.long 0x10 24. " INTWBR ,Interrupt Write Burst" "No interrupt,Interrupt" hexmask.long.word 0x10 8.--23. 1. " TRASMAX ,Time Row Access Maximum" hexmask.long.byte 0x10 0.--7. 1. " TMOD ,Time Mode" line.long 0x14 "DDR_CR07,DDR Control 7 Register" bitfld.long 0x14 24. " CCAPEN ,Concurrent Auto-Precharge Enable" "Disabled,Enabled" bitfld.long 0x14 16. " AP ,Auto Precharge Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 8.--12. " TCKESR ,Minimum CLK low pulse width during self-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 0.--2. " CLKPW ,Minimum CLK pulse width in cycles" "0,1,2,3,4,5,6,7" line.long 0x18 "DDR_CR08,DDR Control 8 Register" bitfld.long 0x18 24.--28. " TDAL ,Auto-precharge write recovery time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--20. " TWR ,Time Write Recovery" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x18 8.--15. 1. " TRASDI ,Time RAS-to-CAS Delay Interval" bitfld.long 0x18 0. " TRAS ,Lockout support by memory device indication" "Not supported,Supported" line.long 0x1c "DDR_CR09,DDR Control 9 Register" bitfld.long 0x1C 24.--26. " BSTLEN ,Burst Length" "0,1,2,3,4,5,6,7" bitfld.long 0x1C 16. " NOCMD ,Disable DRAM commands" "No,Yes" hexmask.long.word 0x1C 0.--15. 1. " TDLL ,DLL lock time in cycles" line.long 0x20 "DDR_CR10,DDR Control 10 Register" bitfld.long 0x20 24.--27. " TRPAB ,DRAM TRP All Bank parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x20 8.--23. 1. " TCPD ,Define DRAM TCPD in cycles" bitfld.long 0x20 0.--5. " TFAW ,Time FAW(cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x24 "DDR_CR11,DDR Control 11 Register" bitfld.long 0x24 24. " TREFEN ,Enable refresh commands" "Disabled,Enabled" bitfld.long 0x24 16. " AREFMODE ,Auto refresh mode" "Always,After end of transaction" textline " " bitfld.long 0x24 8. " AREF ,Auto Refresh enable" "Disabled,Enabled" bitfld.long 0x24 0. " REGDIMM ,Enable registered DIMM operations" "Disabled,Enabled" line.long 0x28 "DDR_CR12,DDR Control 12 Register" hexmask.long.word 0x28 16.--29. 1. " TREF ,DRAM cycles between refresh commands" hexmask.long.word 0x28 0.--9. 1. " TRFC ,DRAM refresh command time" line.long 0x2c "DDR_CR13,DDR Control 13 Register" bitfld.long 0x2c 16. " PD ,DRAM Power Down" "Not powered-down,Powered-down" rgroup.long 0x38++0x3 line.long 0x00 "DDR_CR14,DDR Control 14 Register" hexmask.long.word 0x00 16.--31. 1. " TXSR ,Time Exit Self Refresh" hexmask.long.word 0x00 0.--15. 1. " TPDEX ,Time Power Down Exit" group.long 0x3c++0x1f line.long 0x00 "DDR_CR15,DDR Control 15 Register" bitfld.long 0x00 24. " PUREF ,Refresh enable" "Disabled,Enabled" bitfld.long 0x00 16. " SREF ,Self Refresh Enable" "Disabled,Enabled" hexmask.long.word 0x00 0.--15. 1. " TXSNR ,DRAM TXSNR parameter in cycles" line.long 0x04 "DDR_CR16,DDR Control 16 Register" bitfld.long 0x04 20. " LPCTRL[4] ,Memory power-down mode enable" "Disabled,Enabled" bitfld.long 0x04 19. " LPCTRL[3] ,Memory power-down with memory clock gating mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " LPCTRL[2] ,Memory self-refresh mode enable" "Disabled,Enabled" bitfld.long 0x04 17. " LPCTRL[1] ,Memory self-refresh with memory clock gating mode enable" "Disabled,Enabled" textline " " bitfld.long 0x04 16. " LPCTRL[0] ,Memory self-refresh with memory and controller clock gating mode enable" "Disabled,Enabled" bitfld.long 0x04 8.--10. " CLKDLY ,Clock Delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 0. " QKREF ,Enable quick self-refresh" "Disabled,Enabled" line.long 0x08 "DDR_CR17,DDR Control 17 Register" hexmask.long.word 0x08 16.--31. 1. " LPRFCNT ,Low Power Refresh Count" hexmask.long.word 0x08 0.--15. 1. " LPPDCNT ,Low Power Power Down Count" line.long 0x0c "DDR_CR18,DDR Control 18 Register" bitfld.long 0x0C 20. " LPAUTO[4] ,Memory power-down mode" "Manual,Auto" bitfld.long 0x0C 19. " LPAUTO[3] ,Memory power-down with memory clock gating mode" "Manual,Auto" textline " " bitfld.long 0x0C 18. " LPAUTO[2] ,Memory self-refresh mode" "Manual,Auto" bitfld.long 0x0C 17. " LPAUTO[1] ,Memory self-refresh with memory clock gating mode" "Manual,Auto" textline " " bitfld.long 0x0C 16. " LPAUTO[0] ,Memory self-refresh with memory and controller clock gating mode" "Manual,Auto" hexmask.long.word 0x0C 0.--15. 1. " LPEXTCNT ,Low Power External Count" line.long 0x10 "DDR_CR19,DDR Control 19 Register" hexmask.long.word 0x10 16.--31. 1. " LPRFHOLD ,Low Power Refresh Hold" hexmask.long.word 0x10 0.--15. 1. " LPINTCNT ,Low Power Interval Count" line.long 0x14 "DDR_CR20,DDR Control 20 Register" bitfld.long 0x14 24. " WRMD ,Write mode register data to the DRAMs" "Not written,Written" bitfld.long 0x14 16.--19. " CKSRX ,Clock stable delay on self refresh exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--11. " CKSRE ,Clock hold delay on self refresh entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--1. " LPRE ,Low Power Refresh enable" "Enabled,Disabled,?..." line.long 0x18 "DDR_CR21,DDR Control 21 Register" hexmask.long.word 0x18 16.--31. 1. " MR1DAT0 ,Data to program into memory mode register 1 for chip select" hexmask.long.word 0x18 0.--15. 1. " MR0DAT0 ,Data to program into memory mode register 0 for chip select" line.long 0x1c "DDR_CR22,DDR Control 22 Register" hexmask.long.word 0x1C 16.--31. 1. " MR3DAT0 ,Data to program into memory mode register 3 for chip select" hexmask.long.word 0x1C 0.--15. 1. " MR2DATA0 ,Data to program into memory mode register 2 for chip select" hgroup.long 0x5c++0x7 hide.long 0x00 "DDR_CR23,DDR Control 23 Register" hide.long 0x04 "DDR_CR24,DDR Control 24 Register" group.long 0x64++0x1b line.long 0x00 "DDR_CR25,DDR Control 25 Register" bitfld.long 0x00 24.--27. " APREBIT ,Location of the auto precharge bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--18. " COLSIZ ,Column Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " ADDPINS ,Address Pins" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " BNK8 ,Number of banks on the DRAMs" "4,8" line.long 0x04 "DDR_CR26,DDR Control 26 Register" bitfld.long 0x04 24. " BNKSPT ,Bank Split enable" "Disabled,Enabled" bitfld.long 0x04 16. " ADDCOL ,Address Collision enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x04 8.--15. 1. " CMDAGE ,Command Age count" hexmask.long.byte 0x04 0.--7. 1. " AGECNT ,Age Count" line.long 0x08 "DDR_CR27,DDR Control 27 Register" bitfld.long 0x08 24. " SWPEN ,Swap Enable" "Disabled,Enabled" bitfld.long 0x08 16. " RWEN ,Read Write same Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " PRIEN ,Priority Enable" "Disabled,Enabled" bitfld.long 0x08 0. " PLEN ,Placement Enable" "Disabled,Enabled" line.long 0x0c "DDR_CR28,DDR Control 28 Register" bitfld.long 0x0C 24. " CMDLATR ,Command Latency Reduction Enable" "Disabled,Enabled" bitfld.long 0x0C 16. " BIGEND ,Big Endian Enable" "Little,Big" textline " " bitfld.long 0x0C 8. " REDUC ,Width of the memory datapath" "16-bit,8-bit" bitfld.long 0x0C 0. " CSMAP ,Chip Select Enable" "Disabled,Enabled" line.long 0x10 "DDR_CR29,DDR Control 29 Register" bitfld.long 0x10 24. " RESYNC ,Initiate a DLL resync" "No effect,Initiate" bitfld.long 0x10 16.--17. " QFULL ,Queue Fullness" "0,1,2,3" textline " " bitfld.long 0x10 8. " FSTWR ,Define when write commands are issued to DRAM devices" "Receive data for one DMA burst,After first word of data" bitfld.long 0x10 0. " WRLATR ,Write Latency Reduction enable" "Disabled,Enabled" line.long 0x14 "DDR_CR30,DDR Control 30 Register" bitfld.long 0x14 31. " INTACK[7] ,Interrupt Acknowledge" "No effect,Clear" bitfld.long 0x14 30. " INTACK[6] ,Interrupt Acknowledge" "No effect,Clear" textline " " bitfld.long 0x14 29. " INTACK[5] ,Interrupt Acknowledge" "No effect,Clear" bitfld.long 0x14 28. " INTACK[4] ,Interrupt Acknowledge" "No effect,Clear" textline " " bitfld.long 0x14 27. " INTACK[3] ,Interrupt Acknowledge" "No effect,Clear" bitfld.long 0x14 26. " INTACK[2] ,Interrupt Acknowledge" "No effect,Clear" textline " " bitfld.long 0x14 25. " INTACK[1] ,Interrupt Acknowledge" "No effect,Clear" bitfld.long 0x14 24. " INTACK[0] ,Interrupt Acknowledge" "No effect,Clear" textline " " rbitfld.long 0x14 16. " INTSTAT[8] ,Logical OR of INTSTATUS[7:0]" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 15. " INTSTAT[7] ,User-initiated DLL resync finished" "No interrupt,Interrupt" rbitfld.long 0x14 14. " INTSTAT[6] ,dfi_int_complete state change detected" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 13. " INTSTAT[5] ,register interface mode register write finished" "No interrupt,Interrupt" rbitfld.long 0x14 12. " INTSTAT[4] ,CAS Latency 3 programmed error detected" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 11. " INTSTAT[3] ,Both DDR2 and Mobile enabled" "No interrupt,Interrupt" rbitfld.long 0x14 10. " INTSTAT[2] ,DRAM initialization complete" "No interrupt,Interrupt" textline " " rbitfld.long 0x14 9. " INTSTAT[1] ,Multiple accesses outside the defined physical memory space detected" "No interrupt,Interrupt" rbitfld.long 0x14 8. " INTSTAT[0] ,A single access outside the defined physical memory space detected" "No interrupt,Interrupt" textline " " bitfld.long 0x14 0. " RSYNCRF ,Enable automatic DLL resync after every refresh" "No effect,Enable" line.long 0x18 "DDR_CR31,DDR Control 31 Register" bitfld.long 0x18 8. " INTMASK[8] ,Interrupt Mask" "Not masked,Masked" bitfld.long 0x18 7. " INTMASK[7] ,Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x18 6. " INTMASK[6] ,Interrupt Mask" "Not masked,Masked" bitfld.long 0x18 5. " INTMASK[5] ,Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x18 4. " INTMASK[4] ,Interrupt Mask" "Not masked,Masked" bitfld.long 0x18 3. " INTMASK[3] ,Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x18 2. " INTMASK[2] ,Interrupt Mask" "Not masked,Masked" bitfld.long 0x18 1. " INTMASK[1] ,Interrupt Mask" "Not masked,Masked" textline " " bitfld.long 0x18 0. " INTMASK[0] ,Interrupt Mask" "Not masked,Masked" rgroup.long 0x80++0x7 line.long 0x00 "DDR_CR32,DDR Control 32 Register" line.long 0x04 "DDR_CR33,DDR Control 33 Register" bitfld.long 0x04 24.--25. " OORID ,Out Of Range source ID" "0,1,2,3" bitfld.long 0x04 16.--21. " OORTYP ,Out Of Range Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x04 0.--9. 1. " OORLEN ,Out Of Range Length" group.long 0x88++0x3 line.long 0x00 "DDR_CR34,DDR Control 34 Register" bitfld.long 0x00 8. " ODTWRCS ,Determine if the chip select has termination when a write occurs on the chip select" "No,Yes" bitfld.long 0x00 0. " ODTRDC ,Determine if the chip select has termination when a read occurs on the chip select" "No,Yes" rgroup.long 0x8c++0x3 line.long 0x00 "DDR_CR35,DDR Control 35 Register" bitfld.long 0x00 8.--11. " W2RSMCS ,Additional clocks of delay to insert between WR and RD transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " R2WSMCS ,Additional clocks of delay to insert between RD and WR transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x90++0x3 hide.long 0x00 "DDR_CR36,DDR Control 36 Register" group.long 0x94++0x53 line.long 0x00 "DDR_CR37,DDR Control 37 Register" bitfld.long 0x00 24.--26. " W2WSAME ,W2W Same chip select delay" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " W2RSAME ,W2R Same chip select delay" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 8.--10. " R2WSAME ,R2W Same chip select delay" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " R2RSAME ,R2R Same chip select delay" "0,1,2,3,4,5,6,7" line.long 0x04 "DDR_CR38,DDR Control 38 Register" hexmask.long.word 0x04 16.--26. 1. " PWRCNT ,Port 0 Write Count" textline " " bitfld.long 0x04 12. " PUPCS[4] ,OCD settings" "Decremented,Incremented" bitfld.long 0x04 8.--11. " PUPCS[3:0] ,Number of OCD adjustment commands to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 4. " PDNCS[4] ,OCD settings" "Decremented,Incremented" bitfld.long 0x04 0.--3. " PDNCS[3:0] ,Number of OCD adjustment commands to issue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "DDR_CR39,DDR Control 39 Register" bitfld.long 0x08 24.--25. " WP0 ,Port 0 Write command Priority" "Highest,,,Lowest" bitfld.long 0x08 16.--17. " RP0 ,Port 0 Read command Priority" "Highest,,,Lowest" textline " " hexmask.long.word 0x08 0.--10. 1. " P0RDCNT ,Port 0 Read command Count" line.long 0x0c "DDR_CR40,DDR Control 40 Register" hexmask.long.word 0x0C 8.--18. 1. " P1WRCNT ,Port 1 Write command Count" bitfld.long 0x0C 0.--1. " P0TYP ,Port 0 Type" "Asynchronous,,,Synchronous" line.long 0x10 "DDR_CR41,DDR Control 41 Register" bitfld.long 0x10 24.--25. " WP1 ,Write command priority Port 1" "Highest,,,Lowest" bitfld.long 0x10 16.--17. " RP1 ,Read command priority Port 1" "Highest,,,Lowest" textline " " hexmask.long.word 0x10 0.--10. 1. " P1RDCNT ,Port 1 Read command Count" line.long 0x14 "DDR_CR42,DDR Control 42 Register" hexmask.long.word 0x14 8.--18. 1. " P2WRCNT ,Port 2 Write command Count" bitfld.long 0x14 0.--1. " P1TYP ,Port 1 Type" "Asynchronous,,,Synchronous" line.long 0x18 "DDR_CR43,DDR Control 43 Register" bitfld.long 0x18 24.--25. " WP2 ,Write command priority Port 2" "Highest,,,Lowest" bitfld.long 0x18 16.--17. " RP2 ,Read command priority Port 2" "Highest,,,Lowest" textline " " hexmask.long.word 0x18 0.--10. 1. " P2RDCNT ,Port 2 Read command Count" line.long 0x1c "DDR_CR44,DDR Control 44 Register" rbitfld.long 0x1C 27. " WRRERR[3] ,The port ordering parameter values for paired ports is not sequential" "Not occurred,Occurred" rbitfld.long 0x1C 26. " WRRERR[2] ,The relative priority values for any of the ports paired are not identical" "Not occurred,Occurred" textline " " rbitfld.long 0x1C 25. " WRRERR[1] ,Any of the relative priority parameters have been programmed with a zero value" "Not occurred,Occurred" rbitfld.long 0x1C 24. " WRRERR[0] ,The port ordering parameters do not all contain unique values" "Not occurred,Occurred" textline " " bitfld.long 0x1C 16. " WRRSHARE ,Per-port pair shared arbitration for weighted-round-robin" "Treated independently,Grouped together" bitfld.long 0x1C 8. " WRRLAT ,WRR Latency" "Free-running,Limited" textline " " bitfld.long 0x1C 0.--1. " P2TYP ,Port 2 Type" "Asynchronous,,,Synchronous" line.long 0x20 "DDR_CR45,DDR Control 45 Register" bitfld.long 0x20 24.--27. " P0PRI3 ,Port 0 Priority 3 commands" "Lowest,,,,,,,,,,,,,,,Highest" bitfld.long 0x20 16.--19. " P0PRI2 ,Port 0 Priority 2 commands" "Lowest,,,,,,,,,,,,,,,Highest" textline " " bitfld.long 0x20 8.--11. " P0PRI1 ,Port 0 Priority 1 commands" "Lowest,,,,,,,,,,,,,,,Highest" bitfld.long 0x20 0.--3. " P0PRI0 ,Port 0 Priority 0 commands" "Lowest,,,,,,,,,,,,,,,Highest" line.long 0x24 "DDR_CR46,DDR Control 46 Register" bitfld.long 0x24 24.--27. " P1PRI0 ,Port 1 Priority 0 commands" "Lowest,,,,,,,,,,,,,,,Highest" hexmask.long.word 0x24 8.--17. 1. " P0PRIRLX ,Port 0 Priority Relax" textline " " bitfld.long 0x24 0.--1. " P0ORD ,Port 0 Order" "Highest listing in the scan order,,,Lowest listing in the scan order" line.long 0x28 "DDR_CR47,DDR Control 47 Register" bitfld.long 0x28 24.--25. " P1ORD ,Port 1 Order" "Highest listing in the scan order,,,Lowest listing in the scan order" bitfld.long 0x28 16.--19. " P1PRI3 ,Port 1 Priority 3 commands" "Lowest,,,,,,,,,,,,,,,Highest" textline " " bitfld.long 0x28 8.--11. " P1PRI2 ,Port 1 Priority 2 commands" "Lowest,,,,,,,,,,,,,,,Highest" bitfld.long 0x28 0.--3. " P1PRI1 ,Port 1 Priority 1 commands" "Lowest,,,,,,,,,,,,,,,Highest" line.long 0x2c "DDR_CR48,DDR Control 48 Register" bitfld.long 0x2C 24.--27. " P2PRI1 ,Port 2 Priority 1 commands" "Lowest,,,,,,,,,,,,,,,Highest" bitfld.long 0x2C 16.--19. " P2PRI0 ,Port 2 Priority 0 commands" "Lowest,,,,,,,,,,,,,,,Highest" textline " " hexmask.long.word 0x2C 0.--9. 1. " P1PRIRLX ,Port 1 Priority Relax" line.long 0x30 "DDR_CR49,DDR Control 49 Register" bitfld.long 0x30 16.--17. " P2ORD ,Port 2 Order" "Highest listing in the scan order,,,Lowest listing in the scan order" bitfld.long 0x30 8.--11. " P2PRI3 ,Port 2 Priority 3 commands" "Lowest,,,,,,,,,,,,,,,Highest" textline " " bitfld.long 0x30 0.--3. " P2PRI2 ,Port 2 Priority 2 commands" "Lowest,,,,,,,,,,,,,,,Highest" line.long 0x34 "DDR_CR50,DDR Control 50 Register" rbitfld.long 0x34 16. " CLKSTATUS ,Clock Status" "Disabled,Enabled" hexmask.long.word 0x34 0.--9. 1. " P2PRIRLX ,Port 2 Priority Relax" line.long 0x38 "DDR_CR51,DDR Control 51 Register" rbitfld.long 0x38 24.--27. " PHYWRLAT ,PHY Write Latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x38 16.--23. 1. " DLLRADLY ,DLL Reset Adjust Delay" textline " " hexmask.long.word 0x38 0.--15. 1. " DLLRSTDLY ,DLL Reset Delay" line.long 0x3c "DDR_CR52,DDR Control 52 Register" bitfld.long 0x3C 24.--27. " RDDTENBAS ,Read Data Enable Base Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x3C 16.--19. " RDDATAEN ,Read Data Enable Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x3C 8.--11. " PHYRDLAT ,PHY Read Latency Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x3C 0.--3. " PYWRLTBS ,PHY Write Latency Base Timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x40 "DDR_CR53,DDR Control 53 Register" sif cpuis("MK70*") bitfld.long 0x40 0. " CLKDISCS ,DRAM Clock Disable for chip select" "No,Yes" else hexmask.long.word 0x40 16.--29. 1. " CTRLUPDMX ,DFI CRTLUPD Maximum" bitfld.long 0x40 8.--11. " CRTLUPDMN ,DFI CRTLUPD Minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x40 0. " CLKDISCS ,DRAM Clock Disable for chip select" "No,Yes" endif sif cpuis("MK70*") hgroup.long 0xD8++0x07 hide.long 0x00 "DDR_CR54,DDR Control 54 Register" hide.long 0x04 "DDR_CR55,DDR Control 55 Register" group.long 0xE0++0x07 line.long 0x00 "DDR_CR56,DDR Control 56 Register" bitfld.long 0x00 24.--27. " WRLATADJ ,Adjustment value for PHY write timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RDLATADJ ,Adjustment value for PHY read timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "DDR_CR57,DDR Control 57 Register" bitfld.long 0x04 24. " ODTALTEN ,ODT Alternate Enable" "Disabled,Enabled" else group.long 0xD8++0x0F line.long 0x00 "DDR_CR54,DDR Control 54 Register" hexmask.long.word 0x00 16.--29. 1. " PHYUPDTY1 ,DFI PHYUPD Type 1" hexmask.long.word 0x00 0.--13. 1. " PHYUPDTY0 ,DFI PHYUPD Type 0" line.long 0x04 "DDR_CR55,DDR Control 55 Register" hexmask.long.word 0x04 16.--29. 1. " PHYUPDTY3 ,DFI PHYUPD Type 3" hexmask.long.word 0x04 0.--13. 1. " PHYUPDTY2 ,DFI PHYUPD Type 2" line.long 0x08 "DDR_CR56,DDR Control 56 Register" bitfld.long 0x08 24.--27. " WRLATADJ ,Adjustment value for PHY write timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 16.--19. " RDLATADJ ,Adjustment value for PHY read timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x08 0.--13. 1. " PHYUPDRESP ,TDFI PHYUPDRESP timing" line.long 0x0C "DDR_CR57,DDR Control 57 Register" bitfld.long 0x0C 24. " ODTALTEN ,ODT Alternate Enable" "Disabled,Enabled" bitfld.long 0x0C 16.--19. " CLKENDLY ,DFI Clock Enable Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0C 8.--10. " CLKDISDLY ,DFI Clock Disable Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0C 0.--3. " CMDDLY ,Command Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif hgroup.long 0xe8++0x17 hide.long 0x00 "DDR_CR58,DDR Control 58 Register" hide.long 0x04 "DDR_CR59,DDR Control 59 Register" hide.long 0x08 "DDR_CR60,DDR Control 60 Register" hide.long 0x0c "DDR_CR61,DDR Control 61 Register" hide.long 0x10 "DDR_CR62,DDR Control 62 Register" hide.long 0x14 "DDR_CR63,DDR Control 63 Register" wgroup.long 0x180++0x3 line.long 0x00 "DDR_RCR,RCR Control Register" bitfld.long 0x00 30. " RST ,Software reset" "No reset,Reset" width 14. group.long 0x1AC++0x3 line.long 0x00 "DDR_PAD_CTRL,I/O Pad Control Register" bitfld.long 0x00 24.--25. " PAD_ODT_CS0 ,ODT configuration" "Disabled,75 Ohms,150 Ohms,50 Ohms" bitfld.long 0x00 0.--1. " SPARE_DLY_CTRL ,Delay chain control" "No buffer,4 buffers,7 buffers,10 buffers" width 0x0B tree.end tree.end tree.open "Security and integrity modules" tree "CRC (Cyclic redundancy check)" base ad:0x40032000 width 7. if (((per.l(ad:0x40032000+0x08)&0x1000000)==0x1000000)) group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 24.--31. 1. " HU ,CRC high upper byte" hexmask.long.byte 0x00 16.--23. 1. " HL ,CRC high lower byte" newline hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" else group.long 0x00++0x03 line.long 0x00 "CRC,CRC Data Register" hexmask.long.byte 0x00 8.--15. 1. " LU ,CRC low upper byte" hexmask.long.byte 0x00 0.--7. 1. " LL ,CRC low lower byte" endif group.long 0x04++0x07 line.long 0x00 "GPOLY,CRC Polynomial Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,High polynomial half-word" hexmask.long.word 0x00 0.--15. 1. " LOW ,Low polynomial half-word" line.long 0x04 "CTRL,CRC Control Register" bitfld.long 0x04 30.--31. " TOT ,Type of transpose for writes" "No transposition,Bits,Bits and bytes,Bytes" bitfld.long 0x04 28.--29. " TOTR ,Type of transpose for read" "No transposition,Bits,Bits and bytes,Bytes" newline bitfld.long 0x04 26. " FXOR ,Complement read of CRC data register" "No XOR,Inverted/Complemented" bitfld.long 0x04 25. " WAS ,Write CRC data register as seed" "Data values,Seed values" newline bitfld.long 0x04 24. " TCRC ,Width of CRC protocol" "16-bit,32-bit" width 0x0B tree.end tree "MMCAU (Memory-Mapped Cryptographic Acceleration Unit)" base ad:0xE0081000 width 6. group.long 0x00++0x03 line.long 0x00 "CASR,Status Register" rbitfld.long 0x00 28.--31. " VER ,CAU version" ",Initial CAU version,Second version(with SHA-256 algorithm),?..." bitfld.long 0x00 1. " DPE ,DES parity error" "No error,Error" bitfld.long 0x00 0. " IC ,Illegal command" "Not issued,Issued" group.long 0x01++0x03 line.long 0x00 "CAA,Accumulator" sif cpuis("MK24FN*") group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" else group.long 0x2++0x03 line.long 0x00 "CA0,General Purpose Register" group.long 0x3++0x03 line.long 0x00 "CA1,General Purpose Register" group.long 0x4++0x03 line.long 0x00 "CA2,General Purpose Register" group.long 0x5++0x03 line.long 0x00 "CA3,General Purpose Register" group.long 0x6++0x03 line.long 0x00 "CA4,General Purpose Register" group.long 0x7++0x03 line.long 0x00 "CA5,General Purpose Register" group.long 0x8++0x03 line.long 0x00 "CA6,General Purpose Register" group.long 0x9++0x03 line.long 0x00 "CA7,General Purpose Register" group.long 0xA++0x03 line.long 0x00 "CA8,General Purpose Register" endif width 0x0B tree.end tree "RNGA (Random Number Generator Accelerator)" base ad:0x400A0000 width 5. sif (cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) rgroup.long 0x00++0x03 line.long 0x00 "VER,RNGB Version ID Register" bitfld.long 0x00 28.--31. " TYPE ,Random number generator type" "RNGA,RNGB,RNGC,?..." hexmask.long.byte 0x00 8.--15. 1. " MAJOR ,Major version number" hexmask.long.byte 0x00 0.--7. 1. " MINOR ,Minor version number" group.long 0x04++0x07 line.long 0x00 "CMD,RNGB Command Register" bitfld.long 0x00 6. " SR ,Software reset" "No reset,Reset" bitfld.long 0x00 5. " CE ,Clear error" "No clear,Clear" bitfld.long 0x00 4. " CI ,Clear interrupt" "No clear,Clear" newline bitfld.long 0x00 1. " GS ,Generate seed" "Disabled,Enabled" bitfld.long 0x00 0. " ST ,Self test" "Disabled,Enabled" line.long 0x04 "CR,RNGB Control Register" bitfld.long 0x04 6. " MASKERR ,Mask error interrupt" "Not masked,Masked" bitfld.long 0x04 5. " MASKDONE ,Mask done interrupt" "Not masked,Masked" bitfld.long 0x04 4. " AR ,Auto-reseed enable" "Disabled,Enabled" newline bitfld.long 0x04 0.--1. " FUFMOD ,FIFO underflow response mode" "Return all zeros and set RNG_ESR[FUFE],Return all zeros and set RNG_ESR[FUFE],Generate bus transfer error,Generate interrupt and return all zeros" rgroup.long 0x0C++0x0B line.long 0x00 "SR,RNGB Status Register" bitfld.long 0x00 31. " STATPF[7] ,Long run test pass/fail" "Passed,Failed" bitfld.long 0x00 30. " [6] ,Length 6+ run test pass/fail" "Passed,Failed" bitfld.long 0x00 29. " [5] ,Length 5 run test pass/fail" "Passed,Failed" newline bitfld.long 0x00 28. " [4] ,Length 4 run test pass/fail" "Passed,Failed" bitfld.long 0x00 27. " [3] ,Length 3 run test pass/fail" "Passed,Failed" bitfld.long 0x00 26. " [2] ,Length 2 run test pass/fail" "Passed,Failed" newline bitfld.long 0x00 25. " [1] ,Length 1 run test pass/fail" "Passed,Failed" bitfld.long 0x00 24. " [0] ,Mon-obit test pass/fail" "Passed,Failed" newline bitfld.long 0x00 23. " ST_PF[2] ,TRNG self test pass/fail" "Passed,Failed" bitfld.long 0x00 22. " [1] ,PRNG self test pass/fail" "Passed,Failed" bitfld.long 0x00 21. " [0] ,RESEED self test pass/fail" "Passed,Failed" newline bitfld.long 0x00 16. " ERR ,Error was detected in the RNGB" "No error,Error" bitfld.long 0x00 12.--15. " FIFO_SIZE ,FIFO size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " FIFO_LVL ,FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6. " NSDN ,New seed done" "Not done,Done" bitfld.long 0x00 5. " SDN ,Seed done" "Not done,Done" bitfld.long 0x00 4. " STDN ,Self test done" "Not done,Done" newline bitfld.long 0x00 3. " RS ,Reseed needed" "Not needed,Needed" bitfld.long 0x00 2. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 1. " BUSY ,State of RNGB" "Not busy,Busy" line.long 0x04 "ESR,RNGB Error Status Register" bitfld.long 0x04 4. " FUFE ,FIFO underflow error" "Not occurred,Occurred" bitfld.long 0x04 3. " SATE ,Statistical test error" "Not occurred,Occurred" bitfld.long 0x04 2. " STE ,Self test error" "Not occurred,Occurred" newline bitfld.long 0x04 1. " OSCE ,Oscillator error" "Not occurred,Occurred" bitfld.long 0x04 0. " LFE ,Linear feedback shift register (LFSR) error" "Not occurred,Occurred" line.long 0x08 "OUT,RNGB Output FIFO" elif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("K26P169M180SF5RM")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") width 8. group.long 0x00++0x03 line.long 0x00 "CR,RNGA Control Register" bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " CLRI ,Clear interrupt" "No effect,Clear" bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 1. " HA ,High assurance enable" "Disabled,Enabled" bitfld.long 0x00 0. " GO ,Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled" "Disabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "SR,RNGA Status Register" hexmask.long.byte 0x00 16.--23. " OREG_SIZE ,Output register size" hexmask.long.byte 0x00 8.--15. " OREG_LVL ,Indicates the number of random-data words that are in OR[RANDOUT]" newline bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " ERRI ,Error interrupt" "Not occurred,Occurred" bitfld.long 0x00 2. " ORU ,Output register underflow" "No underflow,Underflow" newline bitfld.long 0x00 1. " LRS ,Last read status" "No underflow,Underflow" bitfld.long 0x00 0. " SECV ,Security violation" "Not occurred,Occurred" wgroup.long 0x08++0x03 line.long 0x00 "ER,RNGA Entropy Register" rgroup.long 0x0C++0x03 line.long 0x00 "OR,RNGA Output Register" else width 8. group.long 0x00++0x03 line.long 0x00 "CR,RNGA Control Register" bitfld.long 0x00 4. " SLP ,Sleep mode" "Disabled,Enabled" bitfld.long 0x00 3. " CLRI ,Clear interrupt" "No effect,Clear" bitfld.long 0x00 2. " INTM ,Interrupt mask" "Not masked,Masked" newline bitfld.long 0x00 1. " HA ,High assurance enable" "Disabled,Enabled" bitfld.long 0x00 0. " GO ,Specifies whether random-data generation and loading (into OR[RANDOUT]) is enabled" "Disabled,Enabled" newline hgroup.long 0x04++0x03 hide.long 0x00 "SR,RNGA Status Register" in wgroup.long 0x08++0x03 line.long 0x00 "ER,RNGA Entropy Register" hgroup.long 0x0C++0x03 hide.long 0x00 "OR,RNGA Output Register" in endif width 0x0B tree.end sif (!cpuis("MK70FN1M0VMJ1*")) tree "MCU DryIce" base ad:0x40042000 width 10. group.long 0x04++0x33 line.long 0x00 "DRY_SKVR,DryIce Secure Key Valid Register" eventfld.long 0x00 7. " SKV7 ,Secure Key Register 7 initialization status" "Not initialized,Initialized" eventfld.long 0x00 6. " SKV6 ,Secure Key Register 6 initialization status" "Not initialized,Initialized" eventfld.long 0x00 5. " SKV5 ,Secure Key Register 5 initialization status" "Not initialized,Initialized" textline " " eventfld.long 0x00 4. " SKV4 ,Secure Key Register 4 initialization status" "Not initialized,Initialized" eventfld.long 0x00 3. " SKV3 ,Secure Key Register 3 initialization status" "Not initialized,Initialized" eventfld.long 0x00 2. " SKV2 ,Secure Key Register 2 initialization status" "Not initialized,Initialized" textline " " eventfld.long 0x00 1. " SKV1 ,Secure Key Register 1 initialization status" "Not initialized,Initialized" eventfld.long 0x00 0. " SKV0 ,Secure Key Register 0 initialization status" "Not initialized,Initialized" line.long 0x04 "DRY_SKWLR,DryIce Secure Key Write Lock Register" bitfld.long 0x04 7. " SKWL7 ,Secure Key Register 7 write lock" "Locked,Unlocked" bitfld.long 0x04 6. " SKWL6 ,Secure Key Register 6 write lock" "Locked,Unlocked" bitfld.long 0x04 5. " SKWL5 ,Secure Key Register 5 write lock" "Locked,Unlocked" textline " " bitfld.long 0x04 4. " SKWL4 ,Secure Key Register 4 write lock" "Locked,Unlocked" bitfld.long 0x04 3. " SKWL3 ,Secure Key Register 3 write lock" "Locked,Unlocked" bitfld.long 0x04 2. " SKWL2 ,Secure Key Register 2 write lock" "Locked,Unlocked" textline " " bitfld.long 0x04 1. " SKWL1 ,Secure Key Register 1 write lock" "Locked,Unlocked" bitfld.long 0x04 0. " SKWL0 ,Secure Key Register 0 write lock" "Locked,Unlocked" line.long 0x08 "DRY_SKRLR,DryIce Secure Key Read Lock Register" bitfld.long 0x08 7. " SKRL7 ,Secure Key Register 7 read lock" "Locked,Unlocked" bitfld.long 0x08 6. " SKRL6 ,Secure Key Register 6 read lock" "Locked,Unlocked" bitfld.long 0x08 5. " SKRL5 ,Secure Key Register 5 read lock" "Locked,Unlocked" textline " " bitfld.long 0x08 4. " SKRL4 ,Secure Key Register 4 read lock" "Locked,Unlocked" bitfld.long 0x08 3. " SKRL3 ,Secure Key Register 3 read lock" "Locked,Unlocked" bitfld.long 0x08 2. " SKRL2 ,Secure Key Register 2 read lock" "Locked,Unlocked" textline " " bitfld.long 0x08 1. " SKRL1 ,Secure Key Register 1 read lock" "Locked,Unlocked" bitfld.long 0x08 0. " SKRL0 ,Secure Key Register 0 read lock" "Locked,Unlocked" line.long 0x0C "DRY_CR,DryIce Control Register" hexmask.long.word 0x0C 17.--31. 1. " DPR ,DryIce Prescaler Register" bitfld.long 0x0C 11. " TSRE ,Tamper Slew Rate Enable" "Slow,Fast" bitfld.long 0x0C 10. " TDSE ,Tamper Drive Strength Enable" "Low,High" textline " " bitfld.long 0x0C 9. " TPFE ,Tamper Passive Filter Enable" "Disabled,Enabled" bitfld.long 0x0C 8. " THYS ,Tamper Hysteresis Select" "305 mV - 440 mV,490 mV - 705 mV" bitfld.long 0x0C 3. " UM ,DryIce status register write prevention when tamper flag is set" "No,Yes" textline " " bitfld.long 0x0C 2. " TFSR ,Tamper Fore System Reset" "Not forced,Forced" bitfld.long 0x0C 1. " DEN ,DryIce Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " SWR ,Software reset" "No effect,Software reset" line.long 0x10 "DRY_SR,DryIce Status Register" bitfld.long 0x10 23. " TPF7 ,Tamper Pin Flag 7" "Not detected,Detected" bitfld.long 0x10 22. " TPF6 ,Tamper Pin Flag 6" "Not detected,Detected" bitfld.long 0x10 21. " TPF5 ,Tamper Pin Flag 5" "Not detected,Detected" textline " " bitfld.long 0x10 20. " TPF4 ,Tamper Pin Flag 4" "Not detected,Detected" bitfld.long 0x10 19. " TPF3 ,Tamper Pin Flag 3" "Not detected,Detected" bitfld.long 0x10 18. " TPF2 ,Tamper Pin Flag 2" "Not detected,Detected" textline " " bitfld.long 0x10 17. " TPF1 ,Tamper Pin Flag 1" "Not detected,Detected" bitfld.long 0x10 16. " TPF0 ,Tamper Pin Flag 0" "Not detected,Detected" bitfld.long 0x10 9. " TMF ,Test Mode Flag" "Not detected,Detected" textline " " bitfld.long 0x10 8. " FSF ,Flash Security Flag" "Not detected,Detected" bitfld.long 0x10 7. " STF ,Security Tamper Flag" "Not detected,Detected" bitfld.long 0x10 6. " TTF ,Temperature Tamper Flag" "Not detected,Detected" textline " " bitfld.long 0x10 5. " CTF ,Clock Tamper Flag" "Not detected,Detected" bitfld.long 0x10 4. " VTF ,Voltage Tamper Flag" "Not detected,Detected" bitfld.long 0x10 3. " MOF ,Monotonic Overflow Flag" "Not detected,Detected" textline " " bitfld.long 0x10 2. " TOF ,Time Overflow Flag" "Not detected,Detected" bitfld.long 0x10 1. " TAF ,Tamper Acknowledge Flag" "Not detected,Detected" bitfld.long 0x10 0. " DTF ,DryIce Tamper Flag" "Not detected,Detected" line.long 0x14 "DRY_LR,DryIce Lock Register" bitfld.long 0x14 23. " GFL7 ,Glitch Filter Lock 7" "Locked,Not locked" bitfld.long 0x14 22. " GFL6 ,Glitch Filter Lock 6" "Locked,Not locked" bitfld.long 0x14 21. " GFL5 ,Glitch Filter Lock 5" "Locked,Not locked" textline " " bitfld.long 0x14 20. " GFL4 ,Glitch Filter Lock 4" "Locked,Not locked" bitfld.long 0x14 19. " GFL3 ,Glitch Filter Lock 3" "Locked,Not locked" bitfld.long 0x14 18. " GFL2 ,Glitch Filter Lock 2" "Locked,Not locked" textline " " bitfld.long 0x14 17. " GFL1 ,Glitch Filter Lock 1" "Locked,Not locked" bitfld.long 0x14 16. " GFL0 ,Glitch Filter Lock 0" "Locked,Not locked" bitfld.long 0x14 13. " ATL1 ,Active Tamper Lock 1" "Locked,Not locked" textline " " bitfld.long 0x14 12. " ATL0 ,Active Tamper Lock 0" "Locked,Not locked" bitfld.long 0x14 11. " PPL ,Pin Polarity Lock" "Locked,Not locked" bitfld.long 0x14 10. " PDL ,Pin Direction Lock" "Locked,Not locked" textline " " bitfld.long 0x14 9. " TEL ,Tamper Enable Lock" "Locked,Not locked" bitfld.long 0x14 8. " TSL ,Tamper Seconds Lock" "Locked,Not locked" bitfld.long 0x14 7. " IEL ,Interrupt Enable Lock" "Locked,Not locked" textline " " bitfld.long 0x14 6. " LRL ,Lock Register Lock" "Locked,Not locked" bitfld.long 0x14 5. " SRL ,Status Register Lock" "Locked,Not locked" bitfld.long 0x14 4. " CRL ,Control Register Lock" "Locked,Not locked" textline " " bitfld.long 0x14 3. " KRL ,Key Read Lock" "Locked,Not locked" bitfld.long 0x14 2. " KWL ,Key Write Lock" "Locked,Not locked" bitfld.long 0x14 1. " KVL ,Key Valid Lock" "Locked,Not locked" line.long 0x18 "DRY_IER,DeyIce Interrupt Enable Register" bitfld.long 0x18 23. " TPIE7 ,Tamper Pin Interrupt Enable 7" "No interrupt,Interrupt" bitfld.long 0x18 22. " TPIE6 ,Tamper Pin Interrupt Enable 6" "No interrupt,Interrupt" bitfld.long 0x18 21. " TPIE5 ,Tamper Pin Interrupt Enable 5" "No interrupt,Interrupt" textline " " bitfld.long 0x18 20. " TPIE4 ,Tamper Pin Interrupt Enable 4" "No interrupt,Interrupt" bitfld.long 0x18 19. " TPIE3 ,Tamper Pin Interrupt Enable 3" "No interrupt,Interrupt" bitfld.long 0x18 18. " TPIE2 ,Tamper Pin Interrupt Enable 2" "No interrupt,Interrupt" textline " " bitfld.long 0x18 17. " TPIE1 ,Tamper Pin Interrupt Enable 1" "No interrupt,Interrupt" bitfld.long 0x18 16. " TPIE0 ,Tamper Pin Interrupt Enable 0" "No interrupt,Interrupt" bitfld.long 0x18 9. " TMIE ,Test Mode Interrupt Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x18 8. " FSIE ,Flash Security Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x18 7. " STIE ,Security Tamper Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x18 6. " TTIE ,Temperature Tamper Interrupt Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x18 5. " CTIE ,Clock Tamper Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x18 4. " VTIE ,Voltage Tamper Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x18 3. " MOIE ,Monotonic Overflow Interrupt Enable" "No interrupt,Interrupt" textline " " bitfld.long 0x18 2. " TOIE ,Time Overflow Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x18 0. " DTIE ,DryIce Tamper Interrupt Enable" "No interrupt,Interrupt" line.long 0x1C "DRY_TSR,DryIce Tamper Seconds Register" line.long 0x20 "DRY_TER,DryIce Tamper Enable Register" bitfld.long 0x20 23. " TPE7 ,Tamper Pin Enable 7" "Not detected,Detected" bitfld.long 0x20 22. " TPE6 ,Tamper Pin Enable 6" "Not detected,Detected" bitfld.long 0x20 21. " TPE5 ,Tamper Pin Enable 5" "Not detected,Detected" textline " " bitfld.long 0x20 20. " TPE4 ,Tamper Pin Enable 4" "Not detected,Detected" bitfld.long 0x20 19. " TPE3 ,Tamper Pin Enable 3" "Not detected,Detected" bitfld.long 0x20 18. " TPE2 ,Tamper Pin Enable 2" "Not detected,Detected" textline " " bitfld.long 0x20 17. " TPE1 ,Tamper Pin Enable 1" "Not detected,Detected" bitfld.long 0x20 16. " TPE0 ,Tamper Pin Enable 0" "Not detected,Detected" bitfld.long 0x20 9. " TME ,Test Mode Enable" "Not detected,Detected" textline " " bitfld.long 0x20 8. " FSE ,Flash Security Enable" "Not detected,Detected" bitfld.long 0x20 7. " STE ,Security Tamper Enable" "Not detected,Detected" bitfld.long 0x20 6. " TTE ,Temperature Tamper Enable" "Not detected,Detected" textline " " bitfld.long 0x20 5. " CTE ,Clock Tamper Enable" "Not detected,Detected" bitfld.long 0x20 4. " VTE ,Voltage Tamper Enable" "Not detected,Detected" bitfld.long 0x20 3. " MOE ,Monotonic Overflow Enable" "Not detected,Detected" textline " " bitfld.long 0x20 2. " TOE ,Time Overflow Enable" "Not detected,Detected" line.long 0x24 "DRY_PDR,DryIce Pin Direction Register" rbitfld.long 0x24 23. " TPOD7 ,Tamper Pin Output Data 7" "Logic zero,Logic one" rbitfld.long 0x24 22. " TPOD6 ,Tamper Pin Output Data 6" "Logic zero,Logic one" rbitfld.long 0x24 21. " TPOD5 ,Tamper Pin Output Data 5" "Logic zero,Logic one" textline " " rbitfld.long 0x24 20. " TPOD4 ,Tamper Pin Output Data 4" "Logic zero,Logic one" rbitfld.long 0x24 19. " TPOD3 ,Tamper Pin Output Data 3" "Logic zero,Logic one" rbitfld.long 0x24 18. " TPOD2 ,Tamper Pin Output Data 2" "Logic zero,Logic one" textline " " rbitfld.long 0x24 17. " TPOD1 ,Tamper Pin Output Data 1" "Logic zero,Logic one" rbitfld.long 0x24 16. " TPOD0 ,Tamper Pin Output Data 0" "Logic zero,Logic one" bitfld.long 0x24 7. " TPD7 ,Tamper Pin Direction 7" "Input,Output" textline " " bitfld.long 0x24 6. " TPD6 ,Tamper Pin Direction 6" "Input,Output" bitfld.long 0x24 5. " TPD5 ,Tamper Pin Direction 5" "Input,Output" bitfld.long 0x24 4. " TPD4 ,Tamper Pin Direction 4" "Input,Output" textline " " bitfld.long 0x24 3. " TPD3 ,Tamper Pin Direction 3" "Input,Output" bitfld.long 0x24 2. " TPD2 ,Tamper Pin Direction 2" "Input,Output" bitfld.long 0x24 1. " TPD1 ,Tamper Pin Direction 1" "Input,Output" textline " " bitfld.long 0x24 0. " TPD0 ,Tamper Pin Direction 0" "Input,Output" line.long 0x28 "DRY_PDR,DryIce Pin Polarity Register" rbitfld.long 0x28 23. " TPID7 ,Tamper Pin Input Data 7" "Logic zero,Logic one" rbitfld.long 0x28 22. " TPID6 ,Tamper Pin Input Data 6" "Logic zero,Logic one" rbitfld.long 0x28 21. " TPID5 ,Tamper Pin Input Data 5" "Logic zero,Logic one" textline " " rbitfld.long 0x28 20. " TPID4 ,Tamper Pin Input Data 4" "Logic zero,Logic one" rbitfld.long 0x28 19. " TPID3 ,Tamper Pin Input Data 3" "Logic zero,Logic one" rbitfld.long 0x28 18. " TPID2 ,Tamper Pin Input Data 2" "Logic zero,Logic one" textline " " rbitfld.long 0x28 17. " TPID1 ,Tamper Pin Input Data 1" "Logic zero,Logic one" rbitfld.long 0x28 16. " TPID0 ,Tamper Pin Input Data 0" "Logic zero,Logic one" bitfld.long 0x28 7. " TPP7 ,Tamper Pin Polarity 7" "Not inverted,Inverted" textline " " bitfld.long 0x28 6. " TPP6 ,Tamper Pin Polarity 6" "Not inverted,Inverted" bitfld.long 0x28 5. " TPP5 ,Tamper Pin Polarity 5" "Not inverted,Inverted" bitfld.long 0x28 4. " TPP4 ,Tamper Pin Polarity 4" "Not inverted,Inverted" textline " " bitfld.long 0x28 3. " TPP3 ,Tamper Pin Polarity 3" "Not inverted,Inverted" bitfld.long 0x28 2. " TPP2 ,Tamper Pin Polarity 2" "Not inverted,Inverted" bitfld.long 0x28 1. " TPP1 ,Tamper Pin Polarity 1" "Not inverted,Inverted" textline " " bitfld.long 0x28 0. " TPP0 ,Tamper Pin Polarity 0" "Not inverted,Inverted" line.long 0x2C "DRY_ATR0,DryIce Active Tamper Register 0" hexmask.long.word 0x2C 16.--31. 1. " ATP ,Active Tamper Polynomial" hexmask.long.word 0x2C 0.--15. 1. " ATSR ,Active Tamper Shift Register" line.long 0x30 "DRY_ATR1,DryIce Active Tamper Register 1" hexmask.long.word 0x30 16.--31. 1. " ATP ,Active Tamper Polynomial" hexmask.long.word 0x30 0.--15. 1. " ATSR ,Active Tamper Shift Register" group.long 0x40++0x1F line.long 0x0 "DRY_PGFR0,DryIce Pin Glitch Filter Register 0" bitfld.long 0x0 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x0 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x0 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x0 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x4 "DRY_PGFR1,DryIce Pin Glitch Filter Register 1" bitfld.long 0x4 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x4 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x4 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x4 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x8 "DRY_PGFR2,DryIce Pin Glitch Filter Register 2" bitfld.long 0x8 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x8 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x8 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x8 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x8 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0xC "DRY_PGFR3,DryIce Pin Glitch Filter Register 3" bitfld.long 0xC 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0xC 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0xC 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0xC 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0xC 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x10 "DRY_PGFR4,DryIce Pin Glitch Filter Register 4" bitfld.long 0x10 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x10 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x10 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x10 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x14 "DRY_PGFR5,DryIce Pin Glitch Filter Register 5" bitfld.long 0x14 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x14 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x14 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x14 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x14 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x18 "DRY_PGFR6,DryIce Pin Glitch Filter Register 6" bitfld.long 0x18 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x18 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x18 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x18 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x18 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" line.long 0x1C "DRY_PGFR7,DryIce Pin Glitch Filter Register 7" bitfld.long 0x1C 24. " TPE ,Tamper Pull Enable" "Disabled,Enabled" bitfld.long 0x1C 16.--17. " TPEX ,Tamper Pin Expected Value" "Logic zero,Tamper 0 output,Tamper 1 output,Tamper 0 XOR Tamper 1" bitfld.long 0x1C 7. " GFE ,Glitch Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x1C 6. " GFP ,Glitch Filter Enable" "Disabled,Enabled" bitfld.long 0x1C 0.--5. " GFW ,Glitch Filter Width" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,88,90,92,94,96,98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128" group.long 0x800++0x07 line.long 0x00 "DRY_WAC,DryIce Write Access Control Register" bitfld.long 0x00 23. " GFW7 ,Glitch Filter Writes ignore setting 7" "Ignored,Not ignored" bitfld.long 0x00 22. " GFW6 ,Glitch Filter Writes ignore setting 6" "Ignored,Not ignored" bitfld.long 0x00 21. " GFW5 ,Glitch Filter Writes ignore setting 5" "Ignored,Not ignored" textline " " bitfld.long 0x00 20. " GFW4 ,Glitch Filter Writes ignore setting 4" "Ignored,Not ignored" bitfld.long 0x00 19. " GFW3 ,Glitch Filter Writes ignore setting 3" "Ignored,Not ignored" bitfld.long 0x00 18. " GFW2 ,Glitch Filter Writes ignore setting 2" "Ignored,Not ignored" textline " " bitfld.long 0x00 17. " GFW1 ,Glitch Filter Writes ignore setting 1" "Ignored,Not ignored" bitfld.long 0x00 16. " GFW0 ,Glitch Filter Writes ignore setting 0" "Ignored,Not ignored" bitfld.long 0x00 13. " ATW1 ,Active Tamper Writes ignore setting 1" "Ignored,Not ignored" textline " " bitfld.long 0x00 12. " ATW0 ,Active Tamper Writes ignore setting 0" "Ignored,Not ignored" bitfld.long 0x00 11. " PPW ,Pin Polarity Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 10. " PDW ,Pin Direction Writes ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x00 9. " TEW ,Tamper Enable Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 8. " TSRW ,Tamper Seconds Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 7. " IEW ,Interrupt Enable Writes ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x00 6. " LRW ,Lock Register Write Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 5. " SRW ,Status Register Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 4. " CRW ,Control Register Writes ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x00 3. " SKRRW ,Secure Key Read Lock Register Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 2. " SKWRW ,Secure Key Write Lock Register Writes ignore setting" "Ignored,Not ignored" bitfld.long 0x00 1. " SKVW ,Secure Key Valid Writes ignore setting" "Ignored,Not ignored" line.long 0x04 "DRY_WAC,DryIce Write Access Control Register" bitfld.long 0x04 23. " GFR7 ,Glitch Filter Reads ignore setting 7" "Ignored,Not ignored" bitfld.long 0x04 22. " GFR6 ,Glitch Filter Reads ignore setting 6" "Ignored,Not ignored" bitfld.long 0x04 21. " GFR5 ,Glitch Filter Reads ignore setting 5" "Ignored,Not ignored" textline " " bitfld.long 0x04 20. " GFR4 ,Glitch Filter Reads ignore setting 4" "Ignored,Not ignored" bitfld.long 0x04 19. " GFR3 ,Glitch Filter Reads ignore setting 3" "Ignored,Not ignored" bitfld.long 0x04 18. " GFR2 ,Glitch Filter Reads ignore setting 2" "Ignored,Not ignored" textline " " bitfld.long 0x04 17. " GFR1 ,Glitch Filter Reads ignore setting 1" "Ignored,Not ignored" bitfld.long 0x04 16. " GFR0 ,Glitch Filter Reads ignore setting 0" "Ignored,Not ignored" bitfld.long 0x04 13. " ATR1 ,Active Tamper Reads ignore setting 1" "Ignored,Not ignored" textline " " bitfld.long 0x04 12. " ATR0 ,Active Tamper Reads ignore setting 0" "Ignored,Not ignored" bitfld.long 0x04 11. " PPR ,Pin Polarity Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 10. " PDR ,Pin Direction Reads ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x04 9. " TER ,Tamper Enable Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 8. " TSRR ,Tamper Seconds Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 7. " IER ,Interrupt Enable Reads ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x04 6. " LRR ,Lock Register Write Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 5. " SRR ,Status Register Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 4. " CRR ,Control Register Reads ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x04 3. " SKRRR ,Secure Key Read Lock Register Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 2. " SKWRR ,Secure Key Write Lock Register Reads ignore setting" "Ignored,Not ignored" bitfld.long 0x04 1. " SKVR ,Secure Key Valid Reads ignore setting" "Ignored,Not ignored" group.long 0x1000++0x1F line.long 0x0 "DRY_SKR,Secure Key Register" line.long 0x4 "DRY_SKR,Secure Key Register" line.long 0x8 "DRY_SKR,Secure Key Register" line.long 0xC "DRY_SKR,Secure Key Register" line.long 0x10 "DRY_SKR,Secure Key Register" line.long 0x14 "DRY_SKR,Secure Key Register" line.long 0x18 "DRY_SKR,Secure Key Register" line.long 0x1C "DRY_SKR,Secure Key Register" group.long 0x1800++0x07 line.long 0x00 "DRY_SWAC,Secure Write Access Control" bitfld.long 0x00 7. " SKRW7 ,Secure Key Register 7 write ignore setting" "Ignored,Not ignored" bitfld.long 0x00 6. " SKRW6 ,Secure Key Register 6 write ignore setting" "Ignored,Not ignored" bitfld.long 0x00 5. " SKRW5 ,Secure Key Register 5 write ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x00 4. " SKRW4 ,Secure Key Register 4 write ignore setting" "Ignored,Not ignored" bitfld.long 0x00 3. " SKRW3 ,Secure Key Register 3 write ignore setting" "Ignored,Not ignored" bitfld.long 0x00 2. " SKRW2 ,Secure Key Register 2 write ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x00 1. " SKRW1 ,Secure Key Register 1 write ignore setting" "Ignored,Not ignored" bitfld.long 0x00 0. " SKRW0 ,Secure Key Register 0 write ignore setting" "Ignored,Not ignored" line.long 0x04 "DRY_SKRRR,Secure Key Read Access Control" bitfld.long 0x04 7. " SKRR7 ,Secure Key Register 7 read ignore setting" "Ignored,Not ignored" bitfld.long 0x04 6. " SKRR6 ,Secure Key Register 6 read ignore setting" "Ignored,Not ignored" bitfld.long 0x04 5. " SKRR5 ,Secure Key Register 5 read ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x04 4. " SKRR4 ,Secure Key Register 4 read ignore setting" "Ignored,Not ignored" bitfld.long 0x04 3. " SKRR3 ,Secure Key Register 3 read ignore setting" "Ignored,Not ignored" bitfld.long 0x04 2. " SKRR2 ,Secure Key Register 2 read ignore setting" "Ignored,Not ignored" textline " " bitfld.long 0x04 1. " SKRR1 ,Secure Key Register 1 read ignore setting" "Ignored,Not ignored" bitfld.long 0x04 0. " SKRR0 ,Secure Key Register 0 read ignore setting" "Ignored,Not ignored" width 0x0B tree.end endif tree.end tree.open "Analog Modules" tree.open "ADC (Analog-to-Digital Converter)" tree "ADC 0" base ad:0x4003b000 width 11. if (((per.l(ad:0x4003b000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN512VMC10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,ADC0_DP2,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DCP0,,,ADC0_DP3,ADC0_SE4a,ADC0_SE5a,ADC0_SE6a,ADC0_SE7a,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,ADC0_DP3,,,,,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003b000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN512VMC10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,,,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,,,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,ADC0_DP2,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,ADC0_DM1,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DCP0,,,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC_SE16,ADC0_SE17,ADC0_SE18,ADC0_DM0,,ADC0_SE21,ADC0_SE22,12-bit DAC0/ADC0_SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,DP2/DM2,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" ",,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4003b000))&0x20)==0x00)&&(((per.l(ad:0x4003b000+0x04))&0x20)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Diff 9-bit,Single-ended 12-bit/Diff 13-bit,Single-ended 10-bit/Diff 11-bit,Single ended 16-bit/Diff 16-bit" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256VR")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "CFG2,ADC Configuration Register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-Speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles" newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.long 0x10++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x14++0x03 hide.long 0x00 "RB,ADC Data Result Register" in else if (((per.l(ad:0x4003b000))&0x20)==0x00) if (((per.l(ad:0x4003b000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.byte 0x00 0.--7. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.byte 0x04 0.--7. 1. " D ,Data result" elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--11. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--11. 1. " D ,Data result" elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--9. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--9. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif else if (((per.l(ad:0x4003b000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--8. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--8. 1. " D ,Data result" elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--12. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--12. 1. " D ,Data result" elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--10. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--10. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") if (((per.l(ad:0x4003b000))&0x20)==0x00) if (((per.l(ad:0x4003b000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif else if (((per.l(ad:0x4003b000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003b000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003b000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x20++0x2F line.long 0x00 "SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x04 "SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x10 "MG,ADC Minus-Side Gain Register" hexmask.long.word 0x10 0.--15. 1. " MG ,Minus-side Gain" line.long 0x14 "CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CLP4,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x1C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x20 0.--8. 1. " CLP3 ,Calibration value" line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x24 0.--7. 1. " CLP2 ,Calibration value" line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x28 0.--6. 1. " CLP1 ,Calibration value" line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register" bitfld.long 0x2C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("MK63FR")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256VR")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") sif cpuis("MK??FR")||cpuis("KK60FN1M0VLQ15") group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 21. " PGACHPB ,PGA chopping enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" newline bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " PGAOFSM ,PGA run mode" "Normal,Offset measurement" else group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." endif endif group.long 0x54++0x1B line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,ADC Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,ADC Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "ADC 1" base ad:0x400bb000 width 11. if (((per.l(ad:0x400bb000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4a,ADC0_SE5a,ADC0_SE6a,ADC0_SE7a,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DC0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x400bb000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400bb000))&0x20)==0x00)&&(((per.l(ad:0x400bb000+0x04))&0x20)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Diff 9-bit,Single-ended 12-bit/Diff 13-bit,Single-ended 10-bit/Diff 11-bit,Single ended 16-bit/Diff 16-bit" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256VR")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "CFG2,ADC Configuration Register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-Speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles" newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.long 0x10++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x14++0x03 hide.long 0x00 "RB,ADC Data Result Register" in else if (((per.l(ad:0x400bb000))&0x20)==0x00) if (((per.l(ad:0x400bb000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.byte 0x00 0.--7. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.byte 0x04 0.--7. 1. " D ,Data result" elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--11. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--11. 1. " D ,Data result" elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--9. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--9. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif else if (((per.l(ad:0x400bb000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--8. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--8. 1. " D ,Data result" elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--12. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--12. 1. " D ,Data result" elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--10. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--10. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") if (((per.l(ad:0x400bb000))&0x20)==0x00) if (((per.l(ad:0x400bb000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif else if (((per.l(ad:0x400bb000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bb000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bb000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x20++0x2F line.long 0x00 "SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x04 "SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x10 "MG,ADC Minus-Side Gain Register" hexmask.long.word 0x10 0.--15. 1. " MG ,Minus-side Gain" line.long 0x14 "CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CLP4,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x1C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x20 0.--8. 1. " CLP3 ,Calibration value" line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x24 0.--7. 1. " CLP2 ,Calibration value" line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x28 0.--6. 1. " CLP1 ,Calibration value" line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register" bitfld.long 0x2C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("MK63FR")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256VR")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") sif cpuis("MK??FR")||cpuis("KK60FN1M0VLQ15") group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 21. " PGACHPB ,PGA chopping enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" newline bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " PGAOFSM ,PGA run mode" "Normal,Offset measurement" else group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." endif endif group.long 0x54++0x1B line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,ADC Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,ADC Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "ADC 2" base ad:0x4003c000 width 11. if (((per.l(ad:0x4003c000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4a,ADC0_SE5a,ADC0_SE6a,ADC0_SE7a,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DC0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x4003c000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4003c000))&0x20)==0x00)&&(((per.l(ad:0x4003c000+0x04))&0x20)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Diff 9-bit,Single-ended 12-bit/Diff 13-bit,Single-ended 10-bit/Diff 11-bit,Single ended 16-bit/Diff 16-bit" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256VR")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "CFG2,ADC Configuration Register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-Speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles" newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.long 0x10++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x14++0x03 hide.long 0x00 "RB,ADC Data Result Register" in else if (((per.l(ad:0x4003c000))&0x20)==0x00) if (((per.l(ad:0x4003c000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.byte 0x00 0.--7. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.byte 0x04 0.--7. 1. " D ,Data result" elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--11. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--11. 1. " D ,Data result" elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--9. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--9. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif else if (((per.l(ad:0x4003c000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--8. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--8. 1. " D ,Data result" elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--12. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--12. 1. " D ,Data result" elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--10. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--10. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") if (((per.l(ad:0x4003c000))&0x20)==0x00) if (((per.l(ad:0x4003c000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif else if (((per.l(ad:0x4003c000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" endif elif (((per.l(ad:0x4003c000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x4003c000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x20++0x2F line.long 0x00 "SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x04 "SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x10 "MG,ADC Minus-Side Gain Register" hexmask.long.word 0x10 0.--15. 1. " MG ,Minus-side Gain" line.long 0x14 "CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CLP4,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x1C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x20 0.--8. 1. " CLP3 ,Calibration value" line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x24 0.--7. 1. " CLP2 ,Calibration value" line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x28 0.--6. 1. " CLP1 ,Calibration value" line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register" bitfld.long 0x2C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("MK63FR")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256VR")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") sif cpuis("MK??FR")||cpuis("KK60FN1M0VLQ15") group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 21. " PGACHPB ,PGA chopping enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" newline bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " PGAOFSM ,PGA run mode" "Normal,Offset measurement" else group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." endif endif group.long 0x54++0x1B line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,ADC Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,ADC Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "ADC 3" base ad:0x400bc000 width 11. if (((per.l(ad:0x400bc000+0x0))&0x20)==0x00) group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4a,ADC0_SE5a,ADC0_SE6a,ADC0_SE7a,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DC0,DP1,,DP3,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4a,SE5a,SE6a,SE7a,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x0++0x03 line.long 0x00 "SC1A,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif if (((per.l(ad:0x400bc000+0x4))&0x20)==0x00) group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,,,SE14,SE15,,SE17,VREF,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,,,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "ADC0_DP0,ADC0_DP1,PGA0_DP,ADC0_DP3,ADC0_SE4b,ADC0_SE5b,ADC0_SE6b,ADC0_SE7b,ADC0_SE8,ADC0_SE9,ADC0_SE10,ADC0_SE11,ADC0_SE12,ADC0_SE13,ADC0_SE14,ADC0_SE15,ADC0_SE16,ADC0_SE17,VREF,ADC0_DM0,ADC0_DM1,,,12-bit DAC1,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60FN1M0VLQ15") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,PGA1_DP,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,,,VREF,DM0,DM1,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,DM1,,,,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,DP1,,DP3,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0,,,,SE4b,SE5b,SE6b,SE7b,SE8,SE9,SE10,SE11,SE12,SE13,SE14,SE15,SE16,SE17,VREF/SE18,DM0,,,,12-bit DAC1/SE23,,,Temp sensor (S.E),Bandgap (S.E),,VREFH (S.E),VREFL,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,AD4a,AD5a,AD6a,AD7a,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,,AD17,AD18,,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" elif cpuis("MK8?FN256VR")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQR")||cpuis("MK30DX256VLL7R")||cpuis("MK70FN1M0VMJ1R")||cpuis("MK40DRZR10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DADP0,DADP1,DADP2,DADP3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,VREFSH,VREFSL,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,AD2,AD3,AD4,AD5,AD6,AD7,AD8,AD9,AD10,AD11,AD12,AD13,AD14,AD15,AD16,AD17,AD18,AD19,AD20,AD21,AD22,AD23,,,Temp sensor,Bandgap,,,VREFSL,Disabled" endif else group.long 0x4++0x03 line.long 0x00 "SC1B,ADC Status and Control Register 1" rbitfld.long 0x00 7. " COCO ,Conversion complete flag" "Not completed,Completed" bitfld.long 0x00 6. " AIEN ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " DIFF ,Differential mode enable" "Disabled,Enabled" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,PGA0_DP/PGA0_DM,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,VREFH (Diff),,Disabled" elif cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,DP1/DM1,,DP3/DM3,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" elif cpuis("MK66FN2M0VLQ18R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DP0/DM0,,,,,,,,,,,,,,,,,,,,,,,,,,Temp sensor (Diff),Bandgap (Diff),,,,Disabled" endif elif cpuis("MK84FN2M0CAU15R") newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "AD0,AD1,,AD3,,,,,,,,,,,,,,,,,,,,,Sense bus,,Temp sensor,Bandgap,,-VREFSH,,Disabled" else newline bitfld.long 0x00 0.--4. " ADCH ,Input channel select" "DAD0,DAD1,DAD2,DAD3,,,,,,,,,,,,,,,,,,,,,,,Temp Sensor,Bandgap,,-VREFSH,,Disabled" endif endif newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400bc000))&0x20)==0x00)&&(((per.l(ad:0x400bc000+0x04))&0x20)==0x00) group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit,Single-ended 12-bit,Single-ended 10-bit,Single-ended 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Differential 9-bit,Differential 13-bit,Differential 11-bit,Differential 16-bit" bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif else group.long 0x08++0x03 line.long 0x00 "CFG1,ADC Configuration Register 1" bitfld.long 0x00 7. " ADLPC ,Low-power configuration" "Normal,Low-power" bitfld.long 0x00 5.--6. " ADIV ,Clock divide select" "/1,/2,/4,/8" bitfld.long 0x00 4. " ADLSMP ,Sample time configuration" "Short,Long" newline bitfld.long 0x00 2.--3. " MODE ,Conversion mode selection" "Single-ended 8-bit/Diff 9-bit,Single-ended 12-bit/Diff 13-bit,Single-ended 10-bit/Diff 11-bit,Single ended 16-bit/Diff 16-bit" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256VR")||cpuis("MK8?FN256V*") newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus clock,ALTCLK2,ALTCLK,ADACK" else newline bitfld.long 0x00 0.--1. " ADICLK ,Input clock select" "Bus-clock,Bus-clock/2,ALTCLK,ADACK" endif endif group.long 0x0C++0x03 line.long 0x00 "CFG2,ADC Configuration Register 2" bitfld.long 0x00 4. " MUXSEL ,ADC Mux select" "ADCA,ADCB" bitfld.long 0x00 3. " ADACKEN ,Asynchronous clock output enable" "Disabled,Enabled" bitfld.long 0x00 2. " ADHSC ,High speed configuration" "Normal,High-Speed" newline bitfld.long 0x00 0.--1. " ADLSTS ,Long sample time select" "24 ADCK cycles,16 ADCK cycles,10 ADCK cycles,6 ADCK cycles" newline sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.long 0x10++0x03 hide.long 0x00 "RA,ADC Data Result Register" in hgroup.long 0x14++0x03 hide.long 0x00 "RB,ADC Data Result Register" in else if (((per.l(ad:0x400bc000))&0x20)==0x00) if (((per.l(ad:0x400bc000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.byte 0x00 0.--7. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.byte 0x04 0.--7. 1. " D ,Data result" elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--11. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--11. 1. " D ,Data result" elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--9. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--9. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif else if (((per.l(ad:0x400bc000+0x08))&0x0C)==0x00) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--8. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--8. 1. " D ,Data result" elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x04) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--12. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--12. 1. " D ,Data result" elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x08) rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--10. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--10. 1. " D ,Data result" else rgroup.long 0x10++0x07 line.long 0x00 "RA,ADC Data Result Register" hexmask.long.word 0x00 0.--15. 1. " D ,Data result" line.long 0x04 "RB,ADC Data Result Register" hexmask.long.word 0x04 0.--15. 1. " D ,Data result" endif endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") if (((per.l(ad:0x400bc000))&0x20)==0x00) if (((per.l(ad:0x400bc000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.byte 0x00 0.--7. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--11. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--9. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif else if (((per.l(ad:0x400bc000+0x08))&0x0C)==0x00) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--8. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x04) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--12. 1. " CV ,Compare value" endif elif (((per.l(ad:0x400bc000+0x08))&0x0C)==0x08) group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--10. 1. " CV ,Compare value" endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif endif else group.long 0x18++0x03 line.long 0x00 "CV1,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" if (((per.l(ad:0x400bc000+0x20))&0x08)==0x08) group.long 0x1C++0x03 line.long 0x00 "CV2,Compare Value Register" hexmask.long.word 0x00 0.--15. 1. " CV ,Compare value" endif endif group.long 0x20++0x2F line.long 0x00 "SC2,Status and Control Register 2" rbitfld.long 0x00 7. " ADACT ,Conversion active" "Not in progress,In progress" bitfld.long 0x00 6. " ADTRG ,Conversion trigger select" "Software,Hardware" bitfld.long 0x00 5. " ACFE ,Compare function enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " ACFGT ,Compare function greater than enable" "Disabled,Enabled" bitfld.long 0x00 3. " ACREN ,Compare function range enable" "Disabled,Enabled" bitfld.long 0x00 2. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " REFSEL ,Voltage reference selection" "Default,Alternate,?..." line.long 0x04 "SC3,Status and Control Register 3" bitfld.long 0x04 7. " CAL ,Calibration" "Not started,Started" eventfld.long 0x04 6. " CALF ,Calibration failed flag" "Not occurred,Occurred" bitfld.long 0x04 3. " ADCO ,Continuous conversion enable" "Disabled,Enabled" newline bitfld.long 0x04 2. " AVGE ,Hardware average enable" "Disabled,Enabled" bitfld.long 0x04 0.--1. " AVGS ,Hardware average select" "4 samples,8 samples,16 samples,32 samples" line.long 0x08 "OFS,ADC Offset Correction Register" hexmask.long.word 0x08 0.--15. 1. " OFS ,Offset error correction value" line.long 0x0C "PG,ADC Plus-Side Gain Register" hexmask.long.word 0x0C 0.--15. 1. " PG ,Plus-side gain" line.long 0x10 "MG,ADC Minus-Side Gain Register" hexmask.long.word 0x10 0.--15. 1. " MG ,Minus-side Gain" line.long 0x14 "CLPD,ADC Plus-Side General Calibration Value Register" bitfld.long 0x14 0.--5. " CLPD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x18 "CLPS,ADC Plus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLPS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x1C "CLP4,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x1C 0.--9. 1. " CLP4 ,Calibration value" line.long 0x20 "CLP3,ADC Plus-Side General Calibration Value Register" hexmask.long.word 0x20 0.--8. 1. " CLP3 ,Calibration value" line.long 0x24 "CLP2,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x24 0.--7. 1. " CLP2 ,Calibration value" line.long 0x28 "CLP1,ADC Plus-Side General Calibration Value Register" hexmask.long.byte 0x28 0.--6. 1. " CLP1 ,Calibration value" line.long 0x2C "CLP0,ADC Plus-Side General Calibration Value Register" bitfld.long 0x2C 0.--5. " CLP0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif !cpuis("MK63FR")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256VR")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R")||cpuis("MK8?FN256V*") sif cpuis("MK??FR")||cpuis("KK60FN1M0VLQ15") group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 21. " PGACHPB ,PGA chopping enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" newline bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." bitfld.long 0x00 14. " PGAOFSM ,PGA run mode" "Normal,Offset measurement" else group.long 0x50++0x03 line.long 0x00 "PGA,ADC PGA Register" bitfld.long 0x00 23. " PGAEN ,PGA enable" "Disabled,Enabled" bitfld.long 0x00 20. " PGALPB ,PGA low-power mode control" "Low,Normal" bitfld.long 0x00 16.--19. " PGAG ,PGA gain setting" "1,2,4,8,16,32,64,?..." endif endif group.long 0x54++0x1B line.long 0x00 "CLMD,ADC Minus-Side General Calibration Value Register" bitfld.long 0x00 0.--5. " CLMD ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CLMS,ADC Minus-Side General Calibration Value Register" bitfld.long 0x04 0.--5. " CLMS ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CLM4,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x08 0.--9. 1. " CLM4 ,Calibration value" line.long 0x0C "CLM3,ADC Minus-Side General Calibration Value Register" hexmask.long.word 0x0C 0.--8. 1. " CLM3 ,Calibration value" line.long 0x10 "CLM2,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x10 0.--7. 1. " CLM2 ,Calibration value" line.long 0x14 "CLM1,ADC Minus-Side General Calibration Value Register" hexmask.long.byte 0x14 0.--6. 1. " CLM1 ,Calibration value" line.long 0x18 "CLM0,ADC Minus-Side General Calibration Value Register" bitfld.long 0x18 0.--5. " CLM0 ,Calibration value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree.end tree.open "HSCMP (Comparator/6-bit DAC Converter)" base ad:0x40073000 tree "CMP 0" width 12. group.byte 0x00++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF output/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") newline sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" endif elif cpuis("MK60DN512VMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC0_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC0_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12 bit DAC1/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12-bit DAC1_OUT/CMP0_IN4,,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12-bit DAC1_OUT/CMP0_IN4,,Bandgap,6-bit DAC0" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP0_IN0,CMP0_IN1,CMP0_IN2,CMP0_IN3,12b DAC1_OUT/CMP0_IN4,VREF Out/CMP0_IN5,Bandgap,6-bit DAC0" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree "CMP 1" width 12. group.byte 0x08++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,Op-amp 0 output/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,Op-amp 0 output/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DN512VMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0SE16/CMP1_IN2,12b DAC0/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b ,,,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b ,,,Bandgap,6-bit DAC1" elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP1_IN0,CMP1_IN1,ADC0_SE16/CMP1_IN2,12b DAC0_OUT/CMP1_IN3,,VREF Out/CMP1_IN5,Bandgap,6-bit DAC1" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree "CMP 2" width 12. group.byte 0x10++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") sif cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,,Bandgap,6-bit DAC2" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,?..." endif elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,ADC0SE16/CMP2_IN2,12b DAC1/CMP2_IN3,CMP2_IN4,CMP2_IN5,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,ADC0SE16/CMP2_IN2,12b DAC1/CMP2_IN3,CMP2_IN4,CMP2_IN5,Bandgap,6-bit DAC2" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,Op-amp 1 output/CMP2_IN2,12b DAC1/CMP2_IN3,,TRIAMP1 output/CMP2_IN5,Bandgap,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,Op-amp 1 output/CMP2_IN2,12b DAC1/CMP2_IN3,,TRIAMP1 output/CMP2_IN5,Bandgap,?..." elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") newline sif cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,12b DAC1/CMP2_IN3,,CMP2_IN5,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,12b DAC1/CMP2_IN3,,CMP2_IN5,Bandgap,6-bit DAC2" else bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,6-bit DAC2" endif elif cpuis("MK60DN512VMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,12b DAC1_OUT/CMP2_IN3,,CMP2_IN5,Bandgap,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,12b DAC1_OUT/CMP2_IN3,,CMP2_IN5,Bandgap,?..." elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,ADC0SE16/CMP2_IN2,12b DAC1/CMP2_IN3,CMP2_IN4,CMP2_IN5,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,ADC0SE16/CMP2_IN2,12b DAC1/CMP2_IN3,CMP2_IN4,CMP2_IN5,Bandgap,6-bit DAC2" elif cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" elif cpuis("MK63FN1M0VLQ12R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,ADC1_SE/CMP2_IN2,,,,Bandgap,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,ADC1_SE/CMP2_IN2,,,,Bandgap,?..." elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,ADC1_SE16/CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,ADC1_SE16/CMP2_IN2,12b DAC1_OUT/CMP2_IN3,,,Bandgap,6-bit DAC2" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree "CMP 3" width 12. group.byte 0x18++0x05 line.byte 0x00 "CR0,CMP Control Register 0" bitfld.byte 0x00 4.--6. " FILTER_CNT ,Filter sample count" "Disabled,1 sample,2 samples,3 samples,4 samples,5 samples,6 samples,7 samples" bitfld.byte 0x00 0.--1. " HYSTCTR ,Comparator hard block hysteresis control" "Level 0,Level 1,Level 2,Level 3" line.byte 0x01 "CR1,CMP Control Register 1" bitfld.byte 0x01 7. " SE ,Sample enable" "Disabled,Enabled" bitfld.byte 0x01 6. " WE ,Windowing enable" "Disabled,Enabled" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x01 5. " TRIGM ,Trigger mode enable" "Disabled,Enabled" endif newline bitfld.byte 0x01 4. " PMODE ,Power mode select" "Low-speed,High-speed" bitfld.byte 0x01 3. " INV ,Comparator INVERT" "Not inverted,Inverted" bitfld.byte 0x01 2. " COS ,Comparator output select" "COUT,COUTA" newline bitfld.byte 0x01 1. " OPE ,Comparator output pin enable" "Disabled,Enabled" bitfld.byte 0x01 0. " EN ,Comparator module enable" "Disabled,Enabled" line.byte 0x02 "FPR,CMP Filter Period Register" line.byte 0x03 "SCR,CMP Status and Control Register" bitfld.byte 0x03 6. " DMAEN ,DMA enable control" "Disabled,Enabled" sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*"))||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") newline bitfld.byte 0x03 5. " SMELB ,Stop mode edge/level interrupt control" "Level,Edge" endif newline bitfld.byte 0x03 4. " IER ,Comparator interrupt enable rising" "Disabled,Enabled" bitfld.byte 0x03 3. " IEF ,Comparator interrupt enable falling" "Disabled,Enabled" eventfld.byte 0x03 2. " CFR ,Analog comparator flag rising" "Not occurred,Occurred" newline eventfld.byte 0x03 1. " CFF ,Analog comparator flag falling" "Not occurred,Occurred" rbitfld.byte 0x03 0. " COUT ,Analog comparator output" "Low,High" line.byte 0x04 "DACCR,DAC Control Register" bitfld.byte 0x04 7. " DACEN ,DAC enable" "Disabled,Enabled" newline sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "Vin1,Vin2" else bitfld.byte 0x04 6. " VRSEL ,Supply voltage reference source select" "VREF_OUT,VDD" endif newline bitfld.byte 0x04 0.--5. " VOSEL ,DAC output voltage level select" "1/64 Vin,2/64 Vin,3/64 Vin,4/64 Vin,5/64 Vin,6/64 Vin,7/64 Vin,8/64 Vin,9/64 Vin,10/64 Vin,11/64 Vin,12/64 Vin,13/64 Vin,14/64 Vin,15/64 Vin,16/64 Vin,17/64 Vin,18/64 Vin,19/64 Vin,20/64 Vin,21/64 Vin,22/64 Vin,23/64 Vin,24/64 Vin,25/64 Vin,26/64 Vin,27/64 Vin,28/64 Vin,29/64 Vin,30/64 Vin,31/64 Vin,32/64 Vin,33/64 Vin,34/64 Vin,35/64 Vin,36/64 Vin,37/64 Vin,38/64 Vin,39/64 Vin,40/64 Vin,41/64 Vin,42/64 Vin,43/64 Vin,44/64 Vin,45/64 Vin,46/64 Vin,47/64 Vin,48/64 Vin,49/64 Vin,50/64 Vin,51/64 Vin,52/64 Vin,53/64 Vin,54/64 Vin,55/64 Vin,56/64 Vin,57/64 Vin,58/64 Vin,59/64 Vin,60/64 Vin,61/64 Vin,62/64 Vin,63/64 Vin,Vin" line.byte 0x05 "MUXCR,MUX Control Register" sif !(cpuis("MK70*"))&&!cpuis("MK8?FN256V*") sif cpuis("MK60D*AB10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK40D*Z*10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 7. " PEN ,PMUX enable" "Disabled,Enabled" newline elif cpuis("MK63*F")||cpuis("MK64*F")||cpuis("MK65*F")||cpuis("MK66*F")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x05 7. " PSTM ,Pass through mode enable" "Disabled,Enabled" newline endif sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" elif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK40D*Z*10")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R") bitfld.byte 0x05 6. " PSTM ,Pass through mode enable" "Disabled,Enabled" else bitfld.byte 0x05 6. " MEN ,MMUX enable" "Disabled,Enabled" endif newline endif sif cpuis("MK84FN2M0CAU15R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,,VREF Out/IN5,Bandgap,6-bit DAC" elif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*") sif cpuis("MK30DX256VLL7*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,,Bandgap,6-bit DAC2" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,,Bandgap,6-bit DAC2" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,?..." bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP2_IN0,CMP2_IN1,,CMP2_IN3,,CMP2_IN5,Bandgap,?..." endif elif cpuis("MK70*") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP3_IN0,CMP3_IN1,CMP3_IN2,12b DAC0/CMP3_IN3,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP3_IN0,CMP3_IN1,CMP3_IN2,12b DAC0/CMP3_IN3,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R") elif cpuis("MK60DN512VMC10R") elif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMC10R") elif cpuis("KK60FN1M0VLQ15") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "CMP3_IN0,CMP3_IN1,CMP3_IN2,12b DAC0/CMP3_IN3,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "CMP3_IN0,CMP3_IN1,CMP3_IN2,12b DAC0/CMP3_IN3,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" elif cpuis("KK60DN512ZCAB10R") elif cpuis("MK63FN1M0VLQ12R") elif cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" ",CMP3_IN1,CMP3_IN2,,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" ",CMP3_IN1,CMP3_IN2,,CMP3_IN4,CMP3_IN5,Bandgap,6-bit DAC3" else newline bitfld.byte 0x05 3.--5. " PSEL ,Positive input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" bitfld.byte 0x05 0.--2. " MSEL ,Minus input MUX control" "IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7" endif width 0x0B tree.end tree.end tree.open "DAC (12-bit Digital-to-Analog Converter)" tree "DAC 0" base ad:0x400cc000 width 8. sif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") group.byte 0x00++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x00 line.byte 0x00 "DAT1L,DAC Data Low Register" group.byte 0x4++0x00 line.byte 0x00 "DAT2L,DAC Data Low Register" group.byte 0x6++0x00 line.byte 0x00 "DAT3L,DAC Data Low Register" group.byte 0x8++0x00 line.byte 0x00 "DAT4L,DAC Data Low Register" group.byte 0xA++0x00 line.byte 0x00 "DAT5L,DAC Data Low Register" group.byte 0xC++0x00 line.byte 0x00 "DAT6L,DAC Data Low Register" group.byte 0xE++0x00 line.byte 0x00 "DAT7L,DAC Data Low Register" group.byte 0x10++0x00 line.byte 0x00 "DAT8L,DAC Data Low Register" group.byte 0x12++0x00 line.byte 0x00 "DAT9L,DAC Data Low Register" group.byte 0x14++0x00 line.byte 0x00 "DAT10L,DAC Data Low Register" group.byte 0x16++0x00 line.byte 0x00 "DAT11L,DAC Data Low Register" group.byte 0x18++0x00 line.byte 0x00 "DAT12L,DAC Data Low Register" group.byte 0x1A++0x00 line.byte 0x00 "DAT13L,DAC Data Low Register" group.byte 0x1C++0x00 line.byte 0x00 "DAT14L,DAC Data Low Register" group.byte 0x1E++0x00 line.byte 0x00 "DAT15L,DAC Data Low Register" else group.byte 0x0++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAT1L,DAC Data Low Register" line.byte 0x01 "DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAT2L,DAC Data Low Register" line.byte 0x01 "DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAT3L,DAC Data Low Register" line.byte 0x01 "DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAT4L,DAC Data Low Register" line.byte 0x01 "DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAT5L,DAC Data Low Register" line.byte 0x01 "DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAT6L,DAC Data Low Register" line.byte 0x01 "DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAT7L,DAC Data Low Register" line.byte 0x01 "DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAT8L,DAC Data Low Register" line.byte 0x01 "DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAT9L,DAC Data Low Register" line.byte 0x01 "DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAT10L,DAC Data Low Register" line.byte 0x01 "DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAT11L,DAC Data Low Register" line.byte 0x01 "DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAT12L,DAC Data Low Register" line.byte 0x01 "DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAT13L,DAC Data Low Register" line.byte 0x01 "DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAT14L,DAC Data Low Register" line.byte 0x01 "DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAT15L,DAC Data Low Register" line.byte 0x01 "DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" endif newline width 4. group.byte 0x20++0x01 line.byte 0x00 "SR,DAC Status Register" bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer reached the watermark level" "Not reached,Reached" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer is zero" "Not zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag (pointer not equal/equal to the DACBFUP)" "Not equal,Equal" line.byte 0x01 "C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "VREF_OUT,VDDA" bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-Power,Low-Power" bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" sif cpuis("MK22FN128*")||cpuis("MK22FN256*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK70*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") if (((per.b(ad:0x400cc000+0x22))&0x06)==0x06) group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif elif cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12R") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,?..." bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" elif cpuis("MK02*") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif group.byte 0x23++0x00 line.byte 0x00 "C2,DAC Control Register 2" sif cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FX512AVLH12R") bitfld.byte 0x00 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x00 0. " DACBFUP ,DAC buffer upper limit" "0,1" else bitfld.byte 0x00 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "DAC 1" base ad:0x400cd000 width 8. sif cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") group.byte 0x00++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x00 line.byte 0x00 "DAT1L,DAC Data Low Register" group.byte 0x4++0x00 line.byte 0x00 "DAT2L,DAC Data Low Register" group.byte 0x6++0x00 line.byte 0x00 "DAT3L,DAC Data Low Register" group.byte 0x8++0x00 line.byte 0x00 "DAT4L,DAC Data Low Register" group.byte 0xA++0x00 line.byte 0x00 "DAT5L,DAC Data Low Register" group.byte 0xC++0x00 line.byte 0x00 "DAT6L,DAC Data Low Register" group.byte 0xE++0x00 line.byte 0x00 "DAT7L,DAC Data Low Register" group.byte 0x10++0x00 line.byte 0x00 "DAT8L,DAC Data Low Register" group.byte 0x12++0x00 line.byte 0x00 "DAT9L,DAC Data Low Register" group.byte 0x14++0x00 line.byte 0x00 "DAT10L,DAC Data Low Register" group.byte 0x16++0x00 line.byte 0x00 "DAT11L,DAC Data Low Register" group.byte 0x18++0x00 line.byte 0x00 "DAT12L,DAC Data Low Register" group.byte 0x1A++0x00 line.byte 0x00 "DAT13L,DAC Data Low Register" group.byte 0x1C++0x00 line.byte 0x00 "DAT14L,DAC Data Low Register" group.byte 0x1E++0x00 line.byte 0x00 "DAT15L,DAC Data Low Register" else group.byte 0x0++0x01 line.byte 0x00 "DAT0L,DAC Data Low Register" line.byte 0x01 "DAT0H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x2++0x01 line.byte 0x00 "DAT1L,DAC Data Low Register" line.byte 0x01 "DAT1H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x4++0x01 line.byte 0x00 "DAT2L,DAC Data Low Register" line.byte 0x01 "DAT2H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x6++0x01 line.byte 0x00 "DAT3L,DAC Data Low Register" line.byte 0x01 "DAT3H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x8++0x01 line.byte 0x00 "DAT4L,DAC Data Low Register" line.byte 0x01 "DAT4H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xA++0x01 line.byte 0x00 "DAT5L,DAC Data Low Register" line.byte 0x01 "DAT5H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xC++0x01 line.byte 0x00 "DAT6L,DAC Data Low Register" line.byte 0x01 "DAT6H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0xE++0x01 line.byte 0x00 "DAT7L,DAC Data Low Register" line.byte 0x01 "DAT7H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x10++0x01 line.byte 0x00 "DAT8L,DAC Data Low Register" line.byte 0x01 "DAT8H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x12++0x01 line.byte 0x00 "DAT9L,DAC Data Low Register" line.byte 0x01 "DAT9H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x14++0x01 line.byte 0x00 "DAT10L,DAC Data Low Register" line.byte 0x01 "DAT10H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x16++0x01 line.byte 0x00 "DAT11L,DAC Data Low Register" line.byte 0x01 "DAT11H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x18++0x01 line.byte 0x00 "DAT12L,DAC Data Low Register" line.byte 0x01 "DAT12H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1A++0x01 line.byte 0x00 "DAT13L,DAC Data Low Register" line.byte 0x01 "DAT13H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1C++0x01 line.byte 0x00 "DAT14L,DAC Data Low Register" line.byte 0x01 "DAT14H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" group.byte 0x1E++0x01 line.byte 0x00 "DAT15L,DAC Data Low Register" line.byte 0x01 "DAT15H,DAC Data High Register" hexmask.byte 0x01 0.--3. 1. " DATA[11:8] ,Data bits" endif newline width 4. group.byte 0x20++0x01 line.byte 0x00 "SR,DAC Status Register" bitfld.byte 0x00 2. " DACBFWMF ,DAC buffer reached the watermark level" "Not reached,Reached" bitfld.byte 0x00 1. " DACBFRPTF ,DAC buffer read pointer is zero" "Not zero,Zero" bitfld.byte 0x00 0. " DACBFRPBF ,DAC buffer read pointer bottom position flag (pointer not equal/equal to the DACBFUP)" "Not equal,Equal" line.byte 0x01 "C0,DAC Control Register" bitfld.byte 0x01 7. " DACEN ,DAC enable" "Disabled,Enabled" bitfld.byte 0x01 6. " DACRFS ,DAC reference select" "VREF_OUT,VDDA" bitfld.byte 0x01 5. " DACTRGSEL ,DAC trigger select" "Hardware,Software" bitfld.byte 0x01 4. " DACSWTRG ,DAC software trigger" "Not valid,Valid" newline bitfld.byte 0x01 3. " LPEN ,DAC low power control" "High-Power,Low-Power" bitfld.byte 0x01 2. " DACBWIEN ,DAC buffer watermark interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " DACBTIEN ,DAC buffer read pointer top flag interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " DACBBIEN ,DAC buffer read pointer bottom flag interrupt enable" "Disabled,Enabled" sif cpuis("MK22FN128*")||cpuis("MK22FN256*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK70*")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK60FN1M0VLQ15") if (((per.b(ad:0x400cd000+0x22))&0x06)==0x06) group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark (Quantity of data remaining in FIFO that will set watermark status)" "2 or less,Max/4 or less,Max/2 or less,Max-2 or less" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif elif cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLH12R") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,?..." bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" elif cpuis("MK02*") group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,FIFO" bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" else group.byte 0x22++0x00 line.byte 0x00 "C1,DAC Control Register 1" bitfld.byte 0x00 7. " DMAEN ,DMA enable select" "Disabled,Enabled" bitfld.byte 0x00 3.--4. " DACBFWM ,DAC buffer watermark select" "1 word,2 words,3 words,4 words" bitfld.byte 0x00 1.--2. " DACBFMD ,DAC buffer work mode select" "Normal,Swing,One-Time scan,?..." bitfld.byte 0x00 0. " DACBFEN ,DAC buffer enable" "Disabled,Enabled" endif group.byte 0x23++0x00 line.byte 0x00 "C2,DAC Control Register 2" sif cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FX512AVLH12R") bitfld.byte 0x00 4. " DACBFRP ,DAC buffer read pointer" "0,1" bitfld.byte 0x00 0. " DACBFUP ,DAC buffer upper limit" "0,1" else bitfld.byte 0x00 4.--7. " DACBFRP ,DAC buffer read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DACBFUP ,DAC buffer upper limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree.end tree "VREFV1 (Voltage Reference)" base ad:0x40074000 width 10. group.byte 0x00++0x01 line.byte 0x00 "VREF_TRM,VREF Trim Register" bitfld.byte 0x00 0.--5. " TRIM ,Trim bits" "Min,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Max" line.byte 0x01 "SC,VREF Status and Control Register" bitfld.byte 0x01 7. " VREFEN ,Internal voltage reference enable" "Disabled,Enabled" bitfld.byte 0x01 6. " REGEN ,Regulator enable" "Disabled,Enabled" rbitfld.byte 0x01 2. " VREFST ,Internal voltage reference has settled" "Not ready,Ready" sif (cpuis("MK70*")) textline " " bitfld.byte 0x01 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,High-power,?..." else textline " " bitfld.byte 0x01 0.--1. " MODE_LV ,Buffer mode selection" "Bandgap,,Tight-regulation,?..." endif width 0x0B tree.end tree.end tree.open "Timers" tree "PDB (Programmable Delay Block)" base ad:0x40036000 width 6. group.long 0x00++0x07 line.long 0x00 "SC,Status and Control Register" bitfld.long 0x00 18.--19. " LDMOD ,Load mode select" "Immediately after 1 to LDOK,PDB reach MOD,Trigger input detected,Trigger input detected/PDB reach MOD" newline bitfld.long 0x00 17. " PDBEIE ,PDB sequence error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 16. " SWTRIG ,Software trigger" "Not triggered,Triggered" bitfld.long 0x00 15. " DMAEN ,DMA enable" "Disabled,Enabled" newline bitfld.long 0x00 12.--14. " PRESCALER ,Prescaler divider select (of multiplication factor)" "/1,/2,/4,/8,/16,/32,/64,/128" sif cpuis("MK11D*MC*") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,,PIT Ch_0 Out.,PIT Ch_1 Out.,PIT Ch_2 Out.,PIT Ch_3 Out.,FTM_0,FTM_1,FTM_2,,RTC Alarm,RTC Sec.,LPTMR Out.,Software" elif cpuis("MK24FN256VDC12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,,PIT Ch 0,PIT Ch 1,PIT Ch 2,PIT Ch 3,FTM0,FTM1,FTM2,FTM3,RTC Alarm,RTC Seconds,LPTMR,Software" elif cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,CMP 2,PIT Ch 0,PIT Ch 1,PIT Ch 2,PIT Ch 3,FTM0,FTM1,FTM2,FTM3,RTC Alarm,RTC Seconds,LPTMR,Software" elif cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10*")||cpuis("MK10DN512ZVMD10*")||cpuis("MK10DN512ZVMC10*")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,CMP 2,PIT Ch 0,PIT Ch 1,PIT Ch 2,PIT Ch 3,FTM0,FTM1,FTM2,,RTC Alarm,RTC Seconds,LPTMR,Software" elif cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "PDB0_EXTRG,CMP0,CMP1,,PIT0,PIT1,PIT2,PIT3,FTM0,FTM1,,,RTC Alarm,RTC Seconds,LPTMR,Software" elif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,CMP 2,PIT Ch_0 Out,PIT Ch_1 Out,PIT Ch_2 Out,PIT Ch_3 Out,FTM_0,FTM_1,FTM_2,,RTC Alarm,RTC Sec.,LPTMR Out.,Software" elif cpuis("MK02*") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP 0,CMP 1,,PIT Ch_0 Out.,PIT Ch_1 Out.,PIT Ch_2 Out.,PIT Ch_3 Out.,FTM_0,FTM_1,FTM_2,,,,LPTMR Out.,?..." elif cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512VLL12") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP0,CMP1,,PIT Ch_0 Out,PIT Ch_1 Out,PIT Ch_2 Out,PIT Ch_3 Out,FTM0,FTM1,FTM2,FTM3,RTC Alarm,RTC Seconds,LPTMR Out,Software trigger" elif cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP0,CMP1,CMP2,PIT Ch_0 Out,PIT Ch_1 Out,PIT Ch_2 Out,PIT Ch_3 Out,FTM0,FTM1,FTM2,,RTC Alarm,RTC Seconds,LPTMR Out,Software trigger" elif cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FX512AVMD12")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "External,CMP0,CMP1,CMP2,PIT Ch_0 Out,PIT Ch_1 Out,PIT Ch_2 Out,PIT Ch_3 Out,FTM0,FTM1,FTM2,FTM3,RTC Alarm,RTC Seconds,LPTMR Out,Software trigger" else bitfld.long 0x00 8.--11. " TRGSEL ,Trigger input source select" "Trigger-In 0,Trigger-In 1,Trigger-In 2,Trigger-In 3,Trigger-In 4,Trigger-In 5,Trigger-In 6,Trigger-In 7,Trigger-In 8,Trigger-In 9,Trigger-In 10,Trigger-In 11,Trigger-In 12,Trigger-In 13,Trigger-In 14,Software trigger" endif bitfld.long 0x00 7. " PDBEN ,PDB enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " PDBIF ,PDB interrupt flag" "No interrupt,Interrupt" bitfld.long 0x00 5. " PDBIE ,PDB interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " MULT ,Multiplication factor select for prescaler" "1,10,20,40" newline bitfld.long 0x00 1. " CONT ,Continuous mode enable" "One-Shot,Continuous" bitfld.long 0x00 0. " LDOK ,Load OK" "Not updated,Updated" line.long 0x04 "MOD,Modulus Register" hexmask.long.word 0x04 0.--15. 1. " MOD ,PDB modulus" rgroup.long 0x08++0x03 line.long 0x00 "CNT,Counter Register" hexmask.long.word 0x00 0.--15. 1. " CNT ,PDB counter" group.long 0x0C++0x03 line.long 0x00 "IDLY,Interrupt Delay Register" hexmask.long.word 0x00 0.--15. 1. " IDLY ,PDB interrupt delay" width 10. tree "Channel 0" group.long 0x10++0x0F line.long 0x00 "CH0_C1,Channel 0 Control Register 1" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline endif bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline sif cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " [6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " [5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " [4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " [3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " [2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline endif bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " [0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH0_S,Channel 0 Status Register" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " [4] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " [0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flag" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH0_DLY0,Channel 0 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH0_DLY1,Channel 0 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" tree.end tree "Channel 1" group.long 0x38++0x0F line.long 0x00 "CH1_C1,Channel 1 Control Register 1" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline endif bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline sif cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " [6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " [5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " [4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " [3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " [2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline endif bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " [0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH1_S,Channel 1 Status Register" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " [4] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " [0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flag" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH1_DLY0,Channel 1 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH1_DLY1,Channel 1 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" tree.end tree "Channel 2" group.long 0x60++0x0F line.long 0x00 "CH2_C1,Channel 2 Control Register 1" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline endif bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline sif cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " [6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " [5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " [4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " [3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " [2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline endif bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " [0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH2_S,Channel 2 Status Register" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " [4] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " [0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flag" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH2_DLY0,Channel 2 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH2_DLY1,Channel 2 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" tree.end tree "Channel 3" group.long 0x88++0x0F line.long 0x00 "CH3_C1,Channel 3 Control Register 1" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 23. " BB[7] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 22. " [6] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 21. " [5] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 20. " [4] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline bitfld.long 0x00 19. " [3] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 18. " [2] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline endif bitfld.long 0x00 17. " BB[1] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" bitfld.long 0x00 16. " [0] ,PDB channel pre-trigger back-to-back operation enable" "Disabled,Enabled" newline sif cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 15. " TOS[7] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 14. " [6] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 13. " [5] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 12. " [4] ,PDB channel pre-trigger output select" "Not selected,Selected" newline bitfld.long 0x00 11. " [3] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 10. " [2] ,PDB channel pre-trigger output select" "Not selected,Selected" newline endif bitfld.long 0x00 9. " TOS[1] ,PDB channel pre-trigger output select" "Not selected,Selected" bitfld.long 0x00 8. " [0] ,PDB channel pre-trigger output select" "Not selected,Selected" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x00 7. " EN[7] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB channel pre-trigger enable" "Disabled,Enabled" newline endif bitfld.long 0x00 1. " EN[1] ,PDB channel pre-trigger enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB channel pre-trigger enable" "Disabled,Enabled" line.long 0x04 "CH3_S,Channel 3 Status Register" sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 23. " CF[7] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 22. " [6] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 21. " [5] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 20. " [4] ,PDB channel flag" "Not occurred,Occurred" newline bitfld.long 0x04 19. " [3] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 18. " [2] ,PDB channel flag" "Not occurred,Occurred" newline endif bitfld.long 0x04 17. " CF[1] ,PDB channel flag" "Not occurred,Occurred" bitfld.long 0x04 16. " [0] ,PDB channel flag" "Not occurred,Occurred" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLQ12R") bitfld.long 0x04 7. " ERR[7] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 6. " [6] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 5. " [5] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 4. " [4] ,PDB channel sequence error flag" "No error,Error" newline bitfld.long 0x04 3. " [3] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 2. " [2] ,PDB channel sequence error flag" "No error,Error" newline endif bitfld.long 0x04 1. " ERR[1] ,PDB channel sequence error flag" "No error,Error" bitfld.long 0x04 0. " [0] ,PDB channel sequence error flag" "No error,Error" line.long 0x08 "CH3_DLY0,Channel 3 Delay 0 Register" hexmask.long.word 0x08 0.--15. 1. " DLY ,PDB channel delay" line.long 0x0C "CH3_DLY1,Channel 3 Delay 1 Register" hexmask.long.word 0x0C 0.--15. 1. " DLY ,PDB channel delay" tree.end newline sif cpuis("MK11D*MC*")||cpuis("MK*7")||cpuis("MK?1D*5")||cpuis("MK?2D*5")||cpuis("MK02*")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK11DN512VLK5*")||cpuis("MK11DN512AVLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK24FN256VDC12") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" elif cpuis("MK11D*LK*") hgroup.long 0x150++0x03 hide.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" hgroup.long 0x154++0x03 hide.long 0x00 "DACINT0,DAC Interval 0 Register" elif !cpuis("MK*DX*5")&&!cpuis("MK*DN*5") group.long 0x150++0x07 line.long 0x00 "DACINTC0,DAC Interval Trigger 0 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT0,DAC Interval 0 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" group.long 0x158++0x07 line.long 0x00 "DACINTC1,DAC Interval Trigger 1 Control Register" bitfld.long 0x00 1. " EXT ,DAC external trigger input enable" "Disabled,Enabled" bitfld.long 0x00 0. " TOE ,DAC interval trigger enable" "Disabled,Enabled" line.long 0x04 "DACINT1,DAC Interval 1 Register" hexmask.long.word 0x04 0.--15. 1. " INT ,DAC interval" endif group.long 0x190++0x03 line.long 0x00 "POEN,Pulse-Out 0 Enable Register" bitfld.long 0x00 3. " POEN[3] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,PDB pulse out enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,PDB pulse out enable" "Disabled,Enabled" sif cpuis("MK02*")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" else group.long 0x194++0x03 line.long 0x00 "PO0DLY,Pulse-Out 0 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x198++0x03 line.long 0x00 "PO1DLY,Pulse-Out 1 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x19C++0x03 line.long 0x00 "PO2DLY,Pulse-Out 2 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" group.long 0x1A0++0x03 line.long 0x00 "PO3DLY,Pulse-Out 3 Delay Register" hexmask.long.word 0x00 16.--31. 1. " DLY1 ,PDB pulse-out delay 1" hexmask.long.word 0x00 0.--15. 1. " DLY2 ,PDB pulse-out delay 2" endif width 0x0B tree.end tree.open "FTM (FlexTimer)" tree "FTM 0" base ad:0x40038000 width 10. sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM0 Status And Control Register" in else if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,FTM0 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,FTM0 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "CNT,FTM0 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM0 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK11D*") sif (!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")) if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0xC++0x07 line.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long 0xC++0x07 line.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM0 Channel 0 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x14++0x07 line.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x14++0x07 line.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM0 Channel 1 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x1C++0x07 line.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C2V,FTM0 Channel 2 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x24++0x07 line.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long 0x24++0x07 line.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C3V,FTM0 Channel 3 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x2C++0x07 line.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C4V,FTM0 Channel 4 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x34++0x07 line.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long 0x34++0x07 line.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C5V,FTM0 Channel 5 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x3C++0x07 line.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C6V,FTM0 Channel 6 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x44++0x07 line.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long 0x44++0x07 line.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C7V,FTM0 Channel 7 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif else if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif endif elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12") if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK40D*Z*10") if (((per.l(ad:0x40038000+0x54))&0x4)==0x4) if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x1C))&0x30)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x1C))&0x30)==0x10) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x24))&0x30)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x24))&0x30)==0x10) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x2C))&0x30)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x2C))&0x30)==0x10) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x34))&0x30)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x34))&0x30)==0x10) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x3C))&0x30)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x3C))&0x30)==0x10) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x44))&0x30)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x44))&0x30)==0x10) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x1C))&0x30)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x1C))&0x30)==0x10) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x24))&0x30)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x24))&0x30)==0x10) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x400)==0x400)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x400)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x2C))&0x30)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x2C))&0x30)==0x10) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x34))&0x30)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x34))&0x30)==0x10) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x3C))&0x30)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x3C))&0x30)==0x10) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x40038000)&0x20)==0x00) if (((per.l(ad:0x40038000+0x44))&0x30)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x44))&0x30)==0x10) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x40038000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40038000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x40038000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM0 Channel 0 Status And Control Register" in group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM0 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM0 Channel 1 Status And Control Register" in group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM0 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM0 Channel 2 Status And Control Register" in group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM0 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM0 Channel 3 Status And Control Register" in group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM0 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM0 Channel 4 Status And Control Register" in group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM0 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM0 Channel 5 Status And Control Register" in group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM0 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM0 Channel 6 Status And Control Register" in group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM0 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM0 Channel 7 Status And Control Register" in group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM0 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else group.long 0x0C++0x3F line.long 0x0 "C0SC,FTM0 Channel 0 Status And Control Register" rbitfld.long 0x0 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x0 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x0 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x0 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x0 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x0+0x4) "C0V,FTM0 Channel 0 Value Register" hexmask.long.word (0x0+0x4) 0.--15. 1. " VAL ,Channel 0 value" line.long 0x8 "C1SC,FTM0 Channel 1 Status And Control Register" rbitfld.long 0x8 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x8 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x8 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x8 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x8 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x8+0x4) "C1V,FTM0 Channel 1 Value Register" hexmask.long.word (0x8+0x4) 0.--15. 1. " VAL ,Channel 1 value" line.long 0x10 "C2SC,FTM0 Channel 2 Status And Control Register" rbitfld.long 0x10 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x10 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" bitfld.long 0x10 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x10 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x10+0x4) "C2V,FTM0 Channel 2 Value Register" hexmask.long.word (0x10+0x4) 0.--15. 1. " VAL ,Channel 2 value" line.long 0x18 "C3SC,FTM0 Channel 3 Status And Control Register" rbitfld.long 0x18 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x18 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x18 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" bitfld.long 0x18 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x18 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x18+0x4) "C3V,FTM0 Channel 3 Value Register" hexmask.long.word (0x18+0x4) 0.--15. 1. " VAL ,Channel 3 value" line.long 0x20 "C4SC,FTM0 Channel 4 Status And Control Register" rbitfld.long 0x20 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x20 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x20 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" bitfld.long 0x20 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x20 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x20+0x4) "C4V,FTM0 Channel 4 Value Register" hexmask.long.word (0x20+0x4) 0.--15. 1. " VAL ,Channel 4 value" line.long 0x28 "C5SC,FTM0 Channel 5 Status And Control Register" rbitfld.long 0x28 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x28 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x28 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" bitfld.long 0x28 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x28 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x28+0x4) "C5V,FTM0 Channel 5 Value Register" hexmask.long.word (0x28+0x4) 0.--15. 1. " VAL ,Channel 5 value" line.long 0x30 "C6SC,FTM0 Channel 6 Status And Control Register" rbitfld.long 0x30 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x30 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x30 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" bitfld.long 0x30 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x30 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x30+0x4) "C6V,FTM0 Channel 6 Value Register" hexmask.long.word (0x30+0x4) 0.--15. 1. " VAL ,Channel 6 value" line.long 0x38 "C7SC,FTM0 Channel 7 Status And Control Register" rbitfld.long 0x38 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x38 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x38 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" bitfld.long 0x38 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x38 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x38+0x4) "C7V,FTM0 Channel 7 Value Register" hexmask.long.word (0x38+0x4) 0.--15. 1. " VAL ,Channel 7 value" endif newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM0 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM0 counter" sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") group.long 0x50++0x03 line.long 0x00 "STATUS,FTM0 Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM0 Capture And Compare Status Register" in endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif else group.long 0x54++0x03 line.long 0x00 "MODE,FTM0 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM0 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" newline line.long 0x04 "OUTINIT,FTM0 Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" newline line.long 0x08 "OUTMASK,FTM0 Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" newline sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM0 Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM0 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM0 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM0 External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM0 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM0 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,FTM0 Fault Mode Status Register" in else group.long 0x74++0x03 line.long 0x00 "FMS,FTM0 Fault Mode Status Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline else bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline endif bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" endif endif group.long 0x78++0x03 line.long 0x00 "FILTER,FTM0 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM0 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN1M0VMC10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*"))||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40038000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK70*") elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else endif else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM0 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM0 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM0 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40038000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM0 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" newline bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,FTM0 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM0 Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM0 Software Output Control Register" bitfld.long 0x08 15. " CH7OCV ,Channel 7 Software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM0 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SE ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SE ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SE ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SE ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SE ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SE ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM 1" base ad:0x40039000 width 10. sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM1 Status And Control Register" in else if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,FTM1 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,FTM1 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "CNT,FTM1 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM1 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK11D*") sif (!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")) if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0xC++0x07 line.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long 0xC++0x07 line.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM1 Channel 0 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x14++0x07 line.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x14++0x07 line.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM1 Channel 1 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif else if (((per.l(ad:0x40039000+0x54))&0x4)==0x4) if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif endif elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12") if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK40D*Z*10") if (((per.l(ad:0x40039000+0x54))&0x4)==0x4) if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) if (((per.l(ad:0x40039000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) if (((per.l(ad:0x40039000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) if (((per.l(ad:0x40039000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSb/MSA ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00) if ((per.l(ad:0x40039000)&0x20)==0x00) if (((per.l(ad:0x40039000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x40039000+0x64))&0x4)==0x4)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x00)&&((per.l(ad:0x40039000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x40039000+0x64))&0x4)==0x00)&&(((per.l(ad:0x40039000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSb/MSA ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM1 Channel 0 Status And Control Register" in group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM1 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM1 Channel 1 Status And Control Register" in group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM1 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x0c++0x0F line.long 0x0 "C0SC,FTM1 Channel 0 Status And Control Register" rbitfld.long 0x0 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x0 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x0 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x0 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x0 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x0+0x4) "C0V,FTM1 Channel 0 Value Register" hexmask.long.word (0x0+0x4) 0.--15. 1. " VAL ,Channel 0 value" line.long 0x8 "C1SC,FTM1 Channel 1 Status And Control Register" rbitfld.long 0x8 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x8 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x8 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x8 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x8 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x8+0x4) "C1V,FTM1 Channel 1 Value Register" hexmask.long.word (0x8+0x4) 0.--15. 1. " VAL ,Channel 1 value" endif newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM1 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM1 counter" sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") group.long 0x50++0x03 line.long 0x00 "STATUS,FTM1 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM1 Capture And Compare Status Register" in endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif else group.long 0x54++0x03 line.long 0x00 "MODE,FTM1 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM1 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" newline line.long 0x04 "OUTINIT,FTM1 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" newline line.long 0x08 "OUTMASK,FTM1 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" newline sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM1 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM1 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM1 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM1 External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM1 Channels Polarity Register" bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM1 Channels Polarity Register" bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,FTM1 Fault Mode Status Register" in else group.long 0x74++0x03 line.long 0x00 "FMS,FTM1 Fault Mode Status Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline else bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline endif bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" endif endif group.long 0x78++0x03 line.long 0x00 "FILTER,FTM1 Input Capture Filter Control Register" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM1 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN1M0VMC10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*"))||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40039000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK70*") if (((per.l(ad:0x40039000+0x54))&0x4)==0x4) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.l(ad:0x40039000+0x54))&0x4)==0x4) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif else if (((per.l(ad:0x40039000+0x54))&0x4)==0x4) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif endif else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM1 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM1 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM1 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x40039000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM1 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,FTM1 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM1 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM1 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM1 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM 2" base ad:0x400B8000 width 10. sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM2 Status And Control Register" in else if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,FTM2 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,FTM2 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "CNT,FTM2 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM2 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK11D*") sif (!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")) if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0xC++0x07 line.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long 0xC++0x07 line.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM2 Channel 0 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x14++0x07 line.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x14++0x07 line.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM2 Channel 1 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif else if (((per.l(ad:0x400B8000+0x54))&0x4)==0x4) if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif endif elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12") if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK40D*Z*10") if (((per.l(ad:0x400B8000+0x54))&0x4)==0x4) if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) if (((per.l(ad:0x400B8000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) if (((per.l(ad:0x400B8000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) if (((per.l(ad:0x400B8000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSb/MSA ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B8000)&0x20)==0x00) if (((per.l(ad:0x400B8000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B8000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B8000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B8000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSb/MSA ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM2 Channel 0 Status And Control Register" in group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM2 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM2 Channel 1 Status And Control Register" in group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM2 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x0c++0x0F line.long 0x0 "C0SC,FTM2 Channel 0 Status And Control Register" rbitfld.long 0x0 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x0 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x0 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x0 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x0 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x0+0x4) "C0V,FTM2 Channel 0 Value Register" hexmask.long.word (0x0+0x4) 0.--15. 1. " VAL ,Channel 0 value" line.long 0x8 "C1SC,FTM2 Channel 1 Status And Control Register" rbitfld.long 0x8 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x8 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x8 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x8 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x8 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x8+0x4) "C1V,FTM2 Channel 1 Value Register" hexmask.long.word (0x8+0x4) 0.--15. 1. " VAL ,Channel 1 value" endif newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM2 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM2 counter" sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") group.long 0x50++0x03 line.long 0x00 "STATUS,FTM2 Capture And Compare Status Register" bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM2 Capture And Compare Status Register" in endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif else group.long 0x54++0x03 line.long 0x00 "MODE,FTM2 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM2 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" newline line.long 0x04 "OUTINIT,FTM2 Initial State For Channels Output Register" bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" newline line.long 0x08 "OUTMASK,FTM2 Output Mask Register" bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" newline sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM2 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM2 Function For Linked Channels Register" rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM2 Function For Linked Channels Register" bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x400B8000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM2 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM2 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM2 External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline if ((per.l(ad:0x400B8000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM2 Channels Polarity Register" bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM2 Channels Polarity Register" bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,FTM2 Fault Mode Status Register" in else group.long 0x74++0x03 line.long 0x00 "FMS,FTM2 Fault Mode Status Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" newline bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline else bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline endif bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" endif endif group.long 0x78++0x03 line.long 0x00 "FILTER,FTM2 Input Capture Filter Control Register" bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM2 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN1M0VMC10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*"))||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x400B8000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK70*") if (((per.l(ad:0x400B8000+0x54))&0x4)==0x4) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.l(ad:0x400B8000+0x54))&0x4)==0x4) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif else endif else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM2 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM2 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM2 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x400B8000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM2 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,FTM2 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM2 Inverting Control Register" bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM2 Software Output Control Register" bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM2 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree "FTM 3" base ad:0x400B9000 width 10. sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x00++0x03 hide.long 0x00 "SC,FTM3 Status And Control Register" in else if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x00++0x03 line.long 0x00 "SC,FTM3 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline bitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" bitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x00++0x03 line.long 0x00 "SC,FTM3 Status And Control Register" bitfld.long 0x00 7. " TOF ,Timer overflow flag" "No overflow,Overflow" bitfld.long 0x00 6. " TOIE ,Timer overflow interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5. " CPWMS ,Center-aligned PWM select" "Up counting,Up-Down counting" newline rbitfld.long 0x00 3.--4. " CLKS ,Clock source selection" "No clk,System,Fixed frequency,Ext clk" rbitfld.long 0x00 0.--2. " PS ,Prescaler factor selection" "/1,/2,/4,/8,/16,/32,/64,/128" endif endif group.long 0x04++0x07 line.long 0x00 "CNT,FTM3 Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNT ,Counter value" line.long 0x04 "MOD,FTM3 Modulo register" hexmask.long.word 0x04 0.--15. 1. " MOD ,Modulo value" newline sif cpuis("MK11D*") sif (!cpuis("MK11DN512AVLK5*")&&!cpuis("MK11DN512VLK5*")) if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0xC++0x07 line.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" else group.long 0xC++0x07 line.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C0V,FTM3 Channel 0 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 0 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x14++0x07 line.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" else group.long 0x14++0x07 line.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C1V,FTM3 Channel 1 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 1 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x1C++0x07 line.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C2V,FTM3 Channel 2 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 2 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x24++0x07 line.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" else group.long 0x24++0x07 line.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C3V,FTM3 Channel 3 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 3 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x2C++0x07 line.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C4V,FTM3 Channel 4 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 4 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x34++0x07 line.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" else group.long 0x34++0x07 line.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C5V,FTM3 Channel 5 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 5 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x3C++0x07 line.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C6V,FTM3 Channel 6 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 6 value" endif if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x44++0x07 line.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" else group.long 0x44++0x07 line.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x00 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA enable" "Disabled,Enabled" line.long 0x04 "C7V,FTM3 Channel 7 value register" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel 7 value" endif else if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif endif elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12") if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline bitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM,Input capture/On rising Edge,Input capture/On falling edge,Input capture/On rising or falling edge,None/Pin not used for FTM,Output compare/Toggle on match,Output compare/clear on match,Output compare/Set on match,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses,None/Pin not used for FTM,Edge-aligned PWM/Low-true pulses,Edge-aligned PWM/High-true pulses,Edge-aligned PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Pin not used for FTM pulses,Center-Aligned/Low-true pulses,Center-Aligned/High-true pulses,Center-Aligned/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,Combine PWM/Low-true pulses,Combine PWM/High-true pulses,Combine PWM/Low-true pulses" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" newline rbitfld.long 0x00 2.--3. " ELS ,Channel edge and level selection (Channel Port Enable/Detected Edges)" "None/Channel disabled,Rising edge,Falling edge,Raising and falling" bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" eventfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 2.--5. " MS/ELS ,Channel mode edge and level selection (Mode/Configuration)" "None/Channel disabled,?..." newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK40D*Z*10") if (((per.l(ad:0x400B9000+0x54))&0x4)==0x4) if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x1C))&0x30)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x1C))&0x30)==0x10) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x24))&0x30)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x24))&0x30)==0x10) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x2C))&0x30)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x2C))&0x30)==0x10) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x34))&0x30)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x34))&0x30)==0x10) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x3C))&0x30)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x3C))&0x30)==0x10) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x44))&0x30)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x44))&0x30)==0x10) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Combine,Combine,Combine,Combine" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" bitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0xC))&0x30)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0xC))&0x30)==0x10) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 0 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0xC++0x07 line.long 0x00 "C0SC,Channel 0 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C0V,Channel 0 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x14))&0x30)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x14))&0x30)==0x10) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x4)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 1 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1)==0x1) group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x14++0x07 line.long 0x00 "C1SC,Channel 1 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C1V,Channel 1 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x1C))&0x30)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x1C))&0x30)==0x10) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 2 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x1C++0x07 line.long 0x00 "C2SC,Channel 2 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C2V,Channel 2 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x24))&0x30)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x24))&0x30)==0x10) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x400)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 3 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x400)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x100)==0x100) group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x24++0x07 line.long 0x00 "C3SC,Channel 3 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C3V,Channel 3 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x2C))&0x30)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x2C))&0x30)==0x10) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 4 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x2C++0x07 line.long 0x00 "C4SC,Channel 4 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C4V,Channel 4 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x34))&0x30)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x34))&0x30)==0x10) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x40000)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 5 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x40000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x10000)==0x10000) group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x34++0x07 line.long 0x00 "C5SC,Channel 5 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C5V,Channel 5 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x3C))&0x30)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x3C))&0x30)==0x10) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 6 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x3C++0x07 line.long 0x00 "C6SC,Channel 6 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C6V,Channel 6 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif if (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00) if ((per.l(ad:0x400B9000)&0x20)==0x00) if (((per.l(ad:0x400B9000+0x44))&0x30)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x44))&0x30)==0x10) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Toggle Out,Clear Out,Set Out" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Input,Output,Edge-aligned,Edge-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Center-aligned,Center-aligned,Center-aligned,Center-aligned" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x4000000)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x00)&&((per.l(ad:0x400B9000)&0x20)==0x00) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MSB/MSA ,Channel 7 mode select" "Combine,Combine,Combine,Combine" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "Pin not used for FTM,Low,High,Low" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" elif (((per.l(ad:0x400B9000+0x64))&0x4000000)==0x00)&&(((per.l(ad:0x400B9000+0x64))&0x1000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 4.--5. " MS ,Channel mode selection" "One-Shot Capture,Continuous Capture,One-Shot Capture,Continuous Capture" rbitfld.long 0x00 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" else group.long 0x44++0x07 line.long 0x00 "C7SC,Channel 7 Status And Control" rbitfld.long 0x00 7. " CHF ,Channel Flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CHIE ,Channel Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " DMA ,DMA Enable" "Disabled,Enabled" line.long 0x04 "C7V,Channel 7 Value" hexmask.long.word 0x04 0.--15. 1. " VAL ,Channel value" endif endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0xC++0x03 hide.long 0x00 "C0SC,FTM3 Channel 0 Status And Control Register" in group.long (0xC+0x04)++0x03 line.long 0x00 "C0V,FTM3 Channel 0 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 0 value" hgroup.long 0x14++0x03 hide.long 0x00 "C1SC,FTM3 Channel 1 Status And Control Register" in group.long (0x14+0x04)++0x03 line.long 0x00 "C1V,FTM3 Channel 1 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 1 value" hgroup.long 0x1C++0x03 hide.long 0x00 "C2SC,FTM3 Channel 2 Status And Control Register" in group.long (0x1C+0x04)++0x03 line.long 0x00 "C2V,FTM3 Channel 2 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 2 value" hgroup.long 0x24++0x03 hide.long 0x00 "C3SC,FTM3 Channel 3 Status And Control Register" in group.long (0x24+0x04)++0x03 line.long 0x00 "C3V,FTM3 Channel 3 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 3 value" hgroup.long 0x2C++0x03 hide.long 0x00 "C4SC,FTM3 Channel 4 Status And Control Register" in group.long (0x2C+0x04)++0x03 line.long 0x00 "C4V,FTM3 Channel 4 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 4 value" hgroup.long 0x34++0x03 hide.long 0x00 "C5SC,FTM3 Channel 5 Status And Control Register" in group.long (0x34+0x04)++0x03 line.long 0x00 "C5V,FTM3 Channel 5 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 5 value" hgroup.long 0x3C++0x03 hide.long 0x00 "C6SC,FTM3 Channel 6 Status And Control Register" in group.long (0x3C+0x04)++0x03 line.long 0x00 "C6V,FTM3 Channel 6 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 6 value" hgroup.long 0x44++0x03 hide.long 0x00 "C7SC,FTM3 Channel 7 Status And Control Register" in group.long (0x44+0x04)++0x03 line.long 0x00 "C7V,FTM3 Channel 7 Value Register" hexmask.long.word 0x00 0.--15. 1. " VAL ,Channel 7 value" else group.long 0x0C++0x3F line.long 0x0 "C0SC,FTM3 Channel 0 Status And Control Register" rbitfld.long 0x0 7. " CHF ,Channel 0 flag" "Not occurred,Occurred" bitfld.long 0x0 6. " CHIE ,Channel 0 interrupt enable" "Disabled,Enabled" bitfld.long 0x0 4.--5. " MSB/MSA ,Channel 0 mode select" "00,01,10,11" bitfld.long 0x0 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x0 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x0+0x4) "C0V,FTM3 Channel 0 Value Register" hexmask.long.word (0x0+0x4) 0.--15. 1. " VAL ,Channel 0 value" line.long 0x8 "C1SC,FTM3 Channel 1 Status And Control Register" rbitfld.long 0x8 7. " CHF ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x8 6. " CHIE ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x8 4.--5. " MSB/MSA ,Channel 1 mode select" "00,01,10,11" bitfld.long 0x8 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x8 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x8+0x4) "C1V,FTM3 Channel 1 Value Register" hexmask.long.word (0x8+0x4) 0.--15. 1. " VAL ,Channel 1 value" line.long 0x10 "C2SC,FTM3 Channel 2 Status And Control Register" rbitfld.long 0x10 7. " CHF ,Channel 2 flag" "Not occurred,Occurred" bitfld.long 0x10 6. " CHIE ,Channel 2 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4.--5. " MSB/MSA ,Channel 2 mode select" "00,01,10,11" bitfld.long 0x10 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x10 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x10+0x4) "C2V,FTM3 Channel 2 Value Register" hexmask.long.word (0x10+0x4) 0.--15. 1. " VAL ,Channel 2 value" line.long 0x18 "C3SC,FTM3 Channel 3 Status And Control Register" rbitfld.long 0x18 7. " CHF ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x18 6. " CHIE ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x18 4.--5. " MSB/MSA ,Channel 3 mode select" "00,01,10,11" bitfld.long 0x18 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x18 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x18+0x4) "C3V,FTM3 Channel 3 Value Register" hexmask.long.word (0x18+0x4) 0.--15. 1. " VAL ,Channel 3 value" line.long 0x20 "C4SC,FTM3 Channel 4 Status And Control Register" rbitfld.long 0x20 7. " CHF ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x20 6. " CHIE ,Channel 4 interrupt enable" "Disabled,Enabled" bitfld.long 0x20 4.--5. " MSB/MSA ,Channel 4 mode select" "00,01,10,11" bitfld.long 0x20 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x20 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x20+0x4) "C4V,FTM3 Channel 4 Value Register" hexmask.long.word (0x20+0x4) 0.--15. 1. " VAL ,Channel 4 value" line.long 0x28 "C5SC,FTM3 Channel 5 Status And Control Register" rbitfld.long 0x28 7. " CHF ,Channel 5 flag" "Not occurred,Occurred" bitfld.long 0x28 6. " CHIE ,Channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x28 4.--5. " MSB/MSA ,Channel 5 mode select" "00,01,10,11" bitfld.long 0x28 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x28 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x28+0x4) "C5V,FTM3 Channel 5 Value Register" hexmask.long.word (0x28+0x4) 0.--15. 1. " VAL ,Channel 5 value" line.long 0x30 "C6SC,FTM3 Channel 6 Status And Control Register" rbitfld.long 0x30 7. " CHF ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x30 6. " CHIE ,Channel 6 interrupt enable" "Disabled,Enabled" bitfld.long 0x30 4.--5. " MSB/MSA ,Channel 6 mode select" "00,01,10,11" bitfld.long 0x30 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x30 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x30+0x4) "C6V,FTM3 Channel 6 Value Register" hexmask.long.word (0x30+0x4) 0.--15. 1. " VAL ,Channel 6 value" line.long 0x38 "C7SC,FTM3 Channel 7 Status And Control Register" rbitfld.long 0x38 7. " CHF ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x38 6. " CHIE ,Channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x38 4.--5. " MSB/MSA ,Channel 7 mode select" "00,01,10,11" bitfld.long 0x38 2.--3. " ELSB/ELSA ,Edge or level select" "No edge,Rising,Falling,Both" newline bitfld.long 0x38 0. " DMA ,DMA enable" "Disabled,Enabled" line.long (0x38+0x4) "C7V,FTM3 Channel 7 Value Register" hexmask.long.word (0x38+0x4) 0.--15. 1. " VAL ,Channel 7 value" endif newline group.long 0x4C++0x03 line.long 0x00 "CNTIN,FTM3 Counter Initial Value Register" hexmask.long.word 0x00 0.--15. 1. " INIT ,Initial value of FTM3 counter" sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") group.long 0x50++0x03 line.long 0x00 "STATUS,FTM3 Capture And Compare Status Register" bitfld.long 0x00 7. " CH7F ,Channel 7 flag" "Not occurred,Occurred" bitfld.long 0x00 6. " CH6F ,Channel 6 flag" "Not occurred,Occurred" bitfld.long 0x00 5. " CH5F ,Channel 5 flag" "Not occurred,Occurred" newline bitfld.long 0x00 4. " CH4F ,Channel 4 flag" "Not occurred,Occurred" bitfld.long 0x00 3. " CH3F ,Channel 3 flag" "Not occurred,Occurred" bitfld.long 0x00 2. " CH2F ,Channel 2 flag" "Not occurred,Occurred" newline bitfld.long 0x00 1. " CH1F ,Channel 1 flag" "Not occurred,Occurred" bitfld.long 0x00 0. " CH0F ,Channel 0 flag" "Not occurred,Occurred" newline elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") hgroup.long 0x50++0x03 hide.long 0x00 "STATUS,FTM3 Capture And Compare Status Register" in endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x54++0x03 line.long 0x00 "MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (software/hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" else group.long 0x54++0x03 line.long 0x00 "MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline rbitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline rbitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif else group.long 0x54++0x03 line.long 0x00 "MODE,FTM3 Features Mode Selection Register" bitfld.long 0x00 7. " FAULTIE ,Fault interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5.--6. " FAULTM ,Fault control mode" "Disabled,Even channels / Manual fault clearing,All channels / Manual fault clearing,All channels / Auto fault clearing" newline bitfld.long 0x00 4. " CAPTEST ,Capture test mode enable" "Disabled,Enabled" bitfld.long 0x00 3. " PWMSYNC ,PWM synchronization mode (Software/Hardware triggers usage)" "No restrictions,MOD CnV / OUTMASK FTM" newline bitfld.long 0x00 2. " WPDIS ,Write protection disable" "No,Yes" bitfld.long 0x00 1. " INIT ,Initialize the channels output" "Not initialized,Initialized" newline bitfld.long 0x00 0. " FTMEN ,FTM enable" "Disabled,Enabled" endif group.long 0x58++0x0B line.long 0x00 "SYNC,FTM3 Synchronization Register" bitfld.long 0x00 7. " SWSYNC ,PWM synchronization software trigger" "Not selected,Selected" bitfld.long 0x00 6. " TRIG2 ,PWM synchronization hardware trigger 2" "Disabled,Enabled" newline bitfld.long 0x00 5. " TRIG1 ,PWM synchronization hardware trigger 1" "Disabled,Enabled" bitfld.long 0x00 4. " TRIG0 ,PWM synchronization hardware trigger 0" "Disabled,Enabled" newline bitfld.long 0x00 3. " SYNCHOM ,Output mask synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " REINIT ,FTM counter reinitialization by synchronization" "Normal,Updated on trigger" newline bitfld.long 0x00 1. " CNTMAX ,Maximum loading point enable" "Disabled,Enabled" bitfld.long 0x00 0. " CNTMIN ,Minimum loading point enable" "Disabled,Enabled" newline line.long 0x04 "OUTINIT,FTM3 Initial State For Channels Output Register" bitfld.long 0x04 7. " CH7OI ,Channel 7 output initialization value" "0,1" bitfld.long 0x04 6. " CH6OI ,Channel 6 output initialization value" "0,1" bitfld.long 0x04 5. " CH5OI ,Channel 5 output initialization value" "0,1" bitfld.long 0x04 4. " CH4OI ,Channel 4 output initialization value" "0,1" newline bitfld.long 0x04 3. " CH3OI ,Channel 3 output initialization value" "0,1" bitfld.long 0x04 2. " CH2OI ,Channel 2 output initialization value" "0,1" newline bitfld.long 0x04 1. " CH1OI ,Channel 1 output initialization value" "0,1" bitfld.long 0x04 0. " CH0OI ,Channel 0 output initialization value" "0,1" newline line.long 0x08 "OUTMASK,FTM3 Output Mask Register" bitfld.long 0x08 7. " CH7OM ,Channel 7 output mask" "Not masked,Masked" bitfld.long 0x08 6. " CH6OM ,Channel 6 output mask" "Not masked,Masked" bitfld.long 0x08 5. " CH5OM ,Channel 5 output mask" "Not masked,Masked" bitfld.long 0x08 4. " CH4OM ,Channel 4 output mask" "Not masked,Masked" newline bitfld.long 0x08 3. " CH3OM ,Channel 3 output mask" "Not masked,Masked" bitfld.long 0x08 2. " CH2OM ,Channel 2 output mask" "Not masked,Masked" newline bitfld.long 0x08 1. " CH1OM ,Channel 1 output mask" "Not masked,Masked" bitfld.long 0x08 0. " CH0OM ,Channel 0 output mask" "Not masked,Masked" newline sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM3 Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM3 Function For Linked Channels Register" rbitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" rbitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" rbitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline rbitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" rbitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline rbitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 18. " DECAPEN2 ,Dual Edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline rbitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" rbitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" rbitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" rbitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline rbitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" rbitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" rbitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline rbitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" rbitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" rbitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" rbitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline rbitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif else group.long 0x64++0x03 line.long 0x00 "COMBINE,FTM3 Function For Linked Channels Register" bitfld.long 0x00 30. " FAULTEN3 ,Fault control enable in channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 29. " SYNCEN3 ,PWM synchronization enable (C6V,C7V)" "Disabled,Enabled" bitfld.long 0x00 28. " DTEN3 ,Dead-time enable in channels 6 and 7" "Disabled,Enabled" newline bitfld.long 0x00 27. " DECAP3 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 26. " DECAPEN3 ,Dual edge capture mode enable for channels 6 and 7" "Disabled,Enabled" bitfld.long 0x00 25. " COMP3 ,Complementary mode for channels 6 and 7" "CH7 same as CH6,CH7 complement of CH6" newline bitfld.long 0x00 24. " COMBINE3 ,Combine channels 6 and 7" "Independent,Combined" bitfld.long 0x00 22. " FAULTEN2 ,Fault control enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 21. " SYNCEN2 ,PWM synchronization enable (C4V,C5V)" "Disabled,Enabled" newline bitfld.long 0x00 20. " DTEN2 ,Dead-time enable in channels 4 and 5" "Disabled,Enabled" bitfld.long 0x00 19. " DECAP2 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 18. " DECAPEN2 ,Dual edge capture mode enable for channels 4 and 5" "Disabled,Enabled" newline bitfld.long 0x00 17. " COMP2 ,Complementary mode for channels 4 and 5" "CH5 same as CH4,CH5 complement of CH4" bitfld.long 0x00 16. " COMBINE2 ,Combine channels 4 and 5" "Independent,Combined" bitfld.long 0x00 14. " FAULTEN1 ,Fault control enable in channels 2 and 3" "Disabled,Enabled" newline bitfld.long 0x00 13. " SYNCEN1 ,PWM synchronization enable (C2V,C3V)" "Disabled,Enabled" bitfld.long 0x00 12. " DTEN1 ,Dead-time enable in channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 11. " DECAP1 ,Dual edge capture mode captures" "Inactive,Active" newline bitfld.long 0x00 10. " DECAPEN1 ,Dual edge capture mode enable for channels 2 and 3" "Disabled,Enabled" bitfld.long 0x00 9. " COMP1 ,Complementary mode for channels 2 and 3" "CH3 same as CH2,CH3 complement of CH2" bitfld.long 0x00 8. " COMBINE1 ,Combine channels 2 and 3" "Independent,Combined" newline bitfld.long 0x00 6. " FAULTEN0 ,Fault control enable in channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 5. " SYNCEN0 ,PWM synchronization enable (C0V,C1V)" "Disabled,Enabled" bitfld.long 0x00 4. " DTEN0 ,Dead-time enable in channels 0 and 1" "Disabled,Enabled" newline bitfld.long 0x00 3. " DECAP0 ,Dual edge capture mode captures" "Inactive,Active" bitfld.long 0x00 2. " DECAPEN0 ,Dual edge capture mode enable for channels 0 and 1" "Disabled,Enabled" bitfld.long 0x00 1. " COMP0 ,Complementary mode for channels 0 and 1" "CH1 same as CH0,CH1 complement of CH0" newline bitfld.long 0x00 0. " COMBINE0 ,Combine channels 0 and 1" "Independent,Combined" endif if ((per.l(ad:0x400B9000+0x54)&0x04)==0x04) group.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM3 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" else rgroup.long 0x68++0x03 line.long 0x00 "DEADTIME,FTM3 Dead-Time Insertion Control Register" bitfld.long 0x00 6.--7. " DTPS ,Dead-time prescaler value" "/1,/1,/4,/16" bitfld.long 0x00 0.--5. " DTVAL ,Dead-time value" "No counts,1 count,2 counts,3 counts,4 counts,5 counts,6 counts,7 counts,8 counts,9 counts,10 counts,11 counts,12 counts,13 counts,14 counts,15 counts,16 counts,17 counts,18 counts,19 counts,20 counts,21 counts,22 counts,23 counts,24 counts,25 counts,26 counts,27 counts,28 counts,29 counts,30 counts,31 counts,32 counts,33 counts,34 counts,35 counts,36 counts,37 counts,38 counts,39 counts,40 counts,41 counts,42 counts,43 counts,44 counts,45 counts,46 counts,47 counts,48 counts,49 counts,50 counts,51 counts,52 counts,53 counts,54 counts,55 counts,56 counts,57 counts,58 counts,59 counts,60 counts,61 counts,62 counts,63 counts" endif group.long 0x6C++0x03 line.long 0x00 "EXTTRIG,FTM3 External Trigger Register" bitfld.long 0x00 7. " TRIGF ,Channel trigger flag" "Not occurred,Occurred" bitfld.long 0x00 6. " INITTRIGEN ,Initialization trigger enable" "Disabled,Enabled" bitfld.long 0x00 5. " CH1TRIG ,Channel 1 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 4. " CH0TRIG ,Channel 0 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " CH5TRIG ,Channel 5 trigger enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH4TRIG ,Channel 4 trigger enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH3TRIG ,Channel 3 trigger enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " CH2TRIG ,Channel 2 trigger enable" "Disabled,Enabled" if ((per.l(ad:0x400B9000+0x54)&0x04)==0x04) group.long 0x70++0x03 line.long 0x00 "POL,FTM3 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" else rgroup.long 0x70++0x03 line.long 0x00 "POL,FTM3 Channels Polarity Register" bitfld.long 0x00 7. " POL[7] ,Channel 7 polarity" "Active high,Active low" bitfld.long 0x00 6. " [6] ,Channel 6 polarity" "Active high,Active low" bitfld.long 0x00 5. " [5] ,Channel 5 polarity" "Active high,Active low" newline bitfld.long 0x00 4. " [4] ,Channel 4 polarity" "Active high,Active low" bitfld.long 0x00 3. " [3] ,Channel 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " [2] ,Channel 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " POL[1] ,Channel 1 polarity" "Active high,Active low" bitfld.long 0x00 0. " [0] ,Channel 0 polarity" "Active high,Active low" endif sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") hgroup.long 0x74++0x03 hide.long 0x00 "FMS,FTM3 Fault Mode Status Register" in else group.long 0x74++0x03 line.long 0x00 "FMS,FTM3 Fault Mode Status Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" else sif cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*") rbitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline else bitfld.long 0x00 7. " FAULTF ,Fault detection flag" "Not detected,Detected" newline endif bitfld.long 0x00 6. " WPEN ,Write protection enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FAULTIN ,Logic OR of the enabled fault inputs" "0,1" newline bitfld.long 0x00 3. " FAULTF3 ,Fault detection flag 3" "Not detected,Detected" bitfld.long 0x00 2. " FAULTF2 ,Fault detection flag 2" "Not detected,Detected" newline bitfld.long 0x00 1. " FAULTF1 ,Fault detection flag 1" "Not detected,Detected" bitfld.long 0x00 0. " FAULTF0 ,Fault detection flag 0" "Not detected,Detected" endif endif group.long 0x78++0x03 line.long 0x00 "FILTER,FTM3 Input Capture Filter Control Register" bitfld.long 0x00 12.--15. " CH3FVAL ,Channel 3 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " CH2FVAL ,Channel 2 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. " CH1FVAL ,Channel 1 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " CH0FVAL ,Channel 0 input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else bitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" bitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif else group.long 0x7C++0x03 line.long 0x00 "FLTCTRL,FTM3 Fault Control Register" bitfld.long 0x00 8.--11. " FFVAL ,Fault input filter" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" else rbitfld.long 0x00 7. " FFLTR3EN ,Fault input 3 filter enable" "Disabled,Enabled" rbitfld.long 0x00 6. " FFLTR2EN ,Fault input 2 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 5. " FFLTR1EN ,Fault input 1 filter enable" "Disabled,Enabled" rbitfld.long 0x00 4. " FFLTR0EN ,Fault input 0 filter enable" "Disabled,Enabled" newline rbitfld.long 0x00 3. " FAULT3EN ,Fault input 3 enable" "Disabled,Enabled" rbitfld.long 0x00 2. " FAULT2EN ,Fault input 2 enable" "Disabled,Enabled" newline rbitfld.long 0x00 1. " FAULT1EN ,Fault input 1 enable" "Disabled,Enabled" rbitfld.long 0x00 0. " FAULT0EN ,Fault input 0 enable" "Disabled,Enabled" endif endif sif cpuis("MK11D*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN1M0VMC10")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK50DX256ZCLL10")||(cpu()=="MK50DN512ZCLL10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||(cpu()=="MK51DN256ZCLQ10")||(cpu()=="MK51DN256ZCMD10")||(cpu()=="MK51DN512ZCLQ10")||(cpu()=="MK51DN512ZCMD10")||(cpu()=="MK51DX256ZCMC10")||(cpu()=="MK51DN512ZCMC10")||(cpu()=="MK51DX256ZCLL10")||(cpu()=="MK51DN512ZCLL10")||(cpu()=="MK50DN512ZCLQ10")||(cpu()=="MK50DN512ZCMD10")||(cpu()=="MK50DX256ZCLQ10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") sif (cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*"))||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x400B9000+0x54))&0x04)==0x04) group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 Counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" rbitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif elif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK70*") elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") else endif else group.long 0x80++0x03 line.long 0x00 "QDCTRL,FTM3 Quadrature Decoder Control And Status Register" bitfld.long 0x00 7. " PHAFLTREN ,Phase A input filter enable" "Disabled,Enabled" bitfld.long 0x00 6. " PHBFLTREN ,Phase B input filter enable" "Disabled,Enabled" bitfld.long 0x00 5. " PHAPOL ,Phase A input polarity" "Normal,Inverted" newline bitfld.long 0x00 4. " PHBPOL ,Phase B input polarity" "Normal,Inverted" bitfld.long 0x00 3. " QUADMODE ,Quadrature decoder mode" "Phase A & B,Count and direction" rbitfld.long 0x00 2. " QUADIR ,FTM3 counter direction in quadrature decoder mode" "Decreasing,Increasing" newline rbitfld.long 0x00 1. " TOFDIR ,Timer overflow direction in quadrature decoder mode" "Min->Max,Max->Min" bitfld.long 0x00 0. " QUADEN ,Quadrature decoder mode enable" "Disabled,Enabled" endif group.long 0x84++0x03 line.long 0x00 "CONF,FTM3 Configuration Register" bitfld.long 0x00 10. " GTBEOUT ,Global time base output" "Disabled,Enabled" bitfld.long 0x00 9. " GTBEEN ,Global time base enable" "Disabled,Enabled" bitfld.long 0x00 6.--7. " BDMMODE ,BDM mode (FTM counter/FTM channels output)" "Stopped/Functional,Stopped/Forced to safe value,Stopped/Frozen,Functional/Functional" newline bitfld.long 0x00 0.--4. " NUMTOF ,TOF Frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if ((per.l(ad:0x400B9000+0x54)&0x04)==0x04) group.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" else rgroup.long 0x88++0x03 line.long 0x00 "FLTPOL,FTM3 Fault Input Polarity Register" sif cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVMD12")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FX512VMC10")||cpuis("MK21FX512VMD10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R") bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline elif cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK24FN256VDC12") elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline else bitfld.long 0x00 3. " FLT3POL ,Fault input 3 polarity" "Active high,Active low" bitfld.long 0x00 2. " FLT2POL ,Fault input 2 polarity" "Active high,Active low" newline bitfld.long 0x00 1. " FLT1POL ,Fault input 1 polarity" "Active high,Active low" newline endif bitfld.long 0x00 0. " FLT0POL ,Fault input 0 polarity" "Active high,Active low" endif group.long 0x8C++0x0F line.long 0x00 "SYNCONF,FTM3 Synchronization Configuration Register" bitfld.long 0x00 20. " HWSOC ,Software output control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 19. " HWINVC ,Inverting control synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 18. " HWOM ,Output mask synchronization (hardware trigger)" "Not activated,Activated" newline bitfld.long 0x00 17. " HWWRBUF ,MOD, CNTIN and CV registers synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 16. " HWRSTCNT ,FTM counter synchronization (hardware trigger)" "Not activated,Activated" bitfld.long 0x00 12. " SWSOC ,Software output control synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 11. " SWINVC ,Inverting control synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 10. " SWOM ,Output mask synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 9. " SWWRBUF ,MOD, CNTIN and CV registers synchronization (software trigger)" "Not activated,Activated" newline bitfld.long 0x00 8. " SWRSTCNT ,FTM counter synchronization (software trigger)" "Not activated,Activated" bitfld.long 0x00 7. " SYNCMODE ,PWM synchronization mode" "Legacy,Enhanced" bitfld.long 0x00 5. " SWOC ,SWOCTRL register synchronization" "At rising edges of sys clk,By PWM sync" newline bitfld.long 0x00 4. " INVC ,INVCTRL register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 2. " CNTINC ,CNTIN register synchronization" "At rising edges of sys clk,By PWM sync" bitfld.long 0x00 0. " HWTRIGMODE ,Hardware trigger mode" "Cleared,Not cleared" line.long 0x04 "INVCTRL,FTM3 Inverting Control Register" bitfld.long 0x04 3. " INV3EN ,Pair channels 3 inverting enable" "Disabled,Enabled" bitfld.long 0x04 2. " INV2EN ,Pair channels 2 inverting enable" "Disabled,Enabled" bitfld.long 0x04 1. " INV1EN ,Pair channels 1 inverting enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " INV0EN ,Pair channels 0 inverting enable" "Disabled,Enabled" line.long 0x08 "SWOCTRL,FTM3 Software Output Control Register" bitfld.long 0x08 15. " CH7OCV ,Channel 7 Software output control value" "0,1" bitfld.long 0x08 14. " CH6OCV ,Channel 6 software output control value" "0,1" bitfld.long 0x08 13. " CH5OCV ,Channel 5 software output control value" "0,1" newline bitfld.long 0x08 12. " CH4OCV ,Channel 4 software output control value" "0,1" bitfld.long 0x08 11. " CH3OCV ,Channel 3 software output control value" "0,1" bitfld.long 0x08 10. " CH2OCV ,Channel 2 software output control value" "0,1" newline bitfld.long 0x08 9. " CH1OCV ,Channel 1 software output control value" "0,1" bitfld.long 0x08 8. " CH0OCV ,Channel 0 software output control value" "0,1" newline bitfld.long 0x08 7. " CH7OC ,Channel 7 software output control enable" "Disabled,Enabled" bitfld.long 0x08 6. " CH6OC ,Channel 6 software output control enable" "Disabled,Enabled" bitfld.long 0x08 5. " CH5OC ,Channel 5 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 4. " CH4OC ,Channel 4 software output control enable" "Disabled,Enabled" bitfld.long 0x08 3. " CH3OC ,Channel 3 software output control enable" "Disabled,Enabled" bitfld.long 0x08 2. " CH2OC ,Channel 2 software output control enable" "Disabled,Enabled" newline bitfld.long 0x08 1. " CH1OC ,Channel 1 software output control enable" "Disabled,Enabled" bitfld.long 0x08 0. " CH0OC ,Channel 0 software output control enable" "Disabled,Enabled" line.long 0x0C "PWMLOAD,FTM3 PWM Load Register" bitfld.long 0x0C 9. " LDOK ,Load enable" "Disabled,Enabled" newline bitfld.long 0x0C 7. " CH7SE ,Channel 7 select" "Not included,Included" bitfld.long 0x0C 6. " CH6SE ,Channel 6 select" "Not included,Included" bitfld.long 0x0C 5. " CH5SE ,Channel 5 select" "Not included,Included" newline bitfld.long 0x0C 4. " CH4SE ,Channel 4 select" "Not included,Included" bitfld.long 0x0C 3. " CH3SE ,Channel 3 select" "Not included,Included" bitfld.long 0x0C 2. " CH2SE ,Channel 2 select" "Not included,Included" newline bitfld.long 0x0C 1. " CH1SE ,Channel 1 select" "Not included,Included" bitfld.long 0x0C 0. " CH0SE ,Channel 0 select" "Not included,Included" width 0x0B tree.end tree.end tree "PIT (Periodic Interrupt Timer)" base ad:0x40037000 sif cpuis("MK65*F*")||cpuis("MK66*F*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK65FN2M0CAC18R") width 9. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" else group.long 0xE0++0x07 line.long 0x00 "LTMR64H,PIT Upper Lifetime Timer Register" line.long 0x04 "LTMR64L,PIT Lower Lifetime Timer Register" endif else width 8. group.long 0x00++0x03 line.long 0x00 "MCR,PIT Module Control Register" bitfld.long 0x00 1. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 0. " FRZ ,Freeze in debug mode" "Not stopped,Stopped" endif width 9. group.long 0x100++0x03 "PIT 0 Registers" line.long 0x00 "LDVAL0,PIT0 Timer Load Value Register" rgroup.long (0x100+0x4)++0x03 line.long 0x00 "CVAL0,PIT0 Current Timer Value Register" group.long (0x100+0x08)++0x03 line.long 0x00 "TCTRL0,PIT0 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x100+0x0C)++0x03 line.long 0x00 "TFLG0,PIT0 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x110++0x03 "PIT 1 Registers" line.long 0x00 "LDVAL1,PIT1 Timer Load Value Register" rgroup.long (0x110+0x4)++0x03 line.long 0x00 "CVAL1,PIT1 Current Timer Value Register" group.long (0x110+0x08)++0x03 line.long 0x00 "TCTRL1,PIT1 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x110+0x0C)++0x03 line.long 0x00 "TFLG1,PIT1 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x120++0x03 "PIT 2 Registers" line.long 0x00 "LDVAL2,PIT2 Timer Load Value Register" rgroup.long (0x120+0x4)++0x03 line.long 0x00 "CVAL2,PIT2 Current Timer Value Register" group.long (0x120+0x08)++0x03 line.long 0x00 "TCTRL2,PIT2 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x120+0x0C)++0x03 line.long 0x00 "TFLG2,PIT2 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" group.long 0x130++0x03 "PIT 3 Registers" line.long 0x00 "LDVAL3,PIT3 Timer Load Value Register" rgroup.long (0x130+0x4)++0x03 line.long 0x00 "CVAL3,PIT3 Current Timer Value Register" group.long (0x130+0x08)++0x03 line.long 0x00 "TCTRL3,PIT3 Timer Control Register" sif !cpuis("MK?0F*")&&!cpuis("MK?0D*5")&&!cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512*AB10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK20DN512ZVLL10")&&!cpuis("MK20DX256ZVLL10")&&!cpuis("MK20DN512ZVLQ10")&&!cpuis("MK20DN512ZVLQ10R")&&!cpuis("MK20DN512ZVMD10")&&!cpuis("MK20DX128ZVLQ10")&&!cpuis("MK20DX256ZVLQ10")&&!cpuis("MK20DX256ZVLQ10R")&&!cpuis("MK20DX256ZVMD10")&&!cpuis("MK20DN512ZVLK10")&&!cpuis("MK20DX256ZVLK10")&&!cpuis("MK20DN512ZVMC10")&&!cpuis("MK20DN512ZVMC10R") sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK02*")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK8?FN256V*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15") bitfld.long 0x00 2. " CHN ,Chain mode" "Not chained,Chained" newline endif endif bitfld.long 0x00 1. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" group.long (0x130+0x0C)++0x03 line.long 0x00 "TFLG3,PIT3 Timer Flag Register" eventfld.long 0x00 0. " TIF ,Timer interrupt flag" "Not occurred,Occurred" width 0x0B tree.end tree "LPT (Low Power Timer)" base ad:0x40040000 width 5. sif cpuis("MK11D*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK02*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40D*Z*10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK21DN512AVMC5R")||cpuis("MK21DX256AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline rbitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" rbitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" rbitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" newline sif cpuis("MK20DX256VLK10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK22FN1M0VMC10")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0VLH10")||cpuis("MK22FX512AVMD12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN512VMP12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0AVLH12")||(cpuis("MK40DN512ZVLQ10"))||(cpuis("MK40DN512ZVMD10"))||(cpuis("MK40DX128ZVLQ10"))||(cpuis("MK40DX256ZVLQ10"))||(cpuis("MK40DX256ZVMD10"))||(cpuis("MK40DN512ZVLL10"))||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN1M0VLK12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN128VLH10R")||cpuis("MK20DN512VLK10R")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,?..." elif cpuis("MK8?FN256V*")||cpuis("MK40D*Z*10")||cpuis("MK21FX512VMC10")||cpuis("MK21FN1M0VMC10")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK10DN512ZV??10*")||cpuis("MK10DX256ZV??10*")||cpuis("MK11DN512AVLK5*")||cpuis("MK11DN512VLK5*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" else rbitfld.long 0x00 4.--5. " TPS ,Timer pin select" "CMP 0 output,LPTMR_ALT1 pin,LPTMR_ALT2 pin,LPTMR_ALT3 pin" endif newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "CSR,Low Power Timer Control Status Register" eventfld.long 0x00 7. " TCF ,Timer compare flag" "Not equaled,Equaled" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4.--5. " TPS ,Timer pin select" "Input 0,Input 1,Input 2,Input 3" newline bitfld.long 0x00 3. " TPP ,Timer pin polarity" "Active high,Active low" bitfld.long 0x00 2. " TFC ,Timer free running counter" "Reset on TCF set,Reset on overflow" bitfld.long 0x00 1. " TMS ,Timer mode select" "Time counter,Pulse counter" newline bitfld.long 0x00 0. " TEN ,Timer enable" "Disabled,Enabled" endif if ((per.l(ad:0x40040000)&0x02)==0x00) if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " PRESCALE ,Prescale value" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 2. " PBYP ,Prescaler bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif else if (((per.l(ad:0x40040000+0x00))&0x01)==0x01) rgroup.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" else group.long 0x04++0x03 line.long 0x00 "PSR,Low Power Timer Prescale Register" bitfld.long 0x00 3.--6. " GFW ,Glitch filter width" ",2 clk edges,4 clk edges,8 clk edges,16 clk edges,32 clk edges,64 clk edges,128 clk edges,256 clk edges,512 clk edges,1024 clk edges,2048 clk edges,4096 clk edges,8192 clk edges,16384 clk edges,32768 clk edges" bitfld.long 0x00 2. " PBYP ,Glitch filter bypass" "Not bypassed,Bypassed" bitfld.long 0x00 0.--1. " PCS ,Prescaler clock select" "MCGIRCLK,LPO 1kHz,ERCLK32K,OSCERCLK" endif endif sif cpuis("MK84FN2M0CAU15R") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" elif cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN1M0AVLK12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FX512AVLH12R")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R")||cpuis("KK60FN1M0VLQ15") if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif group.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" else if (((per.l(ad:0x40040000+0x00))&0x81)==0x80) rgroup.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" else group.long 0x08++0x03 line.long 0x00 "CMR,Low Power Timer Compare Register" hexmask.long.word 0x00 0.--15. 1. " COMPARE ,Compare value" endif rgroup.long 0x0C++0x03 line.long 0x00 "CNR,Low Power Timer Counter Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter value" endif width 0x0B tree.end tree "CMT (Carrier Modulator Transmitter)" base ad:0x40062000 width 6. group.byte 0x00++0x04 line.byte 0x00 "CGH1,CMT Carrier Generator High Data Register 1" line.byte 0x01 "CGL1,CMT Carrier Generator Low Data Register 1" line.byte 0x02 "CGH2,CMT Carrier Generator High Data Register 2" line.byte 0x03 "CGL2,CMT Carrier Generator Low Data Register 2" line.byte 0x04 "OC,CMT Output Control Register" bitfld.byte 0x04 7. " IROL ,IRO latch control" "Low,High" bitfld.byte 0x04 6. " CMTPOL ,CMT output polarity" "Active low,Active high" bitfld.byte 0x04 5. " IROPEN ,IRO pin enable" "Disabled,Enabled" hgroup.byte 0x05++0x00 hide.byte 0x00 "MSC,CMT Modulator Status and Control Register" in group.byte 0x06++0x05 line.byte 0x00 "CMD1,CMT Modulator Data Register Mark High" line.byte 0x01 "CMD2,CMT Modulator Data Register Mark Low" line.byte 0x02 "CMD3,CMT Modulator Data Register Space High" line.byte 0x03 "CMD4,CMT Modulator Data Register Space Low" line.byte 0x04 "PPS,CMT Primary Prescaler Register" bitfld.byte 0x04 0.--3. " PPSDIV ,Primary prescaler divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" line.byte 0x05 "DMA,CMT Direct Memory Access Register" bitfld.byte 0x05 0. " DMA ,DMA enable" "Disabled,Enabled" width 0x0B tree.end tree "RTC (Real Time Clock)" base ad:0x4003d000 width 6. if ((per.l(ad:0x4003d000+0x14)&0x10)==0x0) group.long 0x00++0x7 line.long 0x00 "TSR,RTC Time Seconds Register" line.long 0x04 "TPR,RTC Time Prescaler Register" hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler" else rgroup.long 0x00++0x7 line.long 0x00 "TSR,RTC Time Seconds Register" line.long 0x04 "TPR,RTC Time Prescaler Register" hexmask.long.word 0x04 0.--15. 1. " TPR ,Time prescaler" endif group.long 0x08++0x17 line.long 0x00 "TAR,RTC Time Alarm Register" line.long 0x04 "TCR,RTC Time Compensation Register" hexmask.long.byte 0x04 24.--31. 1. " CIC ,Compensation interval counter" hexmask.long.byte 0x04 16.--23. 1. " TCV ,Time compensation value" hexmask.long.byte 0x04 8.--15. 1. " CIR ,Compensation interval register" hexmask.long.byte 0x04 0.--7. 1. " TCR ,Time compensation register" line.long 0x08 "CR,RTC Control Register" bitfld.long 0x08 13. " SC2P ,Oscillator 2pF load configure" "Disabled,Enabled" bitfld.long 0x08 12. " SC4P ,Oscillator 4pF load configure" "Disabled,Enabled" bitfld.long 0x08 11. " SC8P ,Oscillator 8pF load configure" "Disabled,Enabled" bitfld.long 0x08 10. " SC16P ,Oscillator 16pF load configure" "Disabled,Enabled" textline " " bitfld.long 0x08 9. " CLKO ,Indicate whether clock is output to other peripherals or not" "Output,Not output" bitfld.long 0x08 8. " OSCE ,Oscillator Enable" "Disabled,Enabled" bitfld.long 0x08 3. " UM ,Update Mode" "Low,High" bitfld.long 0x08 2. " SUP ,Supervisor write access" "Supervisor,Non-supervisor" textline " " bitfld.long 0x08 1. " WPE ,Wakeup pin enable" "Disabled,Enabled" bitfld.long 0x08 0. " SWR ,Software reset" "No reset,Reset" line.long 0x0c "SR,RTC Status Register" bitfld.long 0x0C 4. " TCE ,Time counter enable" "Disabled,Enabled" rbitfld.long 0x0C 3. " MOF ,Monotonic overflow flag" "No overflow,Overflow" rbitfld.long 0x0C 2. " TAF ,Time alarm flag" "Not occurred,Occured" textline " " rbitfld.long 0x0C 1. " TOF ,Time overflow flag" "No overflow,Overflow" rbitfld.long 0x0C 0. " TIF ,Time invalid flag" "Valid,Invalid" line.long 0x10 "LR,RTC Lock Register" sif (!cpuis("MK70*")) bitfld.long 0x10 15. " TIL ,Tamper interrupt lock" "Locked,Not locked" bitfld.long 0x10 14. " TTL ,Tamper trim lock" "Locked,Not locked" bitfld.long 0x10 13. " TDL ,Tamper detect lock" "Locked,Not locked" bitfld.long 0x10 12. " TEL ,Tamper enable lock" "Locked,Not locked" textline " " endif bitfld.long 0x10 11. " MCHL ,Monotonic counter high lock" "Not locked,Locked" bitfld.long 0x10 10. " MCLL ,Monotonic counter low lock" "Not locked,Locked" bitfld.long 0x10 9. " MEL ,Monotonic enable lock" "Not locked,Locked" bitfld.long 0x10 8. " TTSL ,Tamper time seconds lock" "Not locked,Locked" textline " " bitfld.long 0x10 6. " LRL ,Lock register lock" "Locked,Not locked" bitfld.long 0x10 5. " SRL ,Status register lock" "Locked,Not locked" bitfld.long 0x10 4. " CRL ,Control register lock" "Locked,Not locked" bitfld.long 0x10 3. " TCL ,Time compensation lock" "Locked,Not locked" line.long 0x14 "IER,RTC Interrupt Enable Register" sif (cpuis("MK70*")) bitfld.long 0x14 7. " WPON ,Wakeup pin on" "Disabled,Enabled" textline " " endif bitfld.long 0x14 4. " TSIE ,Time seconds interrupt enable" "Disabled,Enabled" bitfld.long 0x14 3. " MOIE ,Monotonic overflow interrupt enable" "Disabled,Enabled" bitfld.long 0x14 2. " TAIE ,Time alarm interrupt enable" "Disabled,Enabled" bitfld.long 0x14 1. " TOIE ,Time overflow interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " TIIE ,Time invalid interrupt enable" "Disabled,Enabled" rgroup.long 0x20++0x03 line.long 0x00 "TTSR,RTC Tamper Time Seconds Register" group.long 0x24++0x0B line.long 0x00 "MER,RTC Monotonic Enable Register" bitfld.long 0x00 4. " MCE ,Monotonic counter enable" "Disabled,Enabled" line.long 0x04 "MCLR,RTC Monotonic Counter Low Register" line.long 0x08 "MCHR,RTC Monotonic Counter High Register" sif (!cpuis("MK70*")) group.long 0x30++0x0F line.long 0x00 "TER,RTC Tamper Enable Register" bitfld.long 0x00 5. " TME ,Test mode enable" "Disabled,Enabled" bitfld.long 0x00 4. " FSE ,Flash security enable" "Disabled,Enabled" bitfld.long 0x00 3. " TTE ,Temperature tamper enable" "Disabled,Enabled" bitfld.long 0x00 2. " CTE ,Clock tamper enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VTE ,Voltage tamper enable" "Disabled,Enabled" bitfld.long 0x04 0. " DTE ,DryIce tamper enable" "Disabled,Enabled" line.long 0x04 "TDR,RTC Tamper Detect Register" eventfld.long 0x04 5. " TMF ,Test mode flag" "Not Detected,Detected" eventfld.long 0x04 4. " FSF ,Flash security flag" "Not Detected,Detected" eventfld.long 0x04 3. " TTF ,Temperature tamper flag" "Not Detected,Detected" eventfld.long 0x04 2. " CTF ,Clock tamper flag" "Not Detected,Detected" textline " " eventfld.long 0x04 1. " VTF ,Voltage tamper flag" "Not Detected,Detected" eventfld.long 0x04 0. " DTF ,DryIce tamper flag" "Not Detected,Detected" line.long 0x08 "TTR,RTC Tamper Trim Register" bitfld.long 0x08 15.--17. " TDTH ,Temperature detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 12.--14. " TDTL ,Temperature detect trim low" "0,1,2,3,4,5,6,7" bitfld.long 0x08 9.--11. " CDTH ,Clock detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 6.--8. " CDTL ,Clock detect trim low" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 3.--5. " VDTH ,Voltage detect trim high" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0.--2. " VDTL ,Voltage detect trim Low" "0,1,2,3,4,5,6,7" line.long 0x0C "TIR,RTC Tamper Interrupt Register" bitfld.long 0x0C 5. " TMIE ,Test mode interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 4. " FSIE ,Flash security interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 3. " TTIE ,Temperature tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x0C 2. " CTIE ,Clock tamper interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0C 1. " VTIE ,Voltage tamper interrupt enable" "Disabled,Enabled" bitfld.long 0x04 0. " DTIE ,DryIce tamper interrupt enable" "Disabled,Enabled" endif group.long 0x800++0x7 line.long 0x00 "WAR,RTC Write Access Register" sif (!cpuis("MK70*")) bitfld.long 0x00 15. " TIRW ,Tamper interrupt register write (writes ignored)" "Ignored,Not ignored" bitfld.long 0x00 14. " TTRW ,Tamper trim register write (writes ignored)" "Ignored,Not ignored" bitfld.long 0x00 13. " TDRW ,Tamper detect register write (writes ignored)" "Ignored,Not ignored" bitfld.long 0x00 12. " TERW ,Tamper enable register write (writes ignored)" "Ignored,Not ignored" textline " " endif bitfld.long 0x00 11. " MCHW ,Monotonic counter high write" "Ignored,Normal" bitfld.long 0x00 10. " MCLW ,Monotonic counter low write" "Ignored,Normal" bitfld.long 0x00 9. " MERW ,Monotonic enable register write" "Ignored,Normal" bitfld.long 0x00 8. " TTSW ,Tamper time seconds write" "Ignored,Normal" textline " " bitfld.long 0x00 7. " IERW ,Interrupt enable register write" "Ignored,Normal" bitfld.long 0x00 6. " LRW ,Lock register write" "Ignored,Normal" bitfld.long 0x00 5. " SRW ,Status register write" "Ignored,Normal" bitfld.long 0x00 4. " CRW ,Control register write" "Ignored,Normal" textline " " bitfld.long 0x00 3. " TCRW ,Time compensation register write" "Ignored,Normal" bitfld.long 0x00 2. " TARW ,Time alarm register write" "Ignored,Normal" bitfld.long 0x00 1. " TPRW ,Time prescaler register write" "Ignored,Normal" bitfld.long 0x00 0. " TSRW ,Time seconds register write" "Ignored,Normal" line.long 0x04 "RAR,RTC Read Access Register" sif (!cpuis("MK70*")) bitfld.long 0x04 15. " TIRR ,Tamper interrupt register read (reads ignored)" "Ignored,Not ignored" bitfld.long 0x04 14. " TTRR ,Tamper trim register read (reads ignored)" "Ignored,Not ignored" bitfld.long 0x04 13. " TDRR ,Tamper detect register read (reads ignored)" "Ignored,Not ignored" bitfld.long 0x04 12. " TERR ,Tamper enable register read (reads ignored)" "Ignored,Not ignored" textline " " endif bitfld.long 0x04 11. " MCHR ,Monotonic counter high read" "Ignored,Normal" bitfld.long 0x04 10. " MCLR ,Monotonic counter low read" "Ignored,Normal" bitfld.long 0x04 9. " MERR ,Monotonic enable register read" "Ignored,Normal" bitfld.long 0x04 8. " TTSR ,Tamper time seconds read" "Ignored,Normal" textline " " bitfld.long 0x04 7. " IERR ,Interrupt enable register read" "Ignored,Normal" bitfld.long 0x04 6. " LRR ,Lock register read" "Ignored,Normal" bitfld.long 0x04 5. " SRR ,Status register read" "Ignored,Normal" bitfld.long 0x04 4. " CRR ,Control register read" "Ignored,Normal" textline " " bitfld.long 0x04 3. " TCRR ,Time compensation register read" "Ignored,Normal" bitfld.long 0x04 2. " TARR ,Time alarm register read" "Ignored,Normal" bitfld.long 0x04 1. " TPRR ,Time prescaler register read" "Ignored,Normal" bitfld.long 0x04 0. " TSRR ,Time seconds register read" "Ignored,Normal" width 0x0B tree.end tree.end tree.open "Communication Interfaces" tree "ENET (10/100-Mbps Ethernet MAC)" base ad:0x400c0000 width 8. tree "Configuration Registers" group.long 0x04++0x07 line.long 0x00 "EIR,Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Completed" eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" eventfld.long 0x00 21. " LC ,Late collision (in half-duplex mode)" "Not occurred,Occurred" eventfld.long 0x00 20. " RL ,Collision retry limit (in half-duplex mode)" "Not occurred,Occurred" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" newline eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node wake-up request" "Not requested,Requested" eventfld.long 0x00 16. " TS_AVAIL ,Transmit timestamp available" "Not available,Available" eventfld.long 0x00 15. " TS_TIMER ,Timestamp timer" "Not reached,Reached" line.long 0x04 "EIMR,Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,Babbling receive error interrupt mask" "Masked,Not masked" bitfld.long 0x04 29. " BABT ,Babbling transmit error interrupt mask" "Masked,Not masked" bitfld.long 0x04 28. " GRA ,Graceful stop complete interrupt mask" "Masked,Not masked" bitfld.long 0x04 27. " TXF ,Transmit frame interrupt mask" "Masked,Not masked" newline bitfld.long 0x04 26. " TXB ,Transmit buffer interrupt mask" "Masked,Not masked" bitfld.long 0x04 25. " RXF ,Receive frame interrupt mask" "Masked,Not masked" bitfld.long 0x04 24. " RXB ,Receive buffer interrupt mask" "Masked,Not masked" bitfld.long 0x04 23. " MII ,MII interrupt mask" "Masked,Not masked" newline bitfld.long 0x04 22. " EBERR ,Ethernet bus error interrupt mask" "Masked,Not masked" bitfld.long 0x04 21. " LC ,Late collision interrupt mask" "Masked,Not masked" bitfld.long 0x04 20. " RL ,Collision Retry Limit Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 19. " UN ,Transmit FIFO underrun interrupt mask" "Masked,Not masked" newline bitfld.long 0x04 18. " PLR ,Payload Receive Error Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 17. " WAKEUP ,Node wake-up request interrupt mask" "Masked,Not masked" bitfld.long 0x04 16. " TS_AVAIL ,Transmit timestamp available interrupt mask" "Masked,Not masked" bitfld.long 0x04 15. " TS_TIMER ,Timestamp timer interrupt mask" "Masked,Not masked" group.long 0x10++0x07 line.long 0x00 "RDAR,Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive descriptor active" "Inactive,Active" line.long 0x04 "TDAR,Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit descriptor active" "Inactive,Active" group.long 0x24++0x03 line.long 0x00 "ECR,Ethernet Control Register" sif !cpuis("MK60D*AB10")&&!cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 8. " DBSWP ,Descriptor byte swapping enable" "Disabled,Enabled" newline endif bitfld.long 0x00 7. " STOPEN ,STOPEN signal control (in doze mode)" "Disabled,Enabled" bitfld.long 0x00 6. " DBGEN ,Debug enable" "Debug,Freeze" bitfld.long 0x00 4. " EN1588 ,EN1588 enable" "Disabled,Enabled" bitfld.long 0x00 3. " SLEEP ,Sleep mode enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " MAGICEN ,Magic packet detection enable (in sleep mode)" "Disabled,Enabled" bitfld.long 0x00 1. " ETHEREN ,Ethernet enable" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Ethernet MAC reset" "No reset,Reset" newline group.long 0x40++0x07 line.long 0x00 "MMFR,MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "0,1,2,3" bitfld.long 0x00 28.--29. " OP ,Operation code" "Write(not MII),Write(MII),Read(MII),Read(not MII)" bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 16.--17. " TA ,Turn around" "00,01,10,11" hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "MSCR,MII Speed Control Register" sif cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 internal bus cycle,2 internal bus cycles,3 internal bus cycles,4 internal bus cycles,5 internal bus cycles,6 internal bus cycles,7 internal bus cycles,8 internal bus cycles" newline elif cpuis("MK70*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 internal bus cycle,2 internal bus cycles,3 internal bus cycles,,,,,8 internal bus cycles" newline else bitfld.long 0x04 8.--10. " HOLDTIME ,Holdtime on MDIO output" "1 internal bus cycle,2 internal bus cycles,3 internal bus cycles,4 internal bus cycles,5 internal bus cycles,6 internal bus cycles,7 internal bus cycles,8 internal bus cycles" newline endif bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" bitfld.long 0x04 1.--6. " MII_SPEED ,MII speed" "0,1/2,1/4,1/6,1/8,1/10,1/12,1/14,1/16,1/18,1/20,1/22,1/24,1/26,1/28,1/30,1/32,1/34,1/36,1/38,1/40,1/42,1/44,1/46,1/48,1/50,1/52,1/54,1/56,1/58,1/60,1/62,1/64,1/66,1/68,1/70,1/72,1/74,1/76,1/78,1/80,1/82,1/84,1/86,1/88,1/90,1/92,1/94,1/96,1/98,1/100,1/102,1/104,1/106,1/108,1/110,1/112,1/114,1/116,1/118,1/120,1/122,1/124,1/126" group.long 0x64++0x03 line.long 0x00 "MIBC,MIB Control Register" bitfld.long 0x00 31. " MIB_DIS ,Disable MIB logic" "No,Yes" rbitfld.long 0x00 30. " MIB_IDLE ,MIB idle" "Not idle,Idle" bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No effect,Cleared" group.long 0x84++0x03 line.long 0x00 "RCR,Receive Control Register" rbitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NLC ,Payload length check disable" "Disabled,Enabled" hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CFEN ,MAC control frame enable" "Disabled,Enabled" newline bitfld.long 0x00 14. " CRCFWD ,Terminate/forward received CRC" "Transmitted,Stripped" bitfld.long 0x00 13. " PAUFWD ,Terminate/forward pause frames" "Terminated,Forwarded" bitfld.long 0x00 12. " PADEN ,Enable frame padding remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,Enable 10-Mbps mode of the RMII" "100 Mbps,10 Mbps" newline bitfld.long 0x00 8. " RMII_MODE ,RMII mode enable" "MII,RMII" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Not rejected,Rejected" bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" newline bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" ",MII/RMII" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" sif cpuis("MK70*")||(cpu()=="MK53DN512ZCLQ10")||(cpu()=="MK53DN512ZCMD10")||(cpu()=="MK53DX256ZCLQ10")||(cpu()=="MK53DX256ZCMD10")||(cpu()=="MK52DN512ZCLQ10")||(cpu()=="MK52DN512ZCMD10")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x400c0000+0x24)&0x02)==0x00)) rgroup.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Not expecting,Expecting" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not overwritten,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" newline bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Not expecting,Expecting" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not overwritten,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" newline bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" rbitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif else group.long 0xC4++0x03 line.long 0x00 "TCR,Transmit Control Register" bitfld.long 0x00 9. " CRCFWD ,Forward frame from application with CRC" "Not expecting,Expecting" bitfld.long 0x00 8. " ADDINS ,Set MAC address on transmit" "Not overwritten,Overwritten" bitfld.long 0x00 5.--7. " ADDSEL ,Source MAC address select on transmit" "PADDR1/2,?..." rbitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Not paused,Paused" newline bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Not paused,Paused" bitfld.long 0x00 2. " FDEN ,Full duplex enable" "Disabled,Enabled" bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" endif group.long 0xE4++0x0B line.long 0x00 "PALR,Physical Address Lower Register" line.long 0x04 "PAUR,Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 0x01 " PADDR2 ,Upper 2 bytes of the 48-bit address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "OPD,Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPCODE ,Opcode field in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause duration" group.long 0x118++0x0F line.long 0x00 "IAUR,Descriptor Individual Upper Address Register" line.long 0x04 "IALR,Descriptor Individual Lower Address Register" line.long 0x08 "GAUR,Descriptor Group Upper Address Register" line.long 0x0c "GALR,Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "TFWR,Transmit FIFO Watermark Register" bitfld.long 0x00 8. " STRFWD ,Store and forward enable" "Disabled,Enabled" newline sif (cpuis("MK70*"))||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*VLQ*")||cpuis("MK60*VMD*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") sif cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64 bytes,64 bytes,128 bytes,192 bytes,256 bytes,320 bytes,384 bytes,448 bytes,512 bytes,576 bytes,640 bytes,704 bytes,768 bytes,832 bytes,896 bytes,960 bytes,1024 bytes,1088 bytes,1152 bytes,1216 bytes,1280 bytes,1344 bytes,1408 bytes,1472 bytes,1536 bytes,1600 bytes,1664 bytes,1728 bytes,1792 bytes,1856 bytes,1920 bytes,1984 bytes,?..." endif else bitfld.long 0x00 0.--5. " TFWR ,Transmit FIFO write" "64 bytes,64 bytes,128 bytes,192 bytes,256 bytes,320 bytes,384 bytes,448 bytes,512 bytes,576 bytes,640 bytes,704 bytes,768 bytes,832 bytes,896 bytes,960 bytes,1024 bytes,1088 bytes,1152 bytes,1216 bytes,1280 bytes,1344 bytes,1408 bytes,1472 bytes,1536 bytes,1600 bytes,1664 bytes,1728 bytes,1792 bytes,1856 bytes,1920 bytes,1984 bytes,2048 bytes,2112 bytes,2176 bytes,2240 bytes,2304 bytes,2368 bytes,2432 bytes,2496 bytes,2560 bytes,2624 bytes,2688 bytes,2752 bytes,2816 bytes,2880 bytes,2944 bytes,3008 bytes,3072 bytes,3136 bytes,3200 bytes,3264 bytes,3328 bytes,3392 bytes,3456 bytes,3520 bytes,3584 bytes,3648 bytes,3712 bytes,3776 bytes,3840 bytes,3904 bytes,3968 bytes,4032 bytes" endif group.long 0x180++0x0B line.long 0x00 "RDSR,Receive Descriptor Ring Start Register" hexmask.long 0x00 3.--31. 0x08 " R_DES_START ,Pointer to the start of the receive buffer descriptor queue" line.long 0x04 "TDSR,Transmit Buffer Descriptor Ring Start Register" hexmask.long 0x04 3.--31. 0x08 " X_DES_START ,Pointer to the start of the transmit buffer descriptor queue" line.long 0x08 "MRBR,Maximum Receive Buffer Size Register" sif cpuis("MK65*")||cpuis("MK66*")||cpuis("MK70*")||cpuis("MK60*VLQ*")||cpuis("MK60*VMD*")||cpuis("MK63FN1M0VLQ12R")||cpuis("KK65FN2M0CAC18R") hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" else hexmask.long.word 0x08 4.--13. 1. " R_BUF_SIZE ,Receive buffer size in bytes" endif group.long 0x190++0x23 line.long 0x00 "RSFL,Receive FIFO Section Full Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " RX_SECTION_FULL ,Value of receive FIFO section full threshold" line.long 0x04 "RSEM,Receive FIFO Section Empty Threshold Register" sif cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*VLQ*")||cpuis("MK60*VMD*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x04 16.--20. " STAT_SECTION_EMPTY ,RX Status FIFO section empty threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif hexmask.long.byte 0x04 0.--7. 1. " RX_SECTION_EMPTY ,Value of the receive FIFO section empty threshold" line.long 0x08 "RAEM,Receive FIFO Almost Empty Threshold Register" hexmask.long.byte 0x08 0.--7. 1. " RX_ALMOST_EMPTY ,Value of the receive FIFO almost empty threshold" line.long 0x0c "RAFL,Receive FIFO Almost Full Threshold Register" hexmask.long.byte 0x0c 0.--7. 1. " RX_ALMOST_FULL ,Value of the receive FIFO almost full threshold" line.long 0x10 "TSEM,Transmit FIFO Section Empty Threshold Register" hexmask.long.byte 0x10 0.--7. 1. " TX_SECTION_EMPTY ,Value of the transmit FIFO section empty threshold" line.long 0x14 "TAEM,Transmit FIFO Almost Empty Threshold Register" hexmask.long.byte 0x14 0.--7. 1. " TX_ALMOST_EMPTY ,Value of the transmit FIFO almost empty threshold" line.long 0x18 "TAFL,Transmit FIFO Almost Full Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " TX_ALMOST_FULL ,Value of the transmit FIFO almost full threshold" line.long 0x1C "TIPG,Transmit Inter-Packet Gap Register" sif cpuis("MK70*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*VLQ*")||cpuis("MK60*VMD*")||cpuis("KK60FN1M0VLQ15")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x1c 0.--4. " IPG ,Transmit inter-packet gap" "12,12,12,12,12,12,12,12,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,12,12,12,12,12" else bitfld.long 0x1c 0.--4. " IPG ,Transmit inter-packet gap" "8,8,8,8,8,8,8,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,27,27,27,27" endif line.long 0x20 "FTRL,Frame Truncation Length Register" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame truncation length" group.long 0x1C0++0x07 line.long 0x00 "TACC,Transmit Accelerator Function Configuration Register" bitfld.long 0x00 4. " PROCHK ,Insertion of protocol checksum enable" "Disabled,Enabled" bitfld.long 0x00 3. " IPCHK ,Insertion of IP header checksum enable" "Disabled,Enabled" bitfld.long 0x00 0. " SHIFT16 ,TX FIFO shift-16 enable" "Disabled,Enabled" line.long 0x04 "RACC,Receive Accelerator Function Configuration Register" bitfld.long 0x04 7. " SHIFT16 ,RX FIFO shift-16 enable" "Disabled,Enabled" bitfld.long 0x04 6. " LINEDIS ,Discard of frames with MAC layer errors enable" "Disabled,Enabled" bitfld.long 0x04 2. " PRODIS ,Discard of frames with wrong protocol checksum enable" "Disabled,Enabled" bitfld.long 0x04 1. " IPDIS ,Discard of frames with wrong IPv4 header checksum enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " PADREM ,Padding removal for short IP frames enable" "Disabled,Enabled" tree.end tree "1588 Timer" group.long 0x400++0x17 line.long 0x00 "ATCR,Timer Control Register" bitfld.long 0x00 13. " SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "Not captured,Captured" bitfld.long 0x00 9. " RESTART ,Reset timer" "No reset,Reset" bitfld.long 0x00 7. " PINPER ,Enables MAC output assertion on period event" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEREN ,Enable periodical event" "Disabled,Enabled" bitfld.long 0x00 3. " OFFRST ,Reset timer on offset event" "No reset,Reset" bitfld.long 0x00 2. " OFFEN ,Enable one-shot offset event" "Disabled,Enabled" bitfld.long 0x00 0. " EN ,Enable timer" "Disabled,Enabled" line.long 0x04 "ATVR,Timer Value Register" line.long 0x08 "ATOFF,Timer Offset Register" line.long 0x0c "ATPER,Timer Period Register" line.long 0x10 "ATCOR,Timer Correction Register" hexmask.long 0x10 0.--30. 1. " COR ,Correction counter wrap-around value" line.long 0x14 "ATINC,Time-Stamping Clock Period Register" hexmask.long.byte 0x14 8.--14. 1. " INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " INC ,Clock period of the timestamping clock (ts_clk) in ns" if ((per.l(ad:0x400c0000+0x4)&0x10000)==0x10000) group.long 0x418++0x3 line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame Register" else hgroup.long 0x418++0x3 hide.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame Register" endif tree.end tree "Capture/Compare Block" width 8. group.long 0x604++0x03 line.long 0x00 "TGSR,Timer Global Status Register" eventfld.long 0x00 3. " TF3 ,Copy of timer flag for channel 3" "Cleared,Set" eventfld.long 0x00 2. " TF2 ,Copy of timer flag for channel 2" "Cleared,Set" eventfld.long 0x00 1. " TF1 ,Copy of timer flag for channel 1" "Cleared,Set" eventfld.long 0x00 0. " TF0 ,Copy of timer flag for channel 0" "Cleared,Set" newline group.long 0x608++0x07 line.long 0x00 "TCSR0,Timer Control Status Register 0" eventfld.long 0x00 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture on rising edge,Input Capture on falling edge,Input Capture on both edges,Output Compare - software only,Output Compare - toggle on compare,Output Compare - clear on compare,Output Compare - set on compare,,Output Compare - set on compare/clear on overflow,Output Compare - clear on compare/set on overflow,Output Compare - set on compare/clear on overflow,,,Output Compare - pulse low on compare for one 1588 clock cycle,Output Compare - pulse high on compare for one 1588 clock cycle" newline bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR0,Timer Compare Capture Register 0" group.long 0x610++0x07 line.long 0x00 "TCSR1,Timer Control Status Register 1" eventfld.long 0x00 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture on rising edge,Input Capture on falling edge,Input Capture on both edges,Output Compare - software only,Output Compare - toggle on compare,Output Compare - clear on compare,Output Compare - set on compare,,Output Compare - set on compare/clear on overflow,Output Compare - clear on compare/set on overflow,Output Compare - set on compare/clear on overflow,,,Output Compare - pulse low on compare for one 1588 clock cycle,Output Compare - pulse high on compare for one 1588 clock cycle" newline bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR1,Timer Compare Capture Register 1" group.long 0x618++0x07 line.long 0x00 "TCSR2,Timer Control Status Register 2" eventfld.long 0x00 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture on rising edge,Input Capture on falling edge,Input Capture on both edges,Output Compare - software only,Output Compare - toggle on compare,Output Compare - clear on compare,Output Compare - set on compare,,Output Compare - set on compare/clear on overflow,Output Compare - clear on compare/set on overflow,Output Compare - set on compare/clear on overflow,,,Output Compare - pulse low on compare for one 1588 clock cycle,Output Compare - pulse high on compare for one 1588 clock cycle" newline bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR2,Timer Compare Capture Register 2" group.long 0x620++0x07 line.long 0x00 "TCSR3,Timer Control Status Register 3" eventfld.long 0x00 7. " TF ,Timer flag" "Not occurred,Occurred" bitfld.long 0x00 6. " TIE ,Timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2.--5. " TMODE ,Timer mode" "Disabled,Input Capture on rising edge,Input Capture on falling edge,Input Capture on both edges,Output Compare - software only,Output Compare - toggle on compare,Output Compare - clear on compare,Output Compare - set on compare,,Output Compare - set on compare/clear on overflow,Output Compare - clear on compare/set on overflow,Output Compare - set on compare/clear on overflow,,,Output Compare - pulse low on compare for one 1588 clock cycle,Output Compare - pulse high on compare for one 1588 clock cycle" newline bitfld.long 0x00 0. " TDRE ,Timer DMA request enable" "Disabled,Enabled" line.long 0x04 "TCCR3,Timer Compare Capture Register 3" tree.end sif (!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")) tree "Statistic Event Counters" width 20. sif (cpuis("MK70*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*")) base ad:0x400c0000+0x204 else base ad:0x400c0000+0x200 endif rgroup.long 0x00++0x43 line.long 0x00 "RMON_T_PACKETS,RMON Tx Packet Count Register" hexmask.long.word 0x00 0.--15. 1. " RMON_T_PACKETS ,RMON Tx packet count" line.long 0x04 "RMON_T_BC_PKT,RMON Tx Broadcast Packets Register" hexmask.long.word 0x04 0.--15. 1. " RMON_T_BC_PKT ,RMON Tx broadcast packets" line.long 0x08 "RMON_T_MC_PKT,RMON Tx Multicast Packets Register" hexmask.long.word 0x08 0.--15. 1. " RMON_T_MC_PKT ,RMON Tx multicast packets" line.long 0x0C "RMON_T_CRC_ALIGN,RMON Tx Packets CRC/Align Error Register" hexmask.long.word 0x0C 0.--15. 1. " RMON_T_CRC_ALIGN ,RMON Tx packets crc/align error" line.long 0x10 "RMON_T_UNDERSIZE,RMON Tx Packets 64 bytes Good CRC Register" hexmask.long.word 0x10 0.--15. 1. " RMON_T_UNDERSIZE ,RMON Tx packets 64 bytes good CRC" line.long 0x14 "RMON_T_OVERSIZE,Good CRC Register" hexmask.long.word 0x14 0.--15. 1. " RMON_T_OVERSIZE ,Good CRC" line.long 0x18 "RMON_T_FRAG,Bad CRC Register" hexmask.long.word 0x18 0.--15. 1. " RMON_T_FRAG ,Bad CRC" line.long 0x1C "RMON_T_JAB,Bad CRC Register" hexmask.long.word 0x1C 0.--15. 1. " RMON_T_JAB ,Bad CRC" line.long 0x20 "RMON_T_COL,RMON Tx Collision Count Register" hexmask.long.word 0x20 0.--15. 1. " RMON_T_COL ,RMON Tx collision count" line.long 0x24 "RMON_T_P64,RMON Tx 64 Byte Packets Register" hexmask.long.word 0x24 0.--15. 1. " RMON_T_P64 ,RMON Tx 64 byte packets" line.long 0x28 "RMON_T_P65TO127,RMON Tx 65 to 127 Byte Packets Register" hexmask.long.word 0x28 0.--15. 1. " RMON_T_P65TO127n ,RMON Tx 65 to 127 byte packets" line.long 0x2C "RMON_T_P128TO255,RMON Tx 128 to 255 Byte Packets Register" hexmask.long.word 0x2C 0.--15. 1. " RMON_T_P128TO255n ,RMON Tx 128 to 255 byte packets" line.long 0x30 "RMON_T_P256TO511,RMON Tx 256 to 511 Byte Packets Register" hexmask.long.word 0x30 0.--15. 1. " RMON_T_P256TO511 ,RMON Tx 256 to 511 byte packets" line.long 0x34 "RMON_T_P512TO1023,RMON Tx 512 to 1023 Byte Packets Register" hexmask.long.word 0x34 0.--15. 1. " RMON_T_P512TO1023 ,RMON Tx 512 to 1023 byte packets" line.long 0x38 "RMON_T_P1024TO2047,RMON Tx 1024 to 2047 Byte Packets Register" hexmask.long.word 0x38 0.--15. 1. " RMON_T_P1024TO2047 ,RMON Tx 1024 to 2047 byte packets" line.long 0x3C "RMON_T_P_GTE2048,RMON Tx Packets 2048 Bytes Register" hexmask.long.word 0x3C 0.--15. 1. " RMON_T_P_GTE2048 ,RMON Tx packets 2048 bytes" line.long 0x40 "RMON_T_OCTETS,RMON Tx Octets Register" sif (!cpuis("MK70*")&&!cpuis("MK66*")&&!cpuis("MK65*")&&!cpuis("MK63*")&&!cpuis("MK60*")) rgroup.long 0x48++0x03 line.long 0x00 "IEEE_T_DROP,Count of Frames Not Counted Correctly Register" hexmask.long.word 0x00 0.--15. 1. " IEEE_T_DROP ,Count of frames not counted correctly" endif base ad:0x400c0000+0x200 rgroup.long 0x4C++0x2F line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Register" hexmask.long.word 0x00 0.--15. 1. " IEEE_T_FRAME_OK ,Frames transmitted OK" line.long 0x04 "IEEE_T_1COL,Frames Transmitted with Single Collision Register" hexmask.long.word 0x04 0.--15. 1. " IEEE_T_1COL ,Frames transmitted with single collision" line.long 0x08 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Register" hexmask.long.word 0x08 0.--15. 1. " IEEE_T_MCOL ,Frames transmitted with multiple collisions" line.long 0x0C "IEEE_T_DEF,Frames Transmitted after Deferral Delay Register" hexmask.long.word 0x0C 0.--15. 1. " IEEE_T_DEF ,Frames transmitted after deferral delay" line.long 0x10 "IEEE_T_LCOL,Frames Transmitted with Late Collision Register" hexmask.long.word 0x10 0.--15. 1. " IEEE_T_LCOL ,Frames transmitted with late collision" line.long 0x14 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Register" hexmask.long.word 0x14 0.--15. 1. " IEEE_T_EX-COL ,Frames transmitted with excessive collisions" line.long 0x18 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Register" hexmask.long.word 0x18 0.--15. 1. " IEEE_T_MAC-ERR ,Frames transmitted with Tx FIFO underrun" line.long 0x1C "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Register" hexmask.long.word 0x1C 0.--15. 1. " IEEE_T_CSERR ,Frames transmitted with carrier sense error" line.long 0x20 "IEEE_T_SQE,Frames Transmitted with SQE Error Register" hexmask.long.word 0x20 0.--15. 1. " IEEE_T_SQE ,Frames transmitted with SQE error" line.long 0x24 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Register" hexmask.long.word 0x24 0.--15. 1. " IEEE_T_FDXFC ,Flow control pause frames transmitted" line.long 0x28 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted Error Register" line.long 0x2C "RMON_R_PACKETS,RMON Rx Packet Count Register" hexmask.long.word 0x2C 0.--15. 1. " RMON_R_PACKETS ,RMON Rx packet count" sif (cpuis("MK70*")||cpuis("MK66*")||cpuis("MK65*")||cpuis("MK63*")||cpuis("MK60*")) base ad:0x400c0000+0x204 else base ad:0x400c0000+0x200 endif rgroup.long 0x84++0x1B line.long 0x00 "RMON_R_BC_PKT,RMON Rx Broadcast Packets Register" hexmask.long.word 0x00 0.--15. 1. " RMON_R_BC_PKT ,RMON Rx broadcast packets" line.long 0x04 "RMON_R_MC_PKT,RMON Rx Multicast Packets Register" hexmask.long.word 0x04 0.--15. 1. " RMON_R_MC_PKT ,RMON Rx multicast packets" line.long 0x08 "RMON_R_CRC_ALIGN,RMON Rx Packets CRC/Align Error Register" hexmask.long.word 0x08 0.--15. 1. " RMON_R_CRC_ALIGN ,RMON Rx packets crc/align error" line.long 0x0c "RMON_R_UNDERSIZE,Good CRC Register" hexmask.long.word 0x0C 0.--15. 1. " RMON_R_UNDERSIZE ,Good CRC" line.long 0x10 "RMON_R_OVERSIZE,Good CRC Register" hexmask.long.word 0x10 0.--15. 1. " RMON_R_OVERSIZE ,Good CR" line.long 0x14 "RMON_R_FRAG,Bad CRC Register" hexmask.long.word 0x14 0.--15. 1. " RMON_R_FRAG ,Bad CRC" line.long 0x18 "RMON_R_JAB,Bad CRC Register" hexmask.long.word 0x18 0.--15. 1. " RMON_R_JAB ,Bad CRC" rgroup.long 0xA4++0x3B line.long 0x00 "RMON_R_P64,RMON Rx 64 Byte Packets Register" hexmask.long.word 0x00 0.--15. 1. " RMON_R_P64 ,RMON Rx 64 byte packets" line.long 0x04 "RMON_R_P65TO127,RMON Rx 65 to 127 Byte Packets Register" hexmask.long.word 0x04 0.--15. 1. " RMON_R_P65TO127 ,RMON Rx 65 to 127 byte packets" line.long 0x08 "RMON_R_P128TO255,RMON Rx 128 to 255 Byte Packets Register" hexmask.long.word 0x08 0.--15. 1. " RMON_R_P128TO255 ,RMON Rx 128 to 255 byte packets" line.long 0x0C "RMON_R_P256TO511,RMON Rx 256 to 511 Byte Packets Register" hexmask.long.word 0x0C 0.--15. 1. " RMON_R_P256TO511 ,RMON Rx 256 to 511 byte packets" line.long 0x10 "RMON_R_P512TO1023,RMON Rx 512 to 1023 Byte Packets Register" hexmask.long.word 0x10 0.--15. 1. " RMON_R_P512TO1023 ,RMON Rx 512 to 1023 byte packets" line.long 0x14 "RMON_R_P1024TO2047,RMON Rx 1024 to 2047 Byte Backets Register" hexmask.long.word 0x14 0.--15. 1. " RMON_R_P1024TO2047 ,RMON Rx 1024 to 2047 byte packets" line.long 0x18 "RMON_R_P_GTE2048,RMON Rx Packets 2048 Bytes Register" hexmask.long.word 0x18 0.--15. 1. " RMON_R_P_GTE2048 ,RMON Rx packets 2048 bytes" line.long 0x1C "RMON_R_OCTETS,RMON Rx Octets Register" line.long 0x20 "IEEE_R_DROP,Count of Frames Not Counted Correctly Register" hexmask.long.word 0x20 0.--15. 1. " IEEE_R_DROP ,Count of frames not counted correctly" line.long 0x24 "IEEE_R_FRAME_OK,Frames Received OK Register" hexmask.long.word 0x24 0.--15. 1. " IEEE_R_FRAME_OK ,Frames received OK" line.long 0x28 "IEEE_R_CRC,Frames Received with CRC Error Register" hexmask.long.word 0x28 0.--15. 1. " IEEE_R_CRC ,Frames received with CRC error" line.long 0x2C "IEEE_R_ALIGN,Frames Received with Alignment Error Register" hexmask.long.word 0x2C 0.--15. 1. " IEEE_R_ALIGN ,Frames received with alignment error" line.long 0x30 "IEEE_R_MACERR,Receive Fifo Overflow Count Register" hexmask.long.word 0x30 0.--15. 1. " IEEE_R_MACERR ,Receive Fifo overflow count" line.long 0x34 "IEEE_R_FDXFC,Flow Control Pause Frames Received Register" hexmask.long.word 0x34 0.--15. 1. " IEEE_R_FDXFC ,Flow control pause frames received" line.long 0x38 "IEEE_R_OCTETS_OK,Octet Count for Frames Rcvd Error Register" tree.end endif width 11. tree.end tree "USBOTG (Universal Serial Bus OTG Controller)" base ad:0x40072000 width 10. rgroup.byte 0x00++0x00 line.byte 0x00 "PERID,Peripheral ID Register" hexmask.byte 0x00 0.--5. 1. " ID ,Peripheral identification" rgroup.byte 0x04++0x00 line.byte 0x00 "IDCOMP,Peripheral ID Complement Register" hexmask.byte 0x00 0.--5. 1. " NID ,Ones complement of peripheral identification" rgroup.byte 0x08++0x00 line.byte 0x00 "REV,Peripheral Revision Register" rgroup.byte 0x0C++0x00 line.byte 0x00 "ADDINFO,Peripheral Additional Info Register" sif !cpuis("MK26FN*")&&!cpuis("MK22FN128*")&&!cpuis("MK22FN256*")&&!cpuis("MK21F*AVMC12")&&!cpuis("MK21D*AVMC5")&&!cpuis("MK21F*AVLQ12")&&!cpuis("MK21F*AVMD12")&&!cpuis("MK21D*AVLK5")&&!cpuis("MK65F*")&&!cpuis("MK66F*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MKS2?FN???V??12")&&!cpuis("MK21D*AVMC5R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 3.--7. " IRQ_NUM ,Assigned interrupt request number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline endif bitfld.byte 0x00 0. " IEHOST ,Host mode enable" "Disabled,Enabled" sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||(cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12"))||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN256VDC12")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") sif cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R")||cpuis("MK63FN1M0VLQ12R") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" bitfld.byte 0x00 7. " ID_CHG ,ID Signal from USB connector change interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline bitfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" else group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 7. " ID_CHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " SESS_VLD_CHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " A_VBUS_CHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" eventfld.byte 0x00 6. " ONE_MSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" else group.byte 0x10++0x00 line.byte 0x00 "OTGISTAT,OTG Interrupt Status Register" bitfld.byte 0x00 7. " IDCHG ,ID signal from USB connector change interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 6. " ONEMSEC ,1 millisecond timer expired interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 5. " LINE_STATE_CHG ,USB line state change interrupt" "No interrupt,Interrupt" newline bitfld.byte 0x00 3. " SESSVLDCHG ,VBUS change indicating session valid/invalid interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 2. " B_SESS_CHG ,VBUS change on B device interrupt" "No interrupt,Interrupt" bitfld.byte 0x00 0. " AVBUSCHG ,VBUS change on A device interrupt" "No interrupt,Interrupt" endif sif cpuis("MK8?FN256V*") group.byte 0x14++0x00 line.byte 0x00 "OTGICR,OTG Interrupt Control Register" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled" else group.byte 0x14++0x00 line.byte 0x00 "OTGICR,OTG Interrupt Control Register" bitfld.byte 0x00 7. " ID_EN ,ID interrupt enable" "Disabled,Enabled" newline sif !cpuis("MK84FN2M0CAU15R")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MKS2?FN???V??12")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK63FN1M0VLQ12R") bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_EN ,Line state change interrupt enable" "Disabled,Enabled" newline endif bitfld.byte 0x00 3. " SESS_VLD_EN ,Session valid interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " B_SESS_EN ,B session end interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " A_VBUS_EN ,A VBUS valid interrupt enable" "Disabled,Enabled" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN256VDC12") sif !cpuis("MK22FX512AVLK12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FX512AVLH12") sif cpuis("MK22FN256VLL12R")||cpuis("MK22FN128VLH10R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" elif cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Below valid trsh,Above valid trsh" newline bitfld.byte 0x00 2. " B_SESS_END ,B Session end" "Above end trsh,Below end trsh" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Below valid trsh,Above valid trsh" endif else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN128CAH12R")||cpuis("MK22FN256CAH12R")||cpuis("MK22FN256CAP12R")||cpuis("MK22FN256VMP12")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" elif cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FX512AVLH12")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" rbitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" elif cpuis("MK63FN1M0VLQ12R") group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 6. " ONEMSECEN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINESTATESTABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" else group.byte 0x18++0x00 line.byte 0x00 "OTGSTAT,OTG Status Register" bitfld.byte 0x00 7. " ID ,Current state of the ID pin on USB connector" "Type A cable,No/Type B cable" bitfld.byte 0x00 6. " ONE_MSEC_EN ,1 millisecond interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " LINE_STATE_STABLE ,LINE_STATE_CHG bit stable" "Not stable,Stable" newline bitfld.byte 0x00 3. " SESS_VLD ,Session valid" "Invalid,Valid" bitfld.byte 0x00 2. " B_SESS_END ,B session end" "Not end,End" bitfld.byte 0x00 0. " A_VBUS_VLD ,A VBUS valid" "Invalid,Valid" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40*Z*10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("MKS2?FN???V??12")||cpuis("KK22FN???CAH12R")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK27FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "D+ D- pull-down,Controlled by DP & DM" else group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "D+ pull-up,Controlled by DP & DM" endif else group.byte 0x1C++0x00 line.byte 0x00 "OTGCTL,OTG Control Register" bitfld.byte 0x00 7. " DP_HIGH ,D+ data line pull-up resistor enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DP_LOW ,D+ data line pull-down resistor enable" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_LOW ,D- data line pull-down resistor enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " OTG_EN ,On-The-Go pull-up/pull-down resistor enable" "Disabled,Enabled" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK27FN2M0VMI15")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FX512VMC12R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40D*Z*")||cpuis("MKS2?FN???V??12")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x80++0x00 line.byte 0x00 "ISTAT,Interrupt Status Register" eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 6. " ATTACH ,Attach interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (for 3ms) interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt" group.byte 0x84++0x00 line.byte 0x00 "INTEN,Interrupt Enable Register" bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled" group.byte 0x88++0x00 line.byte 0x00 "ERRSTAT,Error Interrupt Status Register" eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " BTO_ERR ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " EOF ,End of frame error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt" group.byte 0x8C++0x00 line.byte 0x00 "ERREN,Error Interrupt Enable Register" bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EOF_EN ,CRC5/EOF interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled" else group.byte 0x80++0x00 line.byte 0x00 "ISTAT,Interrupt Status Register" eventfld.byte 0x00 7. " STALL ,Stall interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 5. " RESUME ,Signal remote wake-up signaling interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " SLEEP ,Idle on USB bus (for 3ms) interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 3. " TOKDNE ,Token completed interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 2. " SOF_TOK ,Start of frame token interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " ERROR ,Error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 0. " USB_RST ,USB reset interrupt" "No interrupt,Interrupt" group.byte 0x84++0x00 line.byte 0x00 "INTEN,Interrupt Enable Register" bitfld.byte 0x00 7. " STALL_EN ,STALL interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 6. " ATTACH_EN ,ATTACH interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " RESUME_EN ,RESUME interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " SLEEP_EN ,SLEEP interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " TOK_DNE_EN ,TOK_DNE interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " SOF_TOK_EN ,SOF_TOK interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " ERROR_EN ,ERROR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " USB_RST_EN ,USB_RST interrupt enable" "Disabled,Enabled" group.byte 0x88++0x00 line.byte 0x00 "ERRSTAT,Error Interrupt Status Register" eventfld.byte 0x00 7. " BTS_ERR ,Bit stuff error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 5. " DMA_ERR ,DMA error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 4. " BTO ,Bus turnaround timeout error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 3. " DFN8 ,Data received was not 8 bits in length interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 2. " CRC16 ,CRC16 error interrupt" "No interrupt,Interrupt" eventfld.byte 0x00 1. " CRC5 ,CRC5 error interrupt" "No interrupt,Interrupt" newline eventfld.byte 0x00 0. " PID_ERR ,PID check failed interrupt" "No interrupt,Interrupt" group.byte 0x8C++0x00 line.byte 0x00 "ERREN,Error Interrupt Enable Register" bitfld.byte 0x00 7. " BTS_ERR_EN ,BTS_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 5. " DMA_ERR_EN ,DMA_ERR interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 4. " BTO_ERR_EN ,BTO_ERR interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 3. " DFN8_EN ,DFN8 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " CRC16_EN ,CRC16 interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " CRC5_EN ,CRC5/EOF interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " PID_ERR_EN ,PID_ERR interrupt enable" "Disabled,Enabled" endif endif sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FX512AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FX512AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FX512AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FX512AVLQ12")||cpuis("MK22FX512AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK40*Z*10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MKS2?FN???V??12")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if (((per.b(ad:0x40072000+0x80))&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Receive/Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" endif elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x80)&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" in endif else if ((per.b(ad:0x40072000+0x80)&0x08)==0x08) rgroup.byte 0x90++0x00 line.byte 0x00 "STAT,Status Register" hexmask.byte 0x00 4.--7. 0x10 " ENDP ,Endpoint address" bitfld.byte 0x00 3. " TX ,Transmit indicator" "Receive,Transmit" bitfld.byte 0x00 2. " ODD ,Last buffer descriptor in odd bank of BDT" "Even,Odd" else hgroup.byte 0x90++0x00 hide.byte 0x00 "STAT,Status Register" endif endif if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x94++0x00 line.byte 0x00 "CTL,Control Register" bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High" bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High" bitfld.byte 0x00 5. " TOKEN_BUSY ,USB module is busy executing a USB token" "Not busy,Busy" newline bitfld.byte 0x00 4. " RESET ,USB reset" "No reset,Reset" newline bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset" newline bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB enable" "Disabled,Enabled" else group.byte 0x94++0x00 line.byte 0x00 "CTL,Control Register" bitfld.byte 0x00 7. " JSTATE ,Live USB differential receiver JSTATE signal" "Low,High" bitfld.byte 0x00 6. " SE0 ,Live USB single ended zero signal" "Low,High" bitfld.byte 0x00 5. " TX_SUSPEND ,TXD_SUSPEND is set when the SIE has disabled packet transmission and reception" "No,Yes" newline newline bitfld.byte 0x00 3. " HOST_MODE_EN ,Host mode enable" "Disabled,Enabled" bitfld.byte 0x00 2. " RESUME ,Resume signaling enable" "Disabled,Enabled" bitfld.byte 0x00 1. " ODD_RST ,BDT ODD ping/pong bits reset" "No reset,Reset" newline bitfld.byte 0x00 0. " USB_EN_SOF_EN ,USB Enable" "Disabled,Enabled" endif group.byte 0x98++0x00 line.byte 0x00 "ADDR,Address Register" bitfld.byte 0x00 7. " LS_EN ,Low speed enable" "Disabled,Enabled" hexmask.byte 0x00 0.--6. 0x01 " ADDR ,USB address" group.byte 0x9C++0x00 line.byte 0x00 "BDTPAGE1,BDT Page Register 1" hexmask.byte 0x00 1.--7. 0x02 " BDT_BA[15:9] ,BDT base address bits [15:9]" group.byte 0xA0++0x00 line.byte 0x00 "FRMNUML,Frame Number Register Low" group.byte 0xA4++0x00 line.byte 0x00 "FRMNUMH,Frame Number Register High" bitfld.byte 0x00 0.--2. " FRM[10:8] ,Upper 3 bits of BDT system memory address" "0,1,2,3,4,5,6,7" sif cpuis("MK20DN512*AB10R")||cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63*")||cpuis("MK64*")||cpuis("MK65*")||cpuis("MK66*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK70FN1M0VMJ1*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN1M0VMC10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK40*Z*10")||cpuis("MKS2?FN???V??12")||cpuis("MK20D????ZVLL10")||cpuis("MK20D????ZVLQ10*")||cpuis("MK20D????ZVMD10")||cpuis("MK20DN512ZVMC10*")||cpuis("MK20D????ZVLK10")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("MK21D*AVMC5R")||cpuis("MK21FN1M0AVMC12R")||cpuis("MK22FN1M0AVLK12R")||cpuis("KK22FN???C?P12R")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???CAH12R")||cpuis("MK22FN256VLL12R")||cpuis("MK22FN1M0VLQ12R")||cpuis("MK22FX512VLQ12R")||cpuis("MK22FX512VMD12R")||cpuis("MK22FN1M0VMC12R")||cpuis("MK22FX512VMC12R")||cpuis("MK22FN1M0VLK12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK65FN2M0CAC18R")||cpuis("KK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVLL10") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) if (((per.b(ad:0x40072000+0x94))&0x20)==0x20) rgroup.byte 0xA8++0x00 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." hexmask.byte 0x00 0.--3. 0x01 " TOKEN_ENDPT ,Endpoint address for the token command" else group.byte 0xA8++0x00 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." hexmask.byte 0x00 0.--3. 0x01 " TOKEN_ENDPT ,Endpoint address for the token command" endif group.byte 0xAC++0x00 line.byte 0x00 "SOFTHLD,SOF Threshold Register" else hgroup.byte 0xA8++0x00 hide.byte 0x00 "TOKEN,Token Register" hgroup.byte 0xAC++0x00 hide.byte 0x00 "SOFTHLD,SOF Threshold Register" endif else if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0xA8++0x0 line.byte 0x00 "TOKEN,Token Register" bitfld.byte 0x00 4.--7. " TOKEN_PID ,Token type" ",Out,,,,,,,,In,,,,Setup,?..." bitfld.byte 0x00 0.--3. " TOKEN_ENDPT ,Endpoint address for the token command" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" group.byte 0xAC++0x0 line.byte 0x00 "SOFTHLD,SOF Threshold Register" else hgroup.byte 0xA8++0x0 hide.byte 0x00 "TOKEN,Token Register" hgroup.byte 0xAC++0x0 hide.byte 0x00 "SOFTHLD,SOF Threshold Register" endif endif group.byte 0xB0++0x00 line.byte 0x00 "BDTPAGE2,BDT Page Register 2" group.byte 0xB4++0x00 line.byte 0x00 "BDTPAGE3,BDT Page Register 3" width 9. tree "Endpoints 0-15" if ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0xC0)&0x0C)==0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicate to directly connected low speed device" "Not directly,Directly or no LS dev" bitfld.byte 0x00 6. " RETRY_DIS ,Negative hardware acknowledgment transactions retry disable" "No,Yes" newline bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif ((per.b(ad:0x40072000+0x94)&0x08)==0x00)&&((per.b(ad:0x40072000+0xC0)&0x0C)==0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" newline bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif ((per.b(ad:0x40072000+0x94)&0x08)==0x08)&&((per.b(ad:0x40072000+0xC0)&0x0C)!=0x0C) group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" bitfld.byte 0x00 7. " HOST_WO_HUB ,Host communicate to directly connected low speed device" "Not directly,Directly or no LS dev" bitfld.byte 0x00 6. " RETRY_DIS ,Negative hardware acknowledgment transactions retry disable" "No,Yes" newline bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" newline else group.byte 0xC0++0x00 line.byte 0x00 "ENDPT0,Endpoint Control Register 0" newline bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xC4)&0x0C)==0x0C)) group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xC4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xC4)&0x0C)==0x04)) group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xC4++0x00 line.byte 0x00 "ENDPT1,Endpoint Control Register 1" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xC8)&0x0C)==0x0C)) group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xC8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xC8)&0x0C)==0x04)) group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xC8++0x00 line.byte 0x00 "ENDPT2,Endpoint Control Register 2" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xCC)&0x0C)==0x0C)) group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xCC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xCC)&0x0C)==0x04)) group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xCC++0x00 line.byte 0x00 "ENDPT3,Endpoint Control Register 3" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD0)&0x0C)==0x0C)) group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD0)&0x0C)==0x04)) group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD0++0x00 line.byte 0x00 "ENDPT4,Endpoint Control Register 4" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD4)&0x0C)==0x0C)) group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD4)&0x0C)==0x04)) group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD4++0x00 line.byte 0x00 "ENDPT5,Endpoint Control Register 5" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xD8)&0x0C)==0x0C)) group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xD8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xD8)&0x0C)==0x04)) group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xD8++0x00 line.byte 0x00 "ENDPT6,Endpoint Control Register 6" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xDC)&0x0C)==0x0C)) group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xDC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xDC)&0x0C)==0x04)) group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xDC++0x00 line.byte 0x00 "ENDPT7,Endpoint Control Register 7" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE0)&0x0C)==0x0C)) group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE0)&0x0C)==0x04)) group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE0++0x00 line.byte 0x00 "ENDPT8,Endpoint Control Register 8" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE4)&0x0C)==0x0C)) group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE4)&0x0C)==0x04)) group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE4++0x00 line.byte 0x00 "ENDPT9,Endpoint Control Register 9" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xE8)&0x0C)==0x0C)) group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xE8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xE8)&0x0C)==0x04)) group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xE8++0x00 line.byte 0x00 "ENDPT10,Endpoint Control Register 10" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xEC)&0x0C)==0x0C)) group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xEC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xEC)&0x0C)==0x04)) group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xEC++0x00 line.byte 0x00 "ENDPT11,Endpoint Control Register 11" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF0)&0x0C)==0x0C)) group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF0)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF0)&0x0C)==0x04)) group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF0++0x00 line.byte 0x00 "ENDPT12,Endpoint Control Register 12" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF4)&0x0C)==0x0C)) group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF4)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF4)&0x0C)==0x04)) group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF4++0x00 line.byte 0x00 "ENDPT13,Endpoint Control Register 13" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xF8)&0x0C)==0x0C)) group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xF8)&0x0C)==0x08)||((per.b(ad:0x40072000+0xF8)&0x0C)==0x04)) group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xF8++0x00 line.byte 0x00 "ENDPT14,Endpoint Control Register 14" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif if (((per.b(ad:0x40072000+0xFC)&0x0C)==0x0C)) group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 4. " EP_CTL_DIS ,Control (SETUP) transfers disable" "No,Yes" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" elif (((per.b(ad:0x40072000+0xFC)&0x0C)==0x08)||((per.b(ad:0x40072000+0xFC)&0x0C)==0x04)) group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 1. " EP_STALL ,Endpoint stall" "Not stalled,Stalled" bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" else group.byte 0xFC++0x00 line.byte 0x00 "ENDPT15,Endpoint Control Register 15" bitfld.byte 0x00 3. " EP_RX_EN ,Endpoint RX transfers enable" "Disabled,Enabled" bitfld.byte 0x00 2. " EP_TX_EN ,Endpoint TX transfers enable" "Disabled,Enabled" newline bitfld.byte 0x00 0. " EP_HSHK ,Endpoint handshaking enable" "Disabled,Enabled" endif tree.end newline sif cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") if ((per.b(ad:0x40072000+0x100)&0x10)==0x10) group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" else group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" newline bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select (USB DP/DM signals)" "UART TX/RX,UART RX/TX" bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" endif else group.byte 0x100++0x00 line.byte 0x00 "USBCTRL,USB Control Register" bitfld.byte 0x00 7. " SUSP ,USB transceiver suspend state" "Not suspended,Suspended" bitfld.byte 0x00 6. " PDE ,USB transceiver weak pull-downs enable" "Disabled,Enabled" sif !cpuis("MK20DX256VLQ10R")&&!cpuis("MK20FN1M0VLQ12R")&&!cpuis("MK20DX256VLK10R")&&!cpuis("MK21FX512VMD10")&&!cpuis("MK21FN1M0VMD10")&&!cpuis("MK21FN1M0VMC10")&&!cpuis("MK21FX512VMC10")&&!cpuis("MK20DX256VLK7R")&&!cpuis("MK20DX256VMC7R")&&!cpuis("MK22FN1M0AVLK12")&&!cpuis("MK22FX512AVLK12")&&!cpuis("MK22FN1M0VLK10")&&!cpuis("MK22FN1M0AVLL12")&&!cpuis("MK22FX512AVLL12")&&!cpuis("MK22FN1M0VLL10")&&!cpuis("MK22FN1M0AVMC12")&&!cpuis("MK22FX512AVMC12")&&!cpuis("MK22FN1M0AVLQ12")&&!cpuis("MK22FN1M0AVMD12")&&!cpuis("MK22FX512AVLQ12")&&!cpuis("MK22FX512AVMD12")&&!cpuis("MK22FN1M0VLQ10")&&!cpuis("MK22FX512AVLH12")&&!cpuis("MK22FN1M0AVLH12")&&!cpuis("MK22FN1M0VLH10")&&!cpuis("MK70FN1M0VMJ1*")&&!cpuis("MK22FN128CAH12R")&&!cpuis("MK22FN256CAH12R")&&!cpuis("MK22FN256CAP12R")&&!cpuis("MK22FN256VMP12")&&!cpuis("MK22FN512CAP12R")&&!cpuis("MK22FN512CBP12R")&&!cpuis("MK22FN512VDC12")&&!cpuis("MK22FN512VLH12")&&!cpuis("MK22FN512VLL12")&&!cpuis("MK22FN512VMP12")&&!cpuis("MK22FN1M0VMC10")&&!cpuis("MK20DN32VEX5")&&!cpuis("MK20DN64VEX5")&&!cpuis("MK20DN128VEX5")&&!cpuis("MK20DX32VEX5")&&!cpuis("MK20DX64VEX5")&&!cpuis("MK20DX128VEX5")&&!cpuis("MK20DX64VEX7")&&!cpuis("MK20DX128VEX7")&&!cpuis("MK20DX256VEX7")&&!cpuis("MK20DX64VMB7")&&!cpuis("MK20DX128VMB7")&&!cpuis("MK20DX256VMB7")&&!cpuis("MK24FN1M0CAJ12R")&&!cpuis("MK24FN1M0VDC12R")&&!cpuis("MK24FN1M0VLL12")&&!cpuis("MK24FN1M0VLL12R")&&!cpuis("MK24FN1M0VLQ12R")&&!cpuis("MK24FN256VDC12")&&!cpuis("MK40*Z*10")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK20D????ZVLQ10*")&&!cpuis("MK20D????ZVMD10")&&!cpuis("MK20D????ZVLL10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK20DN512VLK10R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK21D*AVMC5R")&&!cpuis("MK21FN1M0AVMC12R")&&!cpuis("MK22FN1M0AVLK12R")&&!cpuis("KK22FN???C?P12R")&&!cpuis("MK22FN512VDC12*")&&!cpuis("MK22FN512VFX12*")&&!cpuis("MK22FN512VLH12R")&&!cpuis("KK22FN???CAH12R")&&!cpuis("MK22FN256VLL12R")&&!cpuis("MK22FN1M0VLQ12R")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("MK22FN1M0VMC12R")&&!cpuis("MK22FX512VMC12R")&&!cpuis("MK22FX512AVLH12R")&&!cpuis("MK22FN128VLH10R")&&!cpuis("MK22FN1M0VLK12R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DX256ZCLQ10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("KK65FN2M0CAC18R") newline bitfld.byte 0x00 5. " UARTCHLS ,UART signal channel select (USB DP/DM signals)" "UART TX/RX,UART RX/TX" bitfld.byte 0x00 4. " UARTSEL ,Selects USB signals to be used as UART signals" "Not used,Used" endif endif rgroup.byte 0x104++0x00 line.byte 0x00 "OBSERVE,USB OTG Observe Register" bitfld.byte 0x00 7. " DP_PU ,D+ Pull up signal output observability" "Disabled,Enabled" bitfld.byte 0x00 6. " DP_PD ,D+ Pull down signal output observability" "Disabled,Enabled" bitfld.byte 0x00 4. " DM_PD ,D- Pull down signal output observability" "Disabled,Enabled" group.byte 0x108++0x00 line.byte 0x00 "CONTROL,USB OTG Control Register" bitfld.byte 0x00 4. " DPPULLUP_NONOTG ,DP Pull up in the USB OTG control" "Disabled,Enabled" sif (cpuis("MK6*"))||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("MK22FX512AVLH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("MK22FN512VDC12R")||cpuis("MK22FN512VFX12")||cpuis("MK22FN512VFX12R")||cpuis("MK22FN512VLH12R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R") group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" sif !cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" endif newline rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK28FN2M0CAU15R")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("MKS20FN128VFT12")||cpuis("MKS20FN128VLH12")||cpuis("MKS20FN128VLL12")||cpuis("MKS20FN256VFT12")||cpuis("MKS20FN256VLH12")||cpuis("MKS20FN256VLL12")||cpuis("MKS22FN128VFT12")||cpuis("MKS22FN128VLH12")||cpuis("MKS22FN128VLL12")||cpuis("MKS22FN256VFT12")||cpuis("MKS22FN256VLH12")||cpuis("MKS22FN256VLL12") if ((per.b(ad:0x40072000+0x12C)&0x18)==0x18) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif ((per.b(ad:0x40072000+0x12C)&0x18)==0x10) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 4. " VFEDG_DET ,VREGIN falling edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" elif ((per.b(ad:0x40072000+0x12C)&0x18)==0x08) group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 3. " VREDG_DET ,VREGIN rising edge interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" else group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline newline rbitfld.byte 0x00 2. " USB_CLK_RECOVERY_INT ,Combined USB clock recovery interrupt status" "No interrupt,Interrupt" rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" newline rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" endif else group.byte 0x10C++0x00 line.byte 0x00 "USBTRC0,USB Transceiver Control Register 0" bitfld.byte 0x00 7. " USBRESET ,USB_OTG module hard reset" "No reset,Reset" bitfld.byte 0x00 5. " USBRESMEN ,Asynchronous resume interrupt enable" "Disabled,Enabled" newline rbitfld.byte 0x00 1. " SYNC_DET ,Synchronous USB interrupt detect" "Not detected,Detected" rbitfld.byte 0x00 0. " USB_RESUME_INT ,USB asynchronous interrupt" "No interrupt,Interrupt" endif newline width 14. sif cpuis("MK21D*AVLK5")||cpuis("MK21F*AVLQ12")||cpuis("MK21F*AVMD12")||cpuis("MK21D*AVMC5")||cpuis("MK21F*AVMC12")||cpuis("MK22FX512*")||cpuis("MK22FN256*")||cpuis("MK22FN128*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK20DX256VLK10R")||cpuis("MK20DX256VMC7R")||cpuis("MK20DX256VLK7R")||cpuis("MK21FX512VMD10")||cpuis("MK21FN1M0VMD10")||cpuis("MK21FN1M0VMC10")||cpuis("MK21FX512VMC10")||cpuis("MK22FN1M0AVLK12")||cpuis("MK22FN1M0VLK10")||cpuis("MK22FN1M0AVLL12")||cpuis("MK22FN1M0VLL10")||cpuis("MK22FN1M0AVMC12")||cpuis("MK22FN1M0AVLQ12")||cpuis("MK22FN1M0AVMD12")||cpuis("MK22FN1M0VLQ10")||cpuis("MK22FN1M0AVLH12")||cpuis("MK22FN1M0VLH10")||cpuis("MK20DN32VEX5")||cpuis("MK20DN64VEX5")||cpuis("MK20DN128VEX5")||cpuis("MK20DX32VEX5")||cpuis("MK20DX64VEX5")||cpuis("MK20DX128VEX5")||cpuis("MK20DX64VEX7")||cpuis("MK20DX128VEX7")||cpuis("MK20DX256VEX7")||cpuis("MK20DX64VMB7")||cpuis("MK20DX128VMB7")||cpuis("MK20DX256VMB7")||cpuis("MK24FN1M0CAJ12R")||cpuis("MK24FN1M0VDC12R")||cpuis("MK24FN1M0VLL12")||cpuis("MK24FN1M0VLL12R")||cpuis("MK24FN1M0VLQ12R")||cpuis("MK24FN256VDC12")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif cpuis("MK22FX512VMC12R")||cpuis("MK22FX512AVLH12R")||cpuis("MK22FN128VLH10R")||cpuis("MK22FN256VLL12R") group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" else if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" else hgroup.byte 0x114++0x00 hide.byte 0x00 "USBFRMADJUST,Frame Adjust Register" endif endif elif !cpuis("MK?0DN*AB10")&&!cpuis("MK20DN512ZCAB10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK20D????ZVLL10")&&!cpuis("MK20D????ZVLQ10*")&&!cpuis("MK20D????ZVMD10")&&!cpuis("MK20DN512ZVMC10*")&&!cpuis("MK20D????ZVLK10")&&!cpuis("MK22FX512VLQ12R")&&!cpuis("MK22FX512VMD12R")&&!cpuis("KK20DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60DN512ZCAB10R") group.byte 0x114++0x00 line.byte 0x00 "USBFRMADJUST,Frame Adjust Register" endif sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0" bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times" else group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes" endif elif cpuis("MKS2?FN???V??12") if ((per.b(ad:0x40072000+0x94)&0x08)==0x08) group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 7. " STL_ADJ_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" newline bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 1. " SOFBUSSET ,SOF_TOK interrupt generation mode select" "SOF threshold value,Counter reaches 0" bitfld.byte 0x00 0. " SOFDYNTHLD ,Dynamic SOF threshold compare mode" "Byte time,8 byte times" else group.byte 0x12C++0x00 line.byte 0x00 "MISCCTRL,Miscellaneous Control register" bitfld.byte 0x00 4. " VFEDG_EN ,VREGIN falling edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 3. " VREDG_EN ,VREGIN rising edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " OWNERRISODIS ,OWN error detect for ISO IN / ISO OUT disable" "No,Yes" endif endif newline width 18. sif cpuis("MKS2?FN???V??12") if (((per.b(ad:0x40072000+0x94)&0x8)!=0x8)&&((per.b(ad:0x40072000+0x12C)&0x80)==0x80)) group.byte 0x130++0x00 line.byte 0x00 "STALL_IL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In IN Direction" bitfld.byte 0x00 7. " STALL_I_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_I_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_I_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_I_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_I_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_I_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_I_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_I_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x134++0x00 line.byte 0x00 "STALL_IH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 8 In IN Direction" bitfld.byte 0x00 7. " STALL_I_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_I_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_I_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_I_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_I_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_I_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_I_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_I_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x138++0x00 line.byte 0x00 "STALL_OL_DIS,Peripheral Mode Stall Disable For Endpoints 7 To 0 In OUT Direction" bitfld.byte 0x00 7. " STALL_O_DIS7 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_O_DIS6 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_O_DIS5 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_O_DIS4 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_O_DIS3 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_O_DIS2 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_O_DIS1 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_O_DIS0 ,Dynamic SOF threshold compare mode" "No,Yes" group.byte 0x13C++0x00 line.byte 0x00 "STALL_OH_DIS,Peripheral Mode Stall Disable For Endpoints 15 To 0 In OUT Direction" bitfld.byte 0x00 7. " STALL_O_DIS15 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 6. " STALL_O_DIS14 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 5. " STALL_O_DIS13 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 4. " STALL_O_DIS12 ,Dynamic SOF threshold compare mode" "No,Yes" newline bitfld.byte 0x00 3. " STALL_O_DIS11 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 2. " STALL_O_DIS10 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 1. " STALL_O_DIS9 ,Dynamic SOF threshold compare mode" "No,Yes" bitfld.byte 0x00 0. " STALL_O_DIS8 ,Dynamic SOF threshold compare mode" "No,Yes" endif endif newline width 28. sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") group.byte 0x140++0x00 line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset" newline bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart" group.byte 0x144++0x00 line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register" bitfld.byte 0x00 1. " IRC_EN ,IRC48M enable" "Disabled,Enabled" bitfld.byte 0x00 0. " REG_EN ,IRC48M regulator enable" "Disabled,Enabled" sif !cpuis("MK63F*")&&!cpuis("MK64F*") group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" elif cpuis("MK63FN1M0VLQ12R") group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" endif sif cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK63F*")||cpuis("MK64F*")||cpuis("MK65F*")||cpuis("MK66F*")||cpuis("MK27FN2M0VMI15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") group.byte 0x15C++0x00 line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" eventfld.byte 0x00 4. " OVF_ERROR ,USB clock recovery error flag" "No interrupt,Interrupt" else hgroup.byte 0x15C++0x00 hide.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" in endif elif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK22FN512CAP12R")||cpuis("MK22FN512CBP12R")||cpuis("MK22FN512VDC12")||cpuis("MK22FN512VLH12")||cpuis("MK22FN512VLL12")||cpuis("MK22FN512VMP12")||cpuis("MKS2?FN???V??12")||cpuis("MK22FN512VDC12*")||cpuis("MK22FN512VFX12*")||cpuis("MK22FN512VLH12R")||cpuis("KK22FN???C?P12R")||cpuis("KK22FN???CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK22FN128*")||cpuis("MK22FN256*") if ((per.b(ad:0x40072000+0x144)&0x02)==0x02) group.byte 0x140++0x00 line.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" bitfld.byte 0x00 7. " CLOCK_RECOVER_EN ,Crystal-less USB enable" "Disabled,Enabled" bitfld.byte 0x00 6. " RESET_RESUME_ROUGH_EN ,Reset/resume to rough phase enable" "Resume,Reset" newline bitfld.byte 0x00 5. " RESTART_IFRTRIM_EN ,Restart from IFR trim value" "No effect,Restart" else hgroup.byte 0x140++0x00 hide.byte 0x00 "CLK_RECOVER_CTRL,USB Clock Recovery Control Register" endif group.byte 0x144++0x00 line.byte 0x00 "CLK_RECOVER_IRC_EN,IRC48M Oscillator Enable Register" bitfld.byte 0x00 1. " IRC_EN ,IRC48M enable" "Disabled,Enabled" bitfld.byte 0x00 0. " REG_EN ,IRC48M regulator enable" "Disabled,Enabled" group.byte 0x154++0x00 line.byte 0x00 "CLK_RECOVER_INT_EN,Clock Recovery Combined Interrupt Enable Register" bitfld.byte 0x00 4. " OVF_ERROR_EN ,Determines whether OVF_ERROR condition signal is used in generation of USB_CLK_RECOVERY_INT" "Disabled,Enabled" group.byte 0x15C++0x00 line.byte 0x00 "CLK_RECOVER_INT_STATUS,Clock Recovery Separated Interrupt Status Register" eventfld.byte 0x00 4. " OVF_ERROR ,USB clock recovery error flag" "No interrupt,Interrupt" endif endif width 0x0B tree.end tree "USBDCD (USB Device Charger Detection Module)" base ad:0x40035000 width 9. group.long 0x00++0x07 line.long 0x00 "CONTROL,USBDCD Control Register" bitfld.long 0x00 25. " SR ,Software reset" "No reset,Reset" bitfld.long 0x00 24. " START ,Start change detection sequence" "No start,Start" newline sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") bitfld.long 0x00 17. " BC12 ,BC1.2 compatibility" "BC1.1,BC1.2" newline endif endif bitfld.long 0x00 16. " IE ,Interrupt enable" "Disabled,Enabled" rbitfld.long 0x00 8. " IF ,Interrupt flag" "Not pending,Pending" bitfld.long 0x00 0. " IACK ,Interrupt acknowledge" "No effect,Clear" line.long 0x04 "CLOCK,USBDCD Clock Register" hexmask.long.word 0x04 2.--11. 1. " CLOCK_SPEED ,Numerical value of clock speed in binary" bitfld.long 0x04 0. " CLOCK_UNIT ,Unit of measurement encoding for clock speed" "kHz,MHz" newline rgroup.long 0x08++0x03 line.long 0x00 "STATUS,USBDCD Status Register" bitfld.long 0x00 22. " ACTIVE ,Active status indicator" "Not running,Running" bitfld.long 0x00 21. " TO ,Timeout flag" "No timeout,Timeout" newline bitfld.long 0x00 20. " ERR ,Error flag" "No error,Error" newline bitfld.long 0x00 18.--19. " SEQ_STAT ,Charger detection sequence status" "Disabled / Data pins not detected,Data pin contact detection completed,Charger detection completed,Charger type detection completed" newline bitfld.long 0x00 16.--17. " SEQ_RES ,Charger detection sequence results" "No results,Standard host,Charging port,Dedicated charger" newline sif !cpuis("MK63*")&&!cpuis("MK64*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("MK60DN512ZVLL10") sif cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") width 17. group.long 0x0C++0x03 line.long 0x00 "SIGNAL_OVERRIDE,Signal Override Register" bitfld.long 0x00 0.--1. " PS ,Phase selection" "No overrides,,VDP_SRC enabled,?..." newline endif endif width 13. group.long 0x10++0x07 line.long 0x00 "TIMER0,USBDCD TIMER0 Register" hexmask.long.word 0x00 16.--25. 1. " TSEQ_INIT ,Sequence initiation time (in ms)" hexmask.long.word 0x00 0.--11. 1. " TUNIT_CON ,Unit connection timer elapse (in ms)" line.long 0x04 "TIMER1,USBDCD TIMER1 Register" hexmask.long.word 0x04 16.--25. 1. " TDCD_DBNC ,Time period to debounce D+ signal (in ms)" hexmask.long.word 0x04 0.--9. 1. " TVDPSRC_ON ,Time period comparator enabled (in ms)" sif !cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60FN1M0VLQ15")&&!cpuis("MK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVLL10")&&!cpuis("KK60FN1M0VLQ15")&&!cpuis("KK60DN512ZCAB10R") sif (cpuis("MK6*"))||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40035000+0x00))&0x20000)==0x20000) group.long 0x18++0x03 line.long 0x00 "TIMER2_BC12,USBDCD TIMER2_BC12 Register" hexmask.long.word 0x00 16.--25. 1. " TWAIT_AFTER_PRD ,Sets the amount of time (in ms) that the module waits after primary detection before start to secondary detection" hexmask.long.word 0x00 0.--9. 1. " TVDMSRC_ON ,Sets the amount of time (in ms) that the module enables the V DM_SRC" else group.long 0x18++0x03 line.long 0x00 "TIMER2_BC11,USBDCD TIMER2_BC11 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling D+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x18++0x03 line.long 0x00 "TIMER2,USBDCD TIMER2 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling d+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.long 0x18++0x03 line.long 0x00 "TIMER2,USBDCD TIMER2 Register" hexmask.long.word 0x00 16.--25. 1. " TVDPSRC_CON ,Time period before enabling d+ pull-up (in ms)" bitfld.long 0x00 0.--3. " CHECK_DM ,Time before check of D- line (in ms)" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif width 0x0B tree.end tree "USBHS (USB High Speed OTG Controller)" base ad:0x40034000 width 18. rgroup.long 0x00++0x17 line.long 0x00 "ID,USB ID Register" bitfld.long 0x00 29.--31. " VERSIONID ,Version ID" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " VERSION ,Version of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 21.--24. " REVISION ,Revision number of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--20. " TAG ,Tag of the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--13. " NID ,Ones complement version of ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*") line.long 0x04 "HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,Indicates presence of serial interface" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,Indicates USB transceiver interface used" ",,ULPI only,?..." bitfld.long 0x04 4.--5. " PHYW ,Indicates width of data interface to USB phy" "Non-UTMI,?..." elif cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") line.long 0x04 "HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,Indicates presence of serial interface" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,Indicates USB transceiver interface used" "UTMI/UTMI+,?..." bitfld.long 0x04 4.--5. " PHYW ,Indicates width of data interface to USB phy" ",16 bit,?..." else line.long 0x04 "HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,Indicates presence of serial interface" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,Indicates USB transceiver interface used" ",,ULPI only,?..." endif line.long 0x08 "HWHOST,Host Hardware Parameters Register" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Transaction translator periodic contexts" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Transaction translator contexts" bitfld.long 0x08 1.--3. " NPORT ,Number of ports" "1,2,3,4,5,6,7,8" newline bitfld.long 0x08 0. " HC ,Host capable" "Not capable,Capable" line.long 0x0C "HWDEVICE,Device Hardware Parameters Register" bitfld.long 0x0C 1.--5. " DEVEP ,Device endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0C 0. " DC ,Device capable" "Not capable,Capable" line.long 0x10 "HWTXBUF,Transmit Buffer Hardware Parameters Register" bitfld.long 0x10 31. " TXLC ,Transmit local context registers" "TX FIFO,Register file" hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,Number of address bits for channel's Tx buffer" hexmask.long.byte 0x10 8.--15. 1. " TXADD ,Number of address bits for Tx buffer" newline hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Number of data beats in a burst for transmit DMA data transfers" line.long 0x14 "HWRXBUF,Hardware Receive Buffer Register" hexmask.long.byte 0x14 8.--15. 1. " RXADD ,Number of address bits for Rx buffer" hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Number of data beats in a burst for receive DMA data transfers" group.long 0x80++0x13 line.long 0x00 "GPTIMER0LD,General Purpose Timer 0 Load Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x04 "GPTIMER0CTRL,General Purpose Timer 0 Control Register" bitfld.long 0x04 31. " RUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x04 30. " RST ,General purpose timer reset" "No action,Reload" bitfld.long 0x04 24. " MODE ,General purpose timer mode" "One shot,Repeat" newline hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x08 "GPTIMER1LD,General Purpose Timer 1 Load Register" hexmask.long.tbyte 0x08 0.--23. 1. " GPTLD ,General purpose timer load value" line.long 0x0C "GPTIMER1CTRL,General Purpose Timer 1 Control Register" bitfld.long 0x0C 31. " RUN ,General purpose timer run" "Stopped,Running" bitfld.long 0x0C 30. " RST ,General purpose timer reset" "No action,Reload" bitfld.long 0x0C 24. " MODE ,General purpose timer mode" "One shot,Repeat" newline hexmask.long.tbyte 0x0C 0.--23. 1. " GPTCNT ,General purpose timer counter" line.long 0x10 "USB_SBUSCFG,System Bus Interface Configuration Register" bitfld.long 0x10 0.--2. " BURSTMODE ,Burst mode (unspecified decomposition)" "INCR/unspec.,INCR4,INCR8,INCR16,,INCR4/unspec.,INCR8/unspec.,INCR16/unspec." rgroup.long 0x100++0x0B line.long 0x00 "HCIVERSION,Host Controller Interface Version and Capability Registers Length Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,EHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Capability registers length" line.long 0x04 "HCSPARAMS,Host Controller Structural Parameters Register" bitfld.long 0x04 24.--27. " N_TT ,Number of transaction translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " N_PTT ,Number of ports per transaction translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16. " PI ,Port indicators" "Not supported,Supported" newline bitfld.long 0x04 12.--15. " N_CC ,Number of companion controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 8.--11. " N_PCC ,Number of ports per companion controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. " PPC ,Port power control" "Not supported,Supported" newline bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HCCPARAMS,Host Control Capability Parameters Register" hexmask.long.byte 0x08 8.--15. 0x01 " EECP ,EHCI extended capabilities pointer" bitfld.long 0x08 4.--7. " IST ,Isochronous scheduling threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 2. " ASP ,Asynchronous schedule park capability" "Not supported,Supported" newline sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") bitfld.long 0x08 1. " PFL ,Programmable frame list flag" ",Conf. by USBCMD" newline else bitfld.long 0x08 1. " PFL ,Programmable frame list flag" ",Smaller list" newline endif bitfld.long 0x08 0. " ADC ,64bit addressing capability" "Not supported,Supported" sif cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15") rgroup.long 0x120++0x03 line.long 0x00 "DCIVERSION,Device Controller Interface Version" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Device interface revision number" else rgroup.word 0x122++0x01 line.word 0x00 "DCIVERSION,Device Controller Interface Version" endif rgroup.long 0x124++0x03 line.long 0x00 "DCCPARAMS,Device Controller Capability Parameters" bitfld.long 0x00 8. " HC ,Host capable" "Not capable,Capable" bitfld.long 0x00 7. " DC ,Device capable" "Not capable,Capable" sif cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else bitfld.long 0x00 0.--4. " DEN ,Device endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." endif newline sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R") if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" newline bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x00 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" eventfld.long 0x00 8. " SLI ,Device controller suspend" "Not suspended,Suspended" newline eventfld.long 0x00 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x00 6. " URI ,USB reset received" "Not receive,Received" eventfld.long 0x00 4. " SEI ,System error" "No error,Error" eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected" newline eventfld.long 0x00 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) if (((per.l(ad:0x40034000+0x140))&0x20)==0x20) group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" else group.long 0x140++0x03 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,?..." bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" endif group.long 0x144++0x03 line.long 0x00 "USBSTS,USB Status Register" eventfld.long 0x00 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x00 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x00 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x00 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x00 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" rbitfld.long 0x00 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x00 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline rbitfld.long 0x00 12. " HCH ,Host controller halted" "Not halted,Halted" rbitfld.long 0x00 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x00 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" newline eventfld.long 0x00 4. " SEI ,System error" "No error,Error" eventfld.long 0x00 3. " FRI ,Frame list rollover" "Not detected,Detected" eventfld.long 0x00 2. " PCI ,Port change detect" "Not detected,Detected" eventfld.long 0x00 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" newline eventfld.long 0x00 0. " UI ,USB interrupt" "No interrupt,Interrupt" else rgroup.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" bitfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" bitfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" bitfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" bitfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline bitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" bitfld.long 0x04 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" bitfld.long 0x04 14. " PS ,Periodic schedule status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline bitfld.long 0x04 12. " HCH ,Host controller halted" "Not halted,Halted" bitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " SLI ,Device controller suspend" "Not suspended,Suspended" bitfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" newline bitfld.long 0x04 6. " URI ,USB reset received" "Not receive,Received" bitfld.long 0x04 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" bitfld.long 0x04 3. " FRI ,Frame list rollover" "Not detected,Detected" newline bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" bitfld.long 0x04 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" endif elif cpuis("MK70*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Device controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer 1 interrupt" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer 0 interrupt" "No interrupt,Interrupt" rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline endif eventfld.long 0x04 8. " SLI ,Device controller suspend" "Not suspended,Suspended" eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB reset received" "Not received,Received" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" newline bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x04 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" rbitfld.long 0x04 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x04 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline rbitfld.long 0x04 12. " HCH ,Host controller halted" "Not halted,Halted" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline endif eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB reset received" "Not received,Received" newline bitfld.long 0x04 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" bitfld.long 0x04 3. " FRI ,Frame list rollover" "Not detected,Detected" bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" newline bitfld.long 0x04 1. " UEI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" else group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline endif eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" newline bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" endif else if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" newline eventfld.long 0x04 8. " SLI ,Device controller suspend" "Not suspended,Suspended" eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB reset received" "Not received,Received" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" newline bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" newline bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" newline bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x04 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" rbitfld.long 0x04 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x04 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline rbitfld.long 0x04 12. " HCH ,Host controller halted" "Not halted,Halted" rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" eventfld.long 0x04 6. " URI ,USB reset received" "Not received,Received" newline bitfld.long 0x04 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" bitfld.long 0x04 3. " FRI ,Frame list rollover" "Not detected,Detected" bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" newline bitfld.long 0x04 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x00) group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x04 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" rbitfld.long 0x04 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x04 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline rbitfld.long 0x04 12. " HCH ,Host controller halted" "Not halted,Halted" rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" eventfld.long 0x04 8. " SLI ,Device controller suspend" "Not suspended,Suspended" eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" newline eventfld.long 0x04 6. " URI ,USB reset received" "Not received,Received" bitfld.long 0x04 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" bitfld.long 0x04 4. " SEI ,System error" "No error,Error" bitfld.long 0x04 3. " FRI ,Frame list rollover" "Not detected,Detected" newline bitfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" bitfld.long 0x04 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" else group.long 0x140++0x07 line.long 0x00 "USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt threshold control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not added,Added" bitfld.long 0x00 13. " SUTW ,Setup TripWire without being corrupted" "Corrupted,Not corrupted" bitfld.long 0x00 11. " ASPE ,Asynchronous schedule park mode enable" "Disabled,Enabled" newline bitfld.long 0x00 8.--9. " ASP ,Asynchronous schedule park mode count" ",1,2,3" bitfld.long 0x00 6. " IAA ,Interrupt on async advance doorbell" "Disabled,Enabled" bitfld.long 0x00 5. " ASE ,Asynchronous schedule enable" "Disabled,Enabled" bitfld.long 0x00 4. " PSE ,Periodic schedule enable" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. 15. " FS ,Frame list size [elements]" "1024,512,256,128,64,32,16,8" bitfld.long 0x00 1. " RST ,Controller reset" "No reset,Reset" bitfld.long 0x00 0. " RS ,Host controller run/stop" "Stopped,Running" line.long 0x04 "USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General purpose timer interrupt 1" "No interrupt,Interrupt" eventfld.long 0x04 24. " TI0 ,General purpose timer interrupt 0" "No interrupt,Interrupt" eventfld.long 0x04 19. " UPI ,USB host periodic interrupt" "No interrupt,Interrupt" eventfld.long 0x04 18. " UAI ,USB host asynchronous interrupt" "No interrupt,Interrupt" newline rbitfld.long 0x04 16. " NAKI ,NAK interrupt bit" "No interrupt,Interrupt" rbitfld.long 0x04 15. " AS ,Asynchronous schedule status" "Disabled,Enabled" rbitfld.long 0x04 14. " PS ,Periodic schedule status" "Disabled,Enabled" rbitfld.long 0x04 13. " RCL ,Reclamation (asynchronous schedule empty)" "Not empty,Empty" newline rbitfld.long 0x04 12. " HCH ,Host controller halted" "Not halted,Halted" rbitfld.long 0x04 10. " ULPII ,ULPI interrupt" "No interrupt,Interrupt" eventfld.long 0x04 8. " SLI ,Device controller suspend" "Not suspended,Suspended" eventfld.long 0x04 7. " SRI ,Start of (micro) frame received" "Not received,Received" newline eventfld.long 0x04 6. " URI ,USB reset received" "Not receive,Received" eventfld.long 0x04 5. " AAI ,Interrupt on async advance" "No interrupt,Interrupt" eventfld.long 0x04 4. " SEI ,System error" "No error,Error" eventfld.long 0x04 3. " FRI ,Frame list rollover" "Not detected,Detected" newline eventfld.long 0x04 2. " PCI ,Port change detect" "Not detected,Detected" eventfld.long 0x04 1. " USI ,UEI USB error interrupt" "No interrupt,Interrupt" eventfld.long 0x04 0. " UI ,USB interrupt" "No interrupt,Interrupt" endif endif sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R") if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x148++0x03 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" newline bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" bitfld.long 0x00 6. " URE ,USB reset received enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x148++0x03 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" if (((per.l(ad:0x40034000+0x144))&0x1000)==0x1000) group.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" else rgroup.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" endif else rgroup.long 0x148++0x03 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" bitfld.long 0x00 6. " URE ,USB reset received enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" rgroup.long 0x14C++0x3 line.long 0x00 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 0.--13. 1. " FRINDEX ,Frame index" endif elif cpuis("MK70*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " URE ,USB reset received enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame index" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame index" else group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" newline sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") bitfld.long 0x00 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame index" endif else group.long 0x148++0x07 line.long 0x00 "USBINTR,USB Interrupt Enable Register" bitfld.long 0x00 25. " TIE1 ,General purpose timer interrupt 1 enable" "Disabled,Enabled" bitfld.long 0x00 24. " TIE0 ,General purpose timer interrupt 0 enable" "Disabled,Enabled" bitfld.long 0x00 19. " UPIE ,USB host periodic interrupt enable" "Disabled,Enabled" bitfld.long 0x00 18. " UAIE ,USB host asynchronous interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " NAKE ,NAK interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " ULPIE ,ULPI interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLE ,Sleep enable" "Disabled,Enabled" bitfld.long 0x00 7. " SRE ,Start of (micro) frame received enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " URE ,USB reset received enable" "Disabled,Enabled" bitfld.long 0x00 5. " AAE ,Interrupt on async advance enable" "Disabled,Enabled" bitfld.long 0x00 4. " SEE ,System error enable" "Disabled,Enabled" bitfld.long 0x00 3. " FRE ,Frame list rollover enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " PCE ,Port change detect enable" "Disabled,Enabled" bitfld.long 0x00 1. " UEE ,USB error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " UE ,USB interrupt enable" "Disabled,Enabled" line.long 0x04 "FRINDEX,USB Frame Index Register" hexmask.long.word 0x04 0.--13. 1. " FRINDEX ,Frame index" endif newline sif cpuis("MK26FN*") if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x154++0x03 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x02 " USBADR ,Device address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "0,1" group.long 0x158++0x03 line.long 0x00 "EPLISTADDR,Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE ,Endpoint list address" hgroup.long 0x15C++0x03 hide.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control Register" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x154++0x03 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE ,Base address" group.long 0x158++0x03 line.long 0x00 "ASYNCLISTADDR,Current Asynchronous List Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE ,Link pointer low [31:5]" rgroup.long 0x15C++0x03 line.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control Register" hexmask.long.byte 0x00 24.--30. 0x01 " TTHA ,TT hub address" else rgroup.long 0x154++0x03 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" rgroup.long 0x158++0x03 line.long 0x00 "ASYNCLISTADDR,Current Asynchronous List Address Register" rgroup.long 0x15C++0x03 line.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control Register" endif else if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x154++0x03 line.long 0x00 "DEVICEADDR,Device Address Register" hexmask.long.byte 0x00 25.--31. 0x2 " USBADR ,Device address" bitfld.long 0x00 24. " USBADRA ,Device address advance" "0,1" group.long 0x158++0x03 line.long 0x00 "EPLISTADDR,Endpoint List Address Register" hexmask.long.tbyte 0x00 11.--31. 0x8 " EPBASE ,Endpoint list address" hgroup.long 0x15C++0x03 hide.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x154++0x03 line.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE ,Base address" group.long 0x158++0x03 line.long 0x00 "ASYNCLISTADDR,Current Asynchronous List Address Register" hexmask.long 0x00 5.--31. 0x20 " ASYBASE ,Link pointer low [31:5]" rgroup.long 0x15C++0x03 line.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control" hexmask.long.byte 0x00 24.--30. 0x01 " TTHA ,TT hub address" else hgroup.long 0x154++0x03 hide.long 0x00 "PERIODICLISTBASE,Periodic Frame List Base Address Register" in hgroup.long 0x158++0x03 hide.long 0x00 "ASYNCLISTADDR,Current Asynchronous List Address Register" in rgroup.long 0x15C++0x03 line.long 0x00 "TTCTRL,Host TT Asynchronous Buffer Control" hexmask.long.byte 0x00 24.--30. 0x01 " TTHA ,TT hub address" endif endif group.long 0x160++0x07 line.long 0x00 "BURSTSIZE,Master Interface Data Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable Tx burst length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable Rx burst length" line.long 0x04 "TXFILLTUNING,Transmit FIFO Tuning Control Register" bitfld.long 0x04 16.--21. " TXFIFOTHRES ,FIFO burst threshold" ",,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x04 8.--12. " TXSCHHEALTH ,Scheduler health counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x04 0.--6. 1. " TXSCHOH ,Scheduler overhead" sif !cpuis("MK26FN*")&&!cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") group.long 0x170++0x03 line.long 0x00 "ULPI_VIEWPORT,ULPI Register Access" bitfld.long 0x00 31. " ULPI_WU ,ULPI wakeup" "No wake up,Wake up" bitfld.long 0x00 30. " ULPI_RUN ,ULPI read/write run" "Not running,Running" bitfld.long 0x00 29. " ULPI_RW ,ULPI read/write control" "Read,Write" newline bitfld.long 0x00 27. " ULPI_SS ,ULPI sync state" "Other state,Normal Sync" newline sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK70*") bitfld.long 0x00 24.--26. " ULPI_PORT ,ULPI port number" "0,1,?..." newline else bitfld.long 0x00 24.--26. " ULPI_PORT ,ULPI port number" "0,1,2,3,4,5,6,7" newline endif hexmask.long.byte 0x00 16.--23. 0x01 " ULPI_ADDR ,ULPI data address" newline hexmask.long.byte 0x00 8.--15. 1. " ULPI_DATRD ,ULPI data read" hexmask.long.byte 0x00 0.--7. 1. " ULPI_DATWR ,ULPI data write" endif group.long 0x178++0x07 line.long 0x00 "ENDPTNAK,Endpoint NAK Register" eventfld.long 0x00 19. " EPTN[3] ,TX endpoint 3 NAK" "Not detected,Detected" eventfld.long 0x00 18. " EPTN[2] ,TX endpoint 2 NAK" "Not detected,Detected" eventfld.long 0x00 17. " EPTN[1] ,TX endpoint 1 NAK" "Not detected,Detected" newline eventfld.long 0x00 16. " EPTN[0] ,TX endpoint 0 NAK" "Not detected,Detected" eventfld.long 0x00 3. " EPRN[3] ,RX endpoint 3 NAK" "Not detected,Detected" eventfld.long 0x00 2. " EPRN[2] ,RX endpoint 2 NAK" "Not detected,Detected" newline eventfld.long 0x00 1. " EPRN[1] ,RX endpoint 1 NAK" "Not detected,Detected" eventfld.long 0x00 0. " EPRN[0] ,RX endpoint 0 NAK" "Not detected,Detected" line.long 0x04 "ENDPTNAKEN,Endpoint NAK Enable Register" sif cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("MK60FN1M0VLQ15")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") eventfld.long 0x04 19. " EPTNE[3] ,TX endpoint 3 NAK enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNE[2] ,TX endpoint 2 NAK enable" "Disabled,Enabled" eventfld.long 0x04 17. " EPTNE[1] ,TX endpoint 1 NAK enable" "Disabled,Enabled" newline eventfld.long 0x04 16. " EPTNE[0] ,TX endpoint 0 NAK enable" "Disabled,Enabled" eventfld.long 0x04 3. " EPRNE[3] ,RX endpoint 3 NAK enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNE[2] ,RX endpoint 2 NAK enable" "Disabled,Enabled" newline eventfld.long 0x04 1. " EPRNE[1] ,RX endpoint 1 NAK enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNE[0] ,RX endpoint 0 NAK enable" "Disabled,Enabled" else eventfld.long 0x04 19. " EPTNS[3] ,TX endpoint 3 NAK enable" "Disabled,Enabled" eventfld.long 0x04 18. " EPTNS[2] ,TX endpoint 2 NAK enable" "Disabled,Enabled" eventfld.long 0x04 17. " EPTNS[1] ,TX endpoint 1 NAK enable" "Disabled,Enabled" newline eventfld.long 0x04 16. " EPTNS[0] ,TX endpoint 0 NAK enable" "Disabled,Enabled" eventfld.long 0x04 3. " EPRNS[3] ,RX endpoint 3 NAK enable" "Disabled,Enabled" eventfld.long 0x04 2. " EPRNS[2] ,RX endpoint 2 NAK enable" "Disabled,Enabled" newline eventfld.long 0x04 1. " EPRNS[1] ,RX endpoint 1 NAK enable" "Disabled,Enabled" eventfld.long 0x04 0. " EPRNS[0] ,RX endpoint 0 NAK enable" "Disabled,Enabled" endif sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R")||cpuis("MK70*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") sif !cpuis("?K28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R") rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configure Flag Register" endif if (((per.l(ad:0x40034000+0x1A8))&0x03)==0x03) group.long 0x184++0x03 line.long 0x00 "PORTSC,USB Port Status Control Register" sif cpuis("MK70*") bitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" ",,ULPI,?..." newline elif cpuis("MK20FN1M0VLQ12R") rbitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" ",,ULPI,?..." newline else rbitfld.long 0x00 30.--31. 25. " PTS ,Parallel transceiver select" "UTMI,?..." newline endif rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full,Low,High,?..." bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Allow HS,Force FS" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " WKDS ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 12. " PP ,Port power" "Not powered,Powered" newline rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High speed port" "FS or LS,HS" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" newline bitfld.long 0x00 6. " FPR ,Force port resume" "Not resumed,Resumed" eventfld.long 0x00 5. " OCC ,Over-current change" "Not detected,Detected" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Disabled" newline bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "No dev. present,Dev. present" elif (((per.l(ad:0x40034000+0x1A8))&0x03)==0x02) group.long 0x184++0x03 line.long 0x00 "PORTSC,USB Port Status Control Register" sif cpuis("MK70*") bitfld.long 0x00 25. 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,?..." newline else rbitfld.long 0x00 25. 30.--31. " PTS ,Parallel transceiver select" "UTMI,?..." newline endif rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full Speed,Low Speed,High Speed,?..." bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Allow HS,Force FS" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "Not suspended,Suspended" rbitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" newline rbitfld.long 0x00 21. " WKDS ,Wake on disconnect enable" "Disabled,Enabled" rbitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 12. " PP ,Port power" "Not powered,Powered" newline rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,J-state,K-state,?..." rbitfld.long 0x00 9. " HSP ,High speed port" "FS or LS,HS" rbitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" rbitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" newline bitfld.long 0x00 6. " FPR ,Force port resume" "Not resumed,Resumed" rbitfld.long 0x00 5. " OCC ,Over-current change" "Not detected,Detected" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" rbitfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Disabled" newline rbitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not attached,Attached" else rgroup.long 0x184++0x03 line.long 0x00 "PORTSC,USB Port Status Control Register" sif cpuis("MK70*") bitfld.long 0x00 25. 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,?..." newline elif cpuis("KK26FN2M0CAC18?")||cpuis("MK27FN2M0VMI15")||cpuis("MK28FN2M0VMI15")||cpuis("?K28FN2M0CAU15?") rbitfld.long 0x00 25. 30.--31. " PTS ,Parallel transceiver select" "UTMI,?..." newline else bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,?..." newline endif bitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full Speed,Low Speed,High Speed,?..." bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "No,Yes" bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " WKDS ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." bitfld.long 0x00 12. " PP ,Port power" "No control,?..." newline bitfld.long 0x00 10.--11. " LS ,Line status" "SE0,Jstate,Kstate,?..." bitfld.long 0x00 9. " HSP ,High speed port" "FS or LS,HS" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" newline bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" bitfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" bitfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" newline bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" bitfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" bitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected" endif else sif cpuis("MK60FN1M0VLQ15") rgroup.long 0x180++0x03 line.long 0x00 "CONFIGFLAG,Configure Flag Register" endif group.long 0x184++0x03 line.long 0x00 "PORTSC,USB Port Status Control Register" bitfld.long 0x00 30.--31. " PTS ,Parallel transceiver select" ",,ULPI,?..." rbitfld.long 0x00 26.--27. " PSPD ,Port speed" "Full Speed,Low Speed,High Speed,?..." bitfld.long 0x00 24. " PFSC ,Port force full speed connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY low power suspend" "No,Yes" newline bitfld.long 0x00 22. " WKOC ,Wake on over-current enable" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on disconnect enable" "Disabled,Enabled" bitfld.long 0x00 20. " WKCN ,Wake on connect enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port test control" "Disabled,J_STATE,K_STATE,SEQ_NAK,Packet,FORCE_ENABLE_HS,FORCE_ENABLE_FS,FORCE_ENABLE_LS,?..." newline bitfld.long 0x00 12. " PP ,Port power" "No control,?..." rbitfld.long 0x00 10.--11. " LS ,Line status" "SE0,Jstate,Kstate,?..." rbitfld.long 0x00 9. " HSP ,High speed port" "FS or LS,HS" bitfld.long 0x00 8. " PR ,Port reset" "No reset,Reset" newline bitfld.long 0x00 7. " SUSP ,Suspend" "Not suspended,Suspended" bitfld.long 0x00 6. " FPR ,Force port resume" "Not forced,Forced" eventfld.long 0x00 5. " OCC ,Over-current change" "Not changed,Changed" rbitfld.long 0x00 4. " OCA ,Over-current active" "No over-current,Over-current" newline eventfld.long 0x00 3. " PEC ,Port enable/disable change" "Not changed,Changed" bitfld.long 0x00 2. " PE ,Port enabled/disabled" "Disabled,Enabled" eventfld.long 0x00 1. " CSC ,Connect status change" "Not changed,Changed" rbitfld.long 0x00 0. " CCS ,Current connect status" "Not connected,Connected" endif group.long 0x1A4++0x07 line.long 0x00 "OTGSC,On-the-Go Status and Control Register" bitfld.long 0x00 30. " DPIE ,Data pulse interrupt enable" "Disabled,Enabled" bitfld.long 0x00 29. " MSE ,1 milli-second timer interrupt enable" "Disabled,Enabled" bitfld.long 0x00 28. " BSEIE ,B session end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B session valid interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " ASVIE ,A session valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBUS valid interrupt enable" "Disabled,Enabled" bitfld.long 0x00 24. " IDIE ,USB ID interrupt enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data pulse interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 21. " MSS ,1 milli-second timer interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 20. " BSEIS ,B session end interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 19. " BSVIS ,B session valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 18. " ASVIS ,A session valid interrupt status" "No interrupt,Interrupt" newline eventfld.long 0x00 17. " AVVIS ,A VBUS valid interrupt status" "No interrupt,Interrupt" eventfld.long 0x00 16. " IDIS ,USB ID interrupt status" "No interrupt,Interrupt" rbitfld.long 0x00 14. " DPS ,Data bus pulsing status" "Not detected,Detected" rbitfld.long 0x00 13. " MST ,1 milli-second timer toggle" "Low,High" newline rbitfld.long 0x00 12. " BSE ,VBus status relative to B session end" "Above,Below" rbitfld.long 0x00 11. " BSV ,VBus status relative to B session valid" "Below,Above" rbitfld.long 0x00 10. " ASV ,VBus status relative to A session valid" "Below,Above" rbitfld.long 0x00 9. " AVV ,VBus status relative to A VBus valid" "Below,Above" newline rbitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware assist B-Disconnect to a-connect" "Disabled,Enabled" bitfld.long 0x00 5. " IDPU ,ID pull-up enable" "Disabled,Enabled" bitfld.long 0x00 4. " DP ,Data pulsing" "Not asserted,Asserted" newline bitfld.long 0x00 3. " OT ,OTG termination" "Disabled,Enabled" bitfld.long 0x00 2. " HAAR ,Hardware assist auto-reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS charge" "Not charged,Charged" bitfld.long 0x00 0. " VD ,VBUS discharge" "Not discharged,Discharged" line.long 0x04 "USBMODE,USB Mode Register" bitfld.long 0x04 12.--14. " TXHSD ,Tx to Tx HS delay" "10,11,12,13,14,15,16,17" bitfld.long 0x04 4. " SDIS ,Stream disable mode" "Inactive,Active" bitfld.long 0x04 3. " SLOM ,Setup lockout mode" "Disabled,Enabled" bitfld.long 0x04 2. " ES ,Endian select" "Little endian,Big endian" newline bitfld.long 0x04 0.--1. " CM ,Controller mode" "Idle,,Device Controller,Host Controller" if ((((per.l(ad:0x40034000+0x1A8))&0x03)==0x02)||(((per.l(ad:0x40034000+0x1A8))&0x03)==0x00)) group.long 0x1AC++0x0B line.long 0x00 "EPSETUPSR,Endpoint Setup Status Register" eventfld.long 0x00 3. " EPSETUPSTAT[3] ,Setup endpoint 3 status" "Not received,Received" eventfld.long 0x00 2. " [2] ,Setup endpoint 2 status" "Not received,Received" eventfld.long 0x00 1. " [1] ,Setup endpoint 1 status" "Not received,Received" eventfld.long 0x00 0. " [0] ,Setup endpoint 0 status" "Not received,Received" line.long 0x04 "EPPRIME,Endpoint Initialization Register" bitfld.long 0x04 19. " PETB[3] ,Prime endpoint 3 transmit buffer prepare request" "Not requested,Requested" bitfld.long 0x04 18. " [2] ,Prime endpoint 2 transmit buffer prepare request" "Not requested,Requested" bitfld.long 0x04 17. " [1] ,Prime endpoint 1 transmit buffer prepare request" "Not requested,Requested" bitfld.long 0x04 16. " [0] ,Prime endpoint 0 transmit buffer prepare request" "Not requested,Requested" newline bitfld.long 0x04 3. " PERB[3] ,Prime endpoint 3 receive buffer prepare request" "Not requested,Requested" bitfld.long 0x04 2. " [2] ,Prime endpoint 2 receive buffer prepare request" "Not requested,Requested" bitfld.long 0x04 1. " [1] ,Prime endpoint 1 receive buffer prepare request" "Not requested,Requested" bitfld.long 0x04 0. " [0] ,Prime endpoint 0 receive buffer prepare request" "Not requested,Requested" line.long 0x08 "EPFLUSH,Endpoint Flush Register" bitfld.long 0x08 19. " FETB[3] ,Prime endpoint 3 transmit buffer flush" "Not flushed,Flushed" bitfld.long 0x08 18. " [2] ,Prime endpoint 2 transmit buffer flush" "Not flushed,Flushed" bitfld.long 0x08 17. " [1] ,Prime endpoint 1 transmit buffer flush" "Not flushed,Flushed" bitfld.long 0x08 16. " [0] ,Prime endpoint 0 transmit buffer flush" "Not flushed,Flushed" newline bitfld.long 0x08 3. " FERB[3] ,Prime endpoint 3 receive buffer flush" "Not flushed,Flushed" bitfld.long 0x08 2. " [2] ,Prime endpoint 2 receive buffer flush" "Not flushed,Flushed" bitfld.long 0x08 1. " [1] ,Prime endpoint 1 receive buffer flush" "Not flushed,Flushed" bitfld.long 0x08 0. " [0] ,Prime endpoint 0 receive buffer flush" "Not flushed,Flushed" rgroup.long 0x1B8++0x03 line.long 0x00 "EPSR,Endpoint Status Register" bitfld.long 0x00 19. " ETBR[3] ,Endpoint 3 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 18. " [2] ,Endpoint 2 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 17. " [1] ,Endpoint 1 transmit buffer ready" "Not ready,Ready" bitfld.long 0x00 16. " [0] ,Endpoint 0 transmit buffer ready" "Not ready,Ready" newline bitfld.long 0x00 3. " ERBR[3] ,Endpoint 3 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 2. " [2] ,Endpoint 2 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 1. " [1] ,Endpoint 1 receive buffer ready" "Not ready,Ready" bitfld.long 0x00 0. " [0] ,Endpoint 0 receive buffer ready" "Not ready,Ready" group.long 0x1BC++0x03 line.long 0x00 "EPCOMPLETE,Endpoint Complete Register" eventfld.long 0x00 19. " ETCE[3] ,Endpoint 3 transmit complete event" "Not completed,Completed" eventfld.long 0x00 18. " [2] ,Endpoint 2 transmit complete event" "Not completed,Completed" eventfld.long 0x00 17. " [1] ,Endpoint 1 transmit complete event" "Not completed,Completed" eventfld.long 0x00 16. " [0] ,Endpoint 0 transmit complete event" "Not completed,Completed" newline eventfld.long 0x00 3. " ERCE[3] ,Endpoint 3 receive complete event" "Not completed,Completed" eventfld.long 0x00 2. " [2] ,Endpoint 2 receive complete event" "Not completed,Completed" eventfld.long 0x00 1. " [1] ,Endpoint 1 receive complete event" "Not completed,Completed" eventfld.long 0x00 0. " [0] ,Endpoint 0 receive complete event" "Not completed,Completed" else hgroup.long 0x1AC++0x13 hide.long 0x00 "EPSETUPSR,Endpoint Setup Status Register" hide.long 0x04 "EPPRIME,Endpoint Initialization Register" hide.long 0x08 "EPFLUSH,Endpoint Flush Register" hide.long 0x0C "EPSR,Endpoint Status Register" hide.long 0x10 "EPCOMPLETE,Endpoint Complete Register" endif newline width 13. sif cpuis("MK26FN*")||cpuis("MK20FN1M0VLQ12R")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") group.long 0x1C0++0x03 "Endpoints 0-7" line.long 0x00 "EPCR0,Endpoint Control Register 0" sif cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") rbitfld.long 0x00 23. " TXE ,TX endpoint enable" ",Enabled" else rbitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" endif rbitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline sif cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") rbitfld.long 0x00 7. " RXE ,RX endpoint enable" ",Enabled" else rbitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" endif rbitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C4++0x03 line.long 0x00 "ENDPTCTRL1,Endpoint Control Register 1" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C8++0x03 line.long 0x00 "ENDPTCTRL2,Endpoint Control Register 2" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1CC++0x03 line.long 0x00 "ENDPTCTRL3,Endpoint Control Register 3" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D0++0x03 line.long 0x00 "ENDPTCTRL4,Endpoint Control Register 4" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D4++0x03 line.long 0x00 "ENDPTCTRL5,Endpoint Control Register 5" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1D8++0x03 line.long 0x00 "ENDPTCTRL6,Endpoint Control Register 6" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1DC++0x03 line.long 0x00 "ENDPTCTRL7,Endpoint Control Register 7" bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" else group.long 0x1C0++0x03 "Endpoints 0-3" line.long 0x00 "EPCR0,Endpoint Control Register 0" rbitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" rbitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline rbitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" rbitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C4++0x03 sif cpuis("MK70*") line.long 0x00 "EPCR1,Endpoint Control Register 1" else line.long 0x00 "ENDPTCTRL1,Endpoint Control Register 1" endif bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1C8++0x03 sif cpuis("MK70*") line.long 0x00 "EPCR2,Endpoint Control Register 2" else line.long 0x00 "ENDPTCTRL2,Endpoint Control Register 2" endif bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" group.long 0x1CC++0x03 sif cpuis("MK70*") line.long 0x00 "EPCR3,Endpoint Control Register 3" else line.long 0x00 "ENDPTCTRL3,Endpoint Control Register 3" endif bitfld.long 0x00 23. " TXE ,TX endpoint enable" "Disabled,Enabled" bitfld.long 0x00 22. " TXR ,TX data toggle reset" "No reset,Reset" bitfld.long 0x00 21. " TXI ,TX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 18.--19. " TXT ,TX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 17. " TXD ,TX endpoint data source" "Mem. buff./DMA,?..." bitfld.long 0x00 16. " TXS ,TX endpoint stall" "OK,Stalled" newline bitfld.long 0x00 7. " RXE ,RX endpoint enable" "Disabled,Enabled" eventfld.long 0x00 6. " RXR ,RX data toggle reset" "No reset,Reset" bitfld.long 0x00 5. " RXI ,RX data toggle inhibit" "Disabled,Enabled" newline bitfld.long 0x00 2.--3. " RXT ,RX endpoint type" "Control,Isochronous,Bulk,Interrupt" bitfld.long 0x00 1. " RXD ,RX endpoint data sink" "Mem. buff./DMA,?..." bitfld.long 0x00 0. " RXS ,RX endpoint stall" "OK,Stalled" endif sif cpuis("MK26FN*")||cpuis("?K28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("MK27FN2M0VMI15")||cpuis("KK26FN2M0CAC18R") group.long 0x200++0x03 line.long 0x00 "USBGENCTRL,USB General Control Register" bitfld.long 0x00 5. " WU_INT_CLR ,Wakeup interrupt clear" "No effect,Clear" bitfld.long 0x00 0. " WU_IE ,Wake interrupt enable" "Disabled,Enabled" else group.long 0x200++0x03 line.long 0x00 "USBGENCTRL,USB General Control Register" bitfld.long 0x00 5. " WU_INT_CLR ,Wakeup interrupt clear" "No effect,Clear" bitfld.long 0x00 1. " WU_ULPI_EN ,Wakeup on ULPI interrupt event" "Disabled,Enabled" bitfld.long 0x00 0. " WU_IE ,Wake interrupt enable" "Disabled,Enabled" endif width 0x0B tree.end tree.open "CAN (FlexCAN)" tree "CAN0" base ad:0x40024000 width 15. group.long 0x00++0xb line.long 0x00 "CAN0_MCR,CAN0 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN Not Ready" "Ready,Not ready" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 25. " SOFT_RST ,Soft Reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze Mode Acknowledge" "Not Freeze,Freeze" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,Self Wake Up Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,Warning Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low Power Mode Acknowledge" "Not LPM,LPM" textline " " sif (cpuis("MK70*")) bitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered RX input,Filtered RX input" textline " " endif bitfld.long 0x00 17. " SRX_DIS ,Self Reception Disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx Masking and Queue Enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIO_EN ,Local Priority Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the Last Message Buffer" line.long 0x04 "CAN0_CTRL1,CAN0 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler Division Factor" bitfld.long 0x04 22.--23. " RJW ,Resync Jump Width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase Segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 16.--18. " PSEG2 ,Phase Segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Mask" "Masked,Not masked" bitfld.long 0x04 14. " ERR_MSK ,Error Mask" "Masked,Not masked" bitfld.long 0x04 13. " CLK_SRC ,CAN Engine Clock Source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop Back" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 7. " SMP ,Sampling Mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFF_REC ,Bus Off Recovery Mode Disable" "No,Yes" textline " " bitfld.long 0x04 5. " TSYN ,Timer Sync Mode " "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest Buffer Transmitted First" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-Only Mode" "Deactivated,Activated" bitfld.long 0x04 0.--2. " PROPSEG ,Propagation Segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" line.long 0x08 "CAN0_TIMER,CAN0 Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x40024000)&0x40000000)==0x0) rgroup.long 0x10++0x17 line.long 0x00 "CAN0_RXMGMASK,CAN0 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Rx Mailboxes Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Rx Mailboxes Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Rx Mailboxes Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Rx Mailboxes Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Rx Mailboxes Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Rx Mailboxes Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Rx Mailboxes Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Rx Mailboxes Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Rx Mailboxes Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Rx Mailboxes Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Rx Mailboxes Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Rx Mailboxes Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Rx Mailboxes Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Rx Mailboxes Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Rx Mailboxes Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Rx Mailboxes Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Rx Mailboxes Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Rx Mailboxes Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Rx Mailboxes Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Rx Mailboxes Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Rx Mailboxes Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Rx Mailboxes Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Rx Mailboxes Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Rx Mailboxes Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Rx Mailboxes Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Rx Mailboxes Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Rx Mailboxes Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Rx Mailboxes Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Rx Mailboxes Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Rx Mailboxes Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Rx Mailboxes Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Rx Mailboxes Global Mask Bit 0" "Masked,Not masked" line.long 0x04 "CAN0_RX14MASK,CAN0 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M31 ,Rx Buffer 14 Mask Bit 31" "Masked,Not masked" bitfld.long 0x04 30. " RX14M30 ,Rx Buffer 14 Mask Bit 30" "Masked,Not masked" bitfld.long 0x04 29. " RX14M29 ,Rx Buffer 14 Mask Bit 29" "Masked,Not masked" bitfld.long 0x04 28. " RX14M28 ,Rx Buffer 14 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " RX14M27 ,Rx Buffer 14 Mask Bit 27" "Masked,Not masked" bitfld.long 0x04 26. " RX14M26 ,Rx Buffer 14 Mask Bit 26" "Masked,Not masked" bitfld.long 0x04 25. " RX14M25 ,Rx Buffer 14 Mask Bit 25" "Masked,Not masked" bitfld.long 0x04 24. " RX14M24 ,Rx Buffer 14 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " RX14M23 ,Rx Buffer 14 Mask Bit 23" "Masked,Not masked" bitfld.long 0x04 22. " RX14M22 ,Rx Buffer 14 Mask Bit 22" "Masked,Not masked" bitfld.long 0x04 21. " RX14M21 ,Rx Buffer 14 Mask Bit 21" "Masked,Not masked" bitfld.long 0x04 20. " RX14M20 ,Rx Buffer 14 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " RX14M19 ,Rx Buffer 14 Mask Bit 19" "Masked,Not masked" bitfld.long 0x04 18. " RX14M18 ,Rx Buffer 14 Mask Bit 18" "Masked,Not masked" bitfld.long 0x04 17. " RX14M17 ,Rx Buffer 14 Mask Bit 17" "Masked,Not masked" bitfld.long 0x04 16. " RX14M16 ,Rx Buffer 14 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " RX14M15 ,Rx Buffer 14 Mask Bit 15" "Masked,Not masked" bitfld.long 0x04 14. " RX14M14 ,Rx Buffer 14 Mask Bit 14" "Masked,Not masked" bitfld.long 0x04 13. " RX14M13 ,Rx Buffer 14 Mask Bit 13" "Masked,Not masked" bitfld.long 0x04 12. " RX14M12 ,Rx Buffer 14 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " RX14M11 ,Rx Buffer 14 Mask Bit 11" "Masked,Not masked" bitfld.long 0x04 10. " RX14M10 ,Rx Buffer 14 Mask Bit 10" "Masked,Not masked" bitfld.long 0x04 9. " RX14M9 ,Rx Buffer 14 Mask Bit 9" "Masked,Not masked" bitfld.long 0x04 8. " RX14M8 ,Rx Buffer 14 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " RX14M7 ,Rx Buffer 14 Mask Bit 7" "Masked,Not masked" bitfld.long 0x04 6. " RX14M6 ,Rx Buffer 14 Mask Bit 6" "Masked,Not masked" bitfld.long 0x04 5. " RX14M5 ,Rx Buffer 14 Mask Bit 5" "Masked,Not masked" bitfld.long 0x04 4. " RX14M4 ,Rx Buffer 14 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " RX14M3 ,Rx Buffer 14 Mask Bit 3" "Masked,Not masked" bitfld.long 0x04 2. " RX14M2 ,Rx Buffer 14 Mask Bit 2" "Masked,Not masked" bitfld.long 0x04 1. " RX14M1 ,Rx Buffer 14 Mask Bit 1" "Masked,Not masked" bitfld.long 0x04 0. " RX14M0 ,Rx Buffer 14 Mask Bit 0" "Masked,Not masked" line.long 0x08 "CAN0_RX15MASK,CAN0 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M31 ,Rx Buffer 15 Mask Bit 31" "Masked,Not masked" bitfld.long 0x08 30. " RX15M30 ,Rx Buffer 15 Mask Bit 30" "Masked,Not masked" bitfld.long 0x08 29. " RX15M29 ,Rx Buffer 15 Mask Bit 29" "Masked,Not masked" bitfld.long 0x08 28. " RX15M28 ,Rx Buffer 15 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " RX15M27 ,Rx Buffer 15 Mask Bit 27" "Masked,Not masked" bitfld.long 0x08 26. " RX15M26 ,Rx Buffer 15 Mask Bit 26" "Masked,Not masked" bitfld.long 0x08 25. " RX15M25 ,Rx Buffer 15 Mask Bit 25" "Masked,Not masked" bitfld.long 0x08 24. " RX15M24 ,Rx Buffer 15 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " RX15M23 ,Rx Buffer 15 Mask Bit 23" "Masked,Not masked" bitfld.long 0x08 22. " RX15M22 ,Rx Buffer 15 Mask Bit 22" "Masked,Not masked" bitfld.long 0x08 21. " RX15M21 ,Rx Buffer 15 Mask Bit 21" "Masked,Not masked" bitfld.long 0x08 20. " RX15M20 ,Rx Buffer 15 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " RX15M19 ,Rx Buffer 15 Mask Bit 19" "Masked,Not masked" bitfld.long 0x08 18. " RX15M18 ,Rx Buffer 15 Mask Bit 18" "Masked,Not masked" bitfld.long 0x08 17. " RX15M17 ,Rx Buffer 15 Mask Bit 17" "Masked,Not masked" bitfld.long 0x08 16. " RX15M16 ,Rx Buffer 15 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " RX15M15 ,Rx Buffer 15 Mask Bit 15" "Masked,Not masked" bitfld.long 0x08 14. " RX15M14 ,Rx Buffer 15 Mask Bit 14" "Masked,Not masked" bitfld.long 0x08 13. " RX15M13 ,Rx Buffer 15 Mask Bit 13" "Masked,Not masked" bitfld.long 0x08 12. " RX15M12 ,Rx Buffer 15 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " RX15M11 ,Rx Buffer 15 Mask Bit 11" "Masked,Not masked" bitfld.long 0x08 10. " RX15M10 ,Rx Buffer 15 Mask Bit 10" "Masked,Not masked" bitfld.long 0x08 9. " RX15M9 ,Rx Buffer 15 Mask Bit 9" "Masked,Not masked" bitfld.long 0x08 8. " RX15M8 ,Rx Buffer 15 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " RX15M7 ,Rx Buffer 15 Mask Bit 7" "Masked,Not masked" bitfld.long 0x08 6. " RX15M6 ,Rx Buffer 15 Mask Bit 6" "Masked,Not masked" bitfld.long 0x08 5. " RX15M5 ,Rx Buffer 15 Mask Bit 5" "Masked,Not masked" bitfld.long 0x08 4. " RX15M4 ,Rx Buffer 15 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " RX15M3 ,Rx Buffer 15 Mask Bit 3" "Masked,Not masked" bitfld.long 0x08 2. " RX15M2 ,Rx Buffer 15 Mask Bit 2" "Masked,Not masked" bitfld.long 0x08 1. " RX15M1 ,Rx Buffer 15 Mask Bit 1" "Masked,Not masked" bitfld.long 0x08 0. " RX15M0 ,Rx Buffer 15 Mask Bit 0" "Masked,Not masked" line.long 0x0c "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_CNT ,Receive Error Counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_CNT ,Transmit Error Counter" else group.long 0x10++0x17 line.long 0x00 "CAN0_RXMGMASK,CAN0 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Rx Mailboxes Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Rx Mailboxes Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Rx Mailboxes Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Rx Mailboxes Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Rx Mailboxes Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Rx Mailboxes Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Rx Mailboxes Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Rx Mailboxes Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Rx Mailboxes Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Rx Mailboxes Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Rx Mailboxes Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Rx Mailboxes Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Rx Mailboxes Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Rx Mailboxes Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Rx Mailboxes Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Rx Mailboxes Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Rx Mailboxes Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Rx Mailboxes Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Rx Mailboxes Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Rx Mailboxes Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Rx Mailboxes Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Rx Mailboxes Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Rx Mailboxes Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Rx Mailboxes Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Rx Mailboxes Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Rx Mailboxes Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Rx Mailboxes Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Rx Mailboxes Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Rx Mailboxes Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Rx Mailboxes Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Rx Mailboxes Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Rx Mailboxes Global Mask Bit 0" "Masked,Not masked" line.long 0x04 "CAN0_RX14MASK,CAN0 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M31 ,Rx Buffer 14 Mask Bit 31" "Masked,Not masked" bitfld.long 0x04 30. " RX14M30 ,Rx Buffer 14 Mask Bit 30" "Masked,Not masked" bitfld.long 0x04 29. " RX14M29 ,Rx Buffer 14 Mask Bit 29" "Masked,Not masked" bitfld.long 0x04 28. " RX14M28 ,Rx Buffer 14 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " RX14M27 ,Rx Buffer 14 Mask Bit 27" "Masked,Not masked" bitfld.long 0x04 26. " RX14M26 ,Rx Buffer 14 Mask Bit 26" "Masked,Not masked" bitfld.long 0x04 25. " RX14M25 ,Rx Buffer 14 Mask Bit 25" "Masked,Not masked" bitfld.long 0x04 24. " RX14M24 ,Rx Buffer 14 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " RX14M23 ,Rx Buffer 14 Mask Bit 23" "Masked,Not masked" bitfld.long 0x04 22. " RX14M22 ,Rx Buffer 14 Mask Bit 22" "Masked,Not masked" bitfld.long 0x04 21. " RX14M21 ,Rx Buffer 14 Mask Bit 21" "Masked,Not masked" bitfld.long 0x04 20. " RX14M20 ,Rx Buffer 14 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " RX14M19 ,Rx Buffer 14 Mask Bit 19" "Masked,Not masked" bitfld.long 0x04 18. " RX14M18 ,Rx Buffer 14 Mask Bit 18" "Masked,Not masked" bitfld.long 0x04 17. " RX14M17 ,Rx Buffer 14 Mask Bit 17" "Masked,Not masked" bitfld.long 0x04 16. " RX14M16 ,Rx Buffer 14 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " RX14M15 ,Rx Buffer 14 Mask Bit 15" "Masked,Not masked" bitfld.long 0x04 14. " RX14M14 ,Rx Buffer 14 Mask Bit 14" "Masked,Not masked" bitfld.long 0x04 13. " RX14M13 ,Rx Buffer 14 Mask Bit 13" "Masked,Not masked" bitfld.long 0x04 12. " RX14M12 ,Rx Buffer 14 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " RX14M11 ,Rx Buffer 14 Mask Bit 11" "Masked,Not masked" bitfld.long 0x04 10. " RX14M10 ,Rx Buffer 14 Mask Bit 10" "Masked,Not masked" bitfld.long 0x04 9. " RX14M9 ,Rx Buffer 14 Mask Bit 9" "Masked,Not masked" bitfld.long 0x04 8. " RX14M8 ,Rx Buffer 14 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " RX14M7 ,Rx Buffer 14 Mask Bit 7" "Masked,Not masked" bitfld.long 0x04 6. " RX14M6 ,Rx Buffer 14 Mask Bit 6" "Masked,Not masked" bitfld.long 0x04 5. " RX14M5 ,Rx Buffer 14 Mask Bit 5" "Masked,Not masked" bitfld.long 0x04 4. " RX14M4 ,Rx Buffer 14 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " RX14M3 ,Rx Buffer 14 Mask Bit 3" "Masked,Not masked" bitfld.long 0x04 2. " RX14M2 ,Rx Buffer 14 Mask Bit 2" "Masked,Not masked" bitfld.long 0x04 1. " RX14M1 ,Rx Buffer 14 Mask Bit 1" "Masked,Not masked" bitfld.long 0x04 0. " RX14M0 ,Rx Buffer 14 Mask Bit 0" "Masked,Not masked" line.long 0x08 "CAN0_RX15MASK,CAN0 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M31 ,Rx Buffer 15 Mask Bit 31" "Masked,Not masked" bitfld.long 0x08 30. " RX15M30 ,Rx Buffer 15 Mask Bit 30" "Masked,Not masked" bitfld.long 0x08 29. " RX15M29 ,Rx Buffer 15 Mask Bit 29" "Masked,Not masked" bitfld.long 0x08 28. " RX15M28 ,Rx Buffer 15 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " RX15M27 ,Rx Buffer 15 Mask Bit 27" "Masked,Not masked" bitfld.long 0x08 26. " RX15M26 ,Rx Buffer 15 Mask Bit 26" "Masked,Not masked" bitfld.long 0x08 25. " RX15M25 ,Rx Buffer 15 Mask Bit 25" "Masked,Not masked" bitfld.long 0x08 24. " RX15M24 ,Rx Buffer 15 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " RX15M23 ,Rx Buffer 15 Mask Bit 23" "Masked,Not masked" bitfld.long 0x08 22. " RX15M22 ,Rx Buffer 15 Mask Bit 22" "Masked,Not masked" bitfld.long 0x08 21. " RX15M21 ,Rx Buffer 15 Mask Bit 21" "Masked,Not masked" bitfld.long 0x08 20. " RX15M20 ,Rx Buffer 15 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " RX15M19 ,Rx Buffer 15 Mask Bit 19" "Masked,Not masked" bitfld.long 0x08 18. " RX15M18 ,Rx Buffer 15 Mask Bit 18" "Masked,Not masked" bitfld.long 0x08 17. " RX15M17 ,Rx Buffer 15 Mask Bit 17" "Masked,Not masked" bitfld.long 0x08 16. " RX15M16 ,Rx Buffer 15 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " RX15M15 ,Rx Buffer 15 Mask Bit 15" "Masked,Not masked" bitfld.long 0x08 14. " RX15M14 ,Rx Buffer 15 Mask Bit 14" "Masked,Not masked" bitfld.long 0x08 13. " RX15M13 ,Rx Buffer 15 Mask Bit 13" "Masked,Not masked" bitfld.long 0x08 12. " RX15M12 ,Rx Buffer 15 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " RX15M11 ,Rx Buffer 15 Mask Bit 11" "Masked,Not masked" bitfld.long 0x08 10. " RX15M10 ,Rx Buffer 15 Mask Bit 10" "Masked,Not masked" bitfld.long 0x08 9. " RX15M9 ,Rx Buffer 15 Mask Bit 9" "Masked,Not masked" bitfld.long 0x08 8. " RX15M8 ,Rx Buffer 15 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " RX15M7 ,Rx Buffer 15 Mask Bit 7" "Masked,Not masked" bitfld.long 0x08 6. " RX15M6 ,Rx Buffer 15 Mask Bit 6" "Masked,Not masked" bitfld.long 0x08 5. " RX15M5 ,Rx Buffer 15 Mask Bit 5" "Masked,Not masked" bitfld.long 0x08 4. " RX15M4 ,Rx Buffer 15 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " RX15M3 ,Rx Buffer 15 Mask Bit 3" "Masked,Not masked" bitfld.long 0x08 2. " RX15M2 ,Rx Buffer 15 Mask Bit 2" "Masked,Not masked" bitfld.long 0x08 1. " RX15M1 ,Rx Buffer 15 Mask Bit 1" "Masked,Not masked" bitfld.long 0x08 0. " RX15M0 ,Rx Buffer 15 Mask Bit 0" "Masked,Not masked" line.long 0x0c "CAN0_ECR,CAN0 Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_CNT ,Receive Error Counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_CNT ,Transmit Error Counter" endif hgroup.long 0x20++0x3 hide.long 0x00 "CAN0_ESR1,CAN0 Error and Status 1 Register" in group.long 0x28++0x3 line.long 0x00 "CAN0_IMASK1,CAN0 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUFHL31 ,Buffer MB31 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 30. " BUFHL30 ,Buffer MB30 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 29. " BUFHL29 ,Buffer MB29 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 28. " BUFHL28 ,Buffer MB28 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " BUFHL27 ,Buffer MB27 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 26. " BUFHL26 ,Buffer MB26 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 25. " BUFHL25 ,Buffer MB25 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 24. " BUFHL24 ,Buffer MB24 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " BUFHL23 ,Buffer MB23 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 22. " BUFHL22 ,Buffer MB22 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 21. " BUFHL21 ,Buffer MB21 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 20. " BUFHL20 ,Buffer MB20 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " BUFHL19 ,Buffer MB19 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 18. " BUFHL18 ,Buffer MB18 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 17. " BUFHL17 ,Buffer MB17 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 16. " BUFHL16 ,Buffer MB16 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " BUFHL15 ,Buffer MB15 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 14. " BUFHL14 ,Buffer MB14 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 13. " BUFHL13 ,Buffer MB13 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 12. " BUFHL12 ,Buffer MB12 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " BUFHL11 ,Buffer MB11 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 10. " BUFHL10 ,Buffer MB10 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 9. " BUFHL9 ,Buffer MB9 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 8. " BUFHL8 ,Buffer MB8 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " BUFHL7 ,Buffer MB7 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 6. " BUFHL6 ,Buffer MB6 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 5. " BUFHL5 ,Buffer MB5 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 4. " BUFHL4 ,Buffer MB4 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " BUFHL3 ,Buffer MB3 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 2. " BUFHL2 ,Buffer MB2 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 1. " BUFHL1 ,Buffer MB1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 0. " BUFHL0 ,Buffer MB0 Interrupt Mask" "Masked,Not masked" if ((per.l(ad:0x40024000)&0x20000000)==0x0) group.long 0x30++0x3 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " BUF28I ,Buffer MB28 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer MB27 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BUF25I ,Buffer MB25 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer MB23 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " BUF22I ,Buffer MB22 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer MB19 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " BUF16I ,Buffer MB16 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer MB15 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " BUF13I ,Buffer MB13 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer MB11 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " BUF10I ,Buffer MB10 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " BUF7I ,Buffer MB7 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " BUF6I ,Buffer MB6 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " BUF5I ,Buffer MB5 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " BUF4I ,Buffer MB4 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " BUF3I ,Buffer MB3 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BUF2I ,Buffer MB2 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " BUF1I ,Buffer MB1 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 Interrupt" "No interrupt,Interrupt" else group.long 0x30++0x3 line.long 0x00 "CAN0_IFLAG1,CAN0 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " BUF28I ,Buffer MB28 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer MB27 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BUF25I ,Buffer MB25 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer MB23 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " BUF22I ,Buffer MB22 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer MB19 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " BUF16I ,Buffer MB16 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer MB15 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " BUF13I ,Buffer MB13 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer MB11 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " BUF10I ,Buffer MB10 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " RFO ,Rx FIFO Overflow" "No overflow,Overflow" eventfld.long 0x00 6. " RFW ,Rx FIFO Warning" "Not full,Almost full" eventfld.long 0x00 5. " FARF ,Frames available in Rx FIFO" "Not available,Available" endif group.long 0x34++0x3 line.long 0x00 "CAN0_CTRL2,CAN0 Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Write-Access to Memory in Freeze mode" "Restricted,Unrestricted" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes" "Disabled,Enabled" rgroup.long 0x38++0x3 line.long 0x00 "CAN0_ESR2,CAN0 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest Priority Tx Mailbox" bitfld.long 0x00 14. " VPS ,Valid Priority Status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive Mailbox" "No Mailbox,Mailbox" rgroup.long 0x44++0x3 line.long 0x00 "CAN0_CRCR,CAN0 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC Mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC Transmitted" if ((per.l(ad:0x40024000)&0x40000000)==0x0) rgroup.long 0x48++0x3 line.long 0x00 "CAN0_RXFGMASK,CAN0 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM31 ,Rx FIFO Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " FGM30 ,Rx FIFO Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " FGM29 ,Rx FIFO Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " FGM28 ,Rx FIFO Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " FGM27 ,Rx FIFO Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " FGM26 ,Rx FIFO Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " FGM25 ,Rx FIFO Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " FGM24 ,Rx FIFO Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " FGM23 ,Rx FIFO Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " FGM22 ,Rx FIFO Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " FGM21 ,Rx FIFO Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " FGM20 ,Rx FIFO Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " FGM19 ,Rx FIFO Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " FGM18 ,Rx FIFO Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " FGM17 ,Rx FIFO Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " FGM16 ,Rx FIFO Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " FGM15 ,Rx FIFO Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " FGM14 ,Rx FIFO Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " FGM13 ,Rx FIFO Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " FGM12 ,Rx FIFO Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " FGM11 ,Rx FIFO Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " FGM10 ,Rx FIFO Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " FGM9 ,Rx FIFO Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " FGM8 ,Rx FIFO Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " FGM7 ,Rx FIFO Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " FGM6 ,Rx FIFO Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " FGM5 ,Rx FIFO Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " FGM4 ,Rx FIFO Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " FGM3 ,Rx FIFO Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " FGM2 ,Rx FIFO Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " FGM1 ,Rx FIFO Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " FGM0 ,Rx FIFO Global Mask Bit 0" "Masked,Not masked" else group.long 0x48++0x3 line.long 0x00 "CAN0_RXFGMASK,CAN0 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM31 ,Rx FIFO Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " FGM30 ,Rx FIFO Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " FGM29 ,Rx FIFO Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " FGM28 ,Rx FIFO Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " FGM27 ,Rx FIFO Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " FGM26 ,Rx FIFO Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " FGM25 ,Rx FIFO Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " FGM24 ,Rx FIFO Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " FGM23 ,Rx FIFO Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " FGM22 ,Rx FIFO Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " FGM21 ,Rx FIFO Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " FGM20 ,Rx FIFO Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " FGM19 ,Rx FIFO Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " FGM18 ,Rx FIFO Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " FGM17 ,Rx FIFO Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " FGM16 ,Rx FIFO Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " FGM15 ,Rx FIFO Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " FGM14 ,Rx FIFO Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " FGM13 ,Rx FIFO Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " FGM12 ,Rx FIFO Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " FGM11 ,Rx FIFO Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " FGM10 ,Rx FIFO Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " FGM9 ,Rx FIFO Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " FGM8 ,Rx FIFO Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " FGM7 ,Rx FIFO Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " FGM6 ,Rx FIFO Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " FGM5 ,Rx FIFO Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " FGM4 ,Rx FIFO Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " FGM3 ,Rx FIFO Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " FGM2 ,Rx FIFO Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " FGM1 ,Rx FIFO Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " FGM0 ,Rx FIFO Global Mask Bit 0" "Masked,Not masked" endif hgroup.long 0x4c++0x3 hide.long 0x00 "CAN0_RXFIR,CAN0 Rx FIFO Information Register" in tree "CAN0 Rx Individual Mask Registers" width 14. if (((per.l(ad:0x40024000)&0x40000000)==0x40000000)) group.long 0x80++0x3 line.long 0x00 "CAN0_RXIMR0,CAN0 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x84++0x3 line.long 0x00 "CAN0_RXIMR1,CAN0 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x88++0x3 line.long 0x00 "CAN0_RXIMR2,CAN0 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x8C++0x3 line.long 0x00 "CAN0_RXIMR3,CAN0 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x90++0x3 line.long 0x00 "CAN0_RXIMR4,CAN0 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x94++0x3 line.long 0x00 "CAN0_RXIMR5,CAN0 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x98++0x3 line.long 0x00 "CAN0_RXIMR6,CAN0 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x9C++0x3 line.long 0x00 "CAN0_RXIMR7,CAN0 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA0++0x3 line.long 0x00 "CAN0_RXIMR8,CAN0 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA4++0x3 line.long 0x00 "CAN0_RXIMR9,CAN0 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA8++0x3 line.long 0x00 "CAN0_RXIMR10,CAN0 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xAC++0x3 line.long 0x00 "CAN0_RXIMR11,CAN0 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB0++0x3 line.long 0x00 "CAN0_RXIMR12,CAN0 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB4++0x3 line.long 0x00 "CAN0_RXIMR13,CAN0 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB8++0x3 line.long 0x00 "CAN0_RXIMR14,CAN0 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xBC++0x3 line.long 0x00 "CAN0_RXIMR15,CAN0 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" else rgroup.long 0x80++0x3 line.long 0x00 "CAN0_RXIMR0,CAN0 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x84++0x3 line.long 0x00 "CAN0_RXIMR1,CAN0 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x88++0x3 line.long 0x00 "CAN0_RXIMR2,CAN0 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x8C++0x3 line.long 0x00 "CAN0_RXIMR3,CAN0 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x90++0x3 line.long 0x00 "CAN0_RXIMR4,CAN0 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x94++0x3 line.long 0x00 "CAN0_RXIMR5,CAN0 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x98++0x3 line.long 0x00 "CAN0_RXIMR6,CAN0 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x9C++0x3 line.long 0x00 "CAN0_RXIMR7,CAN0 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA0++0x3 line.long 0x00 "CAN0_RXIMR8,CAN0 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA4++0x3 line.long 0x00 "CAN0_RXIMR9,CAN0 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA8++0x3 line.long 0x00 "CAN0_RXIMR10,CAN0 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xAC++0x3 line.long 0x00 "CAN0_RXIMR11,CAN0 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB0++0x3 line.long 0x00 "CAN0_RXIMR12,CAN0 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB4++0x3 line.long 0x00 "CAN0_RXIMR13,CAN0 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB8++0x3 line.long 0x00 "CAN0_RXIMR14,CAN0 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xBC++0x3 line.long 0x00 "CAN0_RXIMR15,CAN0 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" endif tree.end width 11. tree.end tree "CAN1" base ad:0x400A4000 width 15. group.long 0x00++0xb line.long 0x00 "CAN1_MCR,CAN1 Module Configuration Register" bitfld.long 0x00 31. " MDIS ,Module Disable" "No,Yes" bitfld.long 0x00 30. " FRZ ,Freeze Enable" "Disabled,Enabled" bitfld.long 0x00 29. " RFEN ,Rx FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Halt FlexCAN" "Not halted,Halted" textline " " rbitfld.long 0x00 27. " NOT_RDY ,FlexCAN Not Ready" "Ready,Not ready" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 25. " SOFT_RST ,Soft Reset" "No reset,Reset" rbitfld.long 0x00 24. " FRZ_ACK ,Freeze Mode Acknowledge" "Not Freeze,Freeze" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor Mode" "User,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,Self Wake Up Enable" "Disabled,Enabled" bitfld.long 0x00 21. " WRN_EN ,Warning Interrupt Enable" "Disabled,Enabled" rbitfld.long 0x00 20. " LPM_ACK ,Low Power Mode Acknowledge" "Not LPM,LPM" textline " " sif (cpuis("MK70*")) bitfld.long 0x00 19. " WAKSRC ,Wake Up Source" "Unfiltered RX input,Filtered RX input" textline " " endif bitfld.long 0x00 17. " SRX_DIS ,Self Reception Disable" "No,Yes" bitfld.long 0x00 16. " IRMQ ,Individual Rx Masking and Queue Enable" "Disabled,Enabled" bitfld.long 0x00 13. " LPRIO_EN ,Local Priority Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,Abort Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,ID Acceptance Mode" "Format A,Format B,Format C,Format D" hexmask.long.byte 0x00 0.--6. 1. " MAXMB ,Number of the Last Message Buffer" line.long 0x04 "CAN1_CTRL1,CAN1 Control 1 Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Prescaler Division Factor" bitfld.long 0x04 22.--23. " RJW ,Resync Jump Width" "1,2,3,4" bitfld.long 0x04 19.--21. " PSEG1 ,Phase Segment 1" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" bitfld.long 0x04 16.--18. " PSEG2 ,Phase Segment 2" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Bus Off Mask" "Masked,Not masked" bitfld.long 0x04 14. " ERR_MSK ,Error Mask" "Masked,Not masked" bitfld.long 0x04 13. " CLK_SRC ,CAN Engine Clock Source" "Oscillator clk,Peripheral clk" bitfld.long 0x04 12. " LPB ,Loop Back" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRN_MSK ,Tx Warning Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 10. " RWRN_MSK ,Rx Warning Interrupt Mask" "Masked,Not masked" bitfld.long 0x04 7. " SMP ,Sampling Mode" "One sample,Three samples" bitfld.long 0x04 6. " BOFF_REC ,Bus Off Recovery Mode Disable" "No,Yes" textline " " bitfld.long 0x04 5. " TSYN ,Timer Sync Mode " "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Lowest Buffer Transmitted First" "Highest,Lowest" bitfld.long 0x04 3. " LOM ,Listen-Only Mode" "Deactivated,Activated" bitfld.long 0x04 0.--2. " PROPSEG ,Propagation Segment" "1 x Time-Quanta,2 x Time-Quanta,3 x Time-Quanta,4 x Time-Quanta,5 x Time-Quanta,6 x Time-Quanta,7 x Time-Quanta,8 x Time-Quanta" line.long 0x08 "CAN1_TIMER,CAN1 Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Timer value" if ((per.l(ad:0x400A4000)&0x40000000)==0x0) rgroup.long 0x10++0x17 line.long 0x00 "CAN1_RXMGMASK,CAN1 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Rx Mailboxes Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Rx Mailboxes Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Rx Mailboxes Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Rx Mailboxes Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Rx Mailboxes Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Rx Mailboxes Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Rx Mailboxes Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Rx Mailboxes Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Rx Mailboxes Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Rx Mailboxes Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Rx Mailboxes Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Rx Mailboxes Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Rx Mailboxes Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Rx Mailboxes Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Rx Mailboxes Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Rx Mailboxes Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Rx Mailboxes Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Rx Mailboxes Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Rx Mailboxes Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Rx Mailboxes Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Rx Mailboxes Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Rx Mailboxes Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Rx Mailboxes Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Rx Mailboxes Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Rx Mailboxes Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Rx Mailboxes Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Rx Mailboxes Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Rx Mailboxes Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Rx Mailboxes Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Rx Mailboxes Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Rx Mailboxes Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Rx Mailboxes Global Mask Bit 0" "Masked,Not masked" line.long 0x04 "CAN1_RX14MASK,CAN1 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M31 ,Rx Buffer 14 Mask Bit 31" "Masked,Not masked" bitfld.long 0x04 30. " RX14M30 ,Rx Buffer 14 Mask Bit 30" "Masked,Not masked" bitfld.long 0x04 29. " RX14M29 ,Rx Buffer 14 Mask Bit 29" "Masked,Not masked" bitfld.long 0x04 28. " RX14M28 ,Rx Buffer 14 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " RX14M27 ,Rx Buffer 14 Mask Bit 27" "Masked,Not masked" bitfld.long 0x04 26. " RX14M26 ,Rx Buffer 14 Mask Bit 26" "Masked,Not masked" bitfld.long 0x04 25. " RX14M25 ,Rx Buffer 14 Mask Bit 25" "Masked,Not masked" bitfld.long 0x04 24. " RX14M24 ,Rx Buffer 14 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " RX14M23 ,Rx Buffer 14 Mask Bit 23" "Masked,Not masked" bitfld.long 0x04 22. " RX14M22 ,Rx Buffer 14 Mask Bit 22" "Masked,Not masked" bitfld.long 0x04 21. " RX14M21 ,Rx Buffer 14 Mask Bit 21" "Masked,Not masked" bitfld.long 0x04 20. " RX14M20 ,Rx Buffer 14 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " RX14M19 ,Rx Buffer 14 Mask Bit 19" "Masked,Not masked" bitfld.long 0x04 18. " RX14M18 ,Rx Buffer 14 Mask Bit 18" "Masked,Not masked" bitfld.long 0x04 17. " RX14M17 ,Rx Buffer 14 Mask Bit 17" "Masked,Not masked" bitfld.long 0x04 16. " RX14M16 ,Rx Buffer 14 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " RX14M15 ,Rx Buffer 14 Mask Bit 15" "Masked,Not masked" bitfld.long 0x04 14. " RX14M14 ,Rx Buffer 14 Mask Bit 14" "Masked,Not masked" bitfld.long 0x04 13. " RX14M13 ,Rx Buffer 14 Mask Bit 13" "Masked,Not masked" bitfld.long 0x04 12. " RX14M12 ,Rx Buffer 14 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " RX14M11 ,Rx Buffer 14 Mask Bit 11" "Masked,Not masked" bitfld.long 0x04 10. " RX14M10 ,Rx Buffer 14 Mask Bit 10" "Masked,Not masked" bitfld.long 0x04 9. " RX14M9 ,Rx Buffer 14 Mask Bit 9" "Masked,Not masked" bitfld.long 0x04 8. " RX14M8 ,Rx Buffer 14 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " RX14M7 ,Rx Buffer 14 Mask Bit 7" "Masked,Not masked" bitfld.long 0x04 6. " RX14M6 ,Rx Buffer 14 Mask Bit 6" "Masked,Not masked" bitfld.long 0x04 5. " RX14M5 ,Rx Buffer 14 Mask Bit 5" "Masked,Not masked" bitfld.long 0x04 4. " RX14M4 ,Rx Buffer 14 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " RX14M3 ,Rx Buffer 14 Mask Bit 3" "Masked,Not masked" bitfld.long 0x04 2. " RX14M2 ,Rx Buffer 14 Mask Bit 2" "Masked,Not masked" bitfld.long 0x04 1. " RX14M1 ,Rx Buffer 14 Mask Bit 1" "Masked,Not masked" bitfld.long 0x04 0. " RX14M0 ,Rx Buffer 14 Mask Bit 0" "Masked,Not masked" line.long 0x08 "CAN1_RX15MASK,CAN1 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M31 ,Rx Buffer 15 Mask Bit 31" "Masked,Not masked" bitfld.long 0x08 30. " RX15M30 ,Rx Buffer 15 Mask Bit 30" "Masked,Not masked" bitfld.long 0x08 29. " RX15M29 ,Rx Buffer 15 Mask Bit 29" "Masked,Not masked" bitfld.long 0x08 28. " RX15M28 ,Rx Buffer 15 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " RX15M27 ,Rx Buffer 15 Mask Bit 27" "Masked,Not masked" bitfld.long 0x08 26. " RX15M26 ,Rx Buffer 15 Mask Bit 26" "Masked,Not masked" bitfld.long 0x08 25. " RX15M25 ,Rx Buffer 15 Mask Bit 25" "Masked,Not masked" bitfld.long 0x08 24. " RX15M24 ,Rx Buffer 15 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " RX15M23 ,Rx Buffer 15 Mask Bit 23" "Masked,Not masked" bitfld.long 0x08 22. " RX15M22 ,Rx Buffer 15 Mask Bit 22" "Masked,Not masked" bitfld.long 0x08 21. " RX15M21 ,Rx Buffer 15 Mask Bit 21" "Masked,Not masked" bitfld.long 0x08 20. " RX15M20 ,Rx Buffer 15 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " RX15M19 ,Rx Buffer 15 Mask Bit 19" "Masked,Not masked" bitfld.long 0x08 18. " RX15M18 ,Rx Buffer 15 Mask Bit 18" "Masked,Not masked" bitfld.long 0x08 17. " RX15M17 ,Rx Buffer 15 Mask Bit 17" "Masked,Not masked" bitfld.long 0x08 16. " RX15M16 ,Rx Buffer 15 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " RX15M15 ,Rx Buffer 15 Mask Bit 15" "Masked,Not masked" bitfld.long 0x08 14. " RX15M14 ,Rx Buffer 15 Mask Bit 14" "Masked,Not masked" bitfld.long 0x08 13. " RX15M13 ,Rx Buffer 15 Mask Bit 13" "Masked,Not masked" bitfld.long 0x08 12. " RX15M12 ,Rx Buffer 15 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " RX15M11 ,Rx Buffer 15 Mask Bit 11" "Masked,Not masked" bitfld.long 0x08 10. " RX15M10 ,Rx Buffer 15 Mask Bit 10" "Masked,Not masked" bitfld.long 0x08 9. " RX15M9 ,Rx Buffer 15 Mask Bit 9" "Masked,Not masked" bitfld.long 0x08 8. " RX15M8 ,Rx Buffer 15 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " RX15M7 ,Rx Buffer 15 Mask Bit 7" "Masked,Not masked" bitfld.long 0x08 6. " RX15M6 ,Rx Buffer 15 Mask Bit 6" "Masked,Not masked" bitfld.long 0x08 5. " RX15M5 ,Rx Buffer 15 Mask Bit 5" "Masked,Not masked" bitfld.long 0x08 4. " RX15M4 ,Rx Buffer 15 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " RX15M3 ,Rx Buffer 15 Mask Bit 3" "Masked,Not masked" bitfld.long 0x08 2. " RX15M2 ,Rx Buffer 15 Mask Bit 2" "Masked,Not masked" bitfld.long 0x08 1. " RX15M1 ,Rx Buffer 15 Mask Bit 1" "Masked,Not masked" bitfld.long 0x08 0. " RX15M0 ,Rx Buffer 15 Mask Bit 0" "Masked,Not masked" line.long 0x0c "CAN1_ECR,CAN1 Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_CNT ,Receive Error Counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_CNT ,Transmit Error Counter" else group.long 0x10++0x17 line.long 0x00 "CAN1_RXMGMASK,CAN1 Rx Mailboxes Global Mask Register" bitfld.long 0x00 31. " MG31 ,Rx Mailboxes Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MG30 ,Rx Mailboxes Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MG29 ,Rx Mailboxes Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MG28 ,Rx Mailboxes Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MG27 ,Rx Mailboxes Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MG26 ,Rx Mailboxes Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MG25 ,Rx Mailboxes Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MG24 ,Rx Mailboxes Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MG23 ,Rx Mailboxes Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MG22 ,Rx Mailboxes Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MG21 ,Rx Mailboxes Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MG20 ,Rx Mailboxes Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MG19 ,Rx Mailboxes Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MG18 ,Rx Mailboxes Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MG17 ,Rx Mailboxes Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MG16 ,Rx Mailboxes Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MG15 ,Rx Mailboxes Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MG14 ,Rx Mailboxes Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MG13 ,Rx Mailboxes Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MG12 ,Rx Mailboxes Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MG11 ,Rx Mailboxes Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MG10 ,Rx Mailboxes Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MG9 ,Rx Mailboxes Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MG8 ,Rx Mailboxes Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MG7 ,Rx Mailboxes Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MG6 ,Rx Mailboxes Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MG5 ,Rx Mailboxes Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MG4 ,Rx Mailboxes Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MG3 ,Rx Mailboxes Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MG2 ,Rx Mailboxes Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MG1 ,Rx Mailboxes Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MG0 ,Rx Mailboxes Global Mask Bit 0" "Masked,Not masked" line.long 0x04 "CAN1_RX14MASK,CAN1 Rx 14 Mask Register" bitfld.long 0x04 31. " RX14M31 ,Rx Buffer 14 Mask Bit 31" "Masked,Not masked" bitfld.long 0x04 30. " RX14M30 ,Rx Buffer 14 Mask Bit 30" "Masked,Not masked" bitfld.long 0x04 29. " RX14M29 ,Rx Buffer 14 Mask Bit 29" "Masked,Not masked" bitfld.long 0x04 28. " RX14M28 ,Rx Buffer 14 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x04 27. " RX14M27 ,Rx Buffer 14 Mask Bit 27" "Masked,Not masked" bitfld.long 0x04 26. " RX14M26 ,Rx Buffer 14 Mask Bit 26" "Masked,Not masked" bitfld.long 0x04 25. " RX14M25 ,Rx Buffer 14 Mask Bit 25" "Masked,Not masked" bitfld.long 0x04 24. " RX14M24 ,Rx Buffer 14 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x04 23. " RX14M23 ,Rx Buffer 14 Mask Bit 23" "Masked,Not masked" bitfld.long 0x04 22. " RX14M22 ,Rx Buffer 14 Mask Bit 22" "Masked,Not masked" bitfld.long 0x04 21. " RX14M21 ,Rx Buffer 14 Mask Bit 21" "Masked,Not masked" bitfld.long 0x04 20. " RX14M20 ,Rx Buffer 14 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x04 19. " RX14M19 ,Rx Buffer 14 Mask Bit 19" "Masked,Not masked" bitfld.long 0x04 18. " RX14M18 ,Rx Buffer 14 Mask Bit 18" "Masked,Not masked" bitfld.long 0x04 17. " RX14M17 ,Rx Buffer 14 Mask Bit 17" "Masked,Not masked" bitfld.long 0x04 16. " RX14M16 ,Rx Buffer 14 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x04 15. " RX14M15 ,Rx Buffer 14 Mask Bit 15" "Masked,Not masked" bitfld.long 0x04 14. " RX14M14 ,Rx Buffer 14 Mask Bit 14" "Masked,Not masked" bitfld.long 0x04 13. " RX14M13 ,Rx Buffer 14 Mask Bit 13" "Masked,Not masked" bitfld.long 0x04 12. " RX14M12 ,Rx Buffer 14 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x04 11. " RX14M11 ,Rx Buffer 14 Mask Bit 11" "Masked,Not masked" bitfld.long 0x04 10. " RX14M10 ,Rx Buffer 14 Mask Bit 10" "Masked,Not masked" bitfld.long 0x04 9. " RX14M9 ,Rx Buffer 14 Mask Bit 9" "Masked,Not masked" bitfld.long 0x04 8. " RX14M8 ,Rx Buffer 14 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x04 7. " RX14M7 ,Rx Buffer 14 Mask Bit 7" "Masked,Not masked" bitfld.long 0x04 6. " RX14M6 ,Rx Buffer 14 Mask Bit 6" "Masked,Not masked" bitfld.long 0x04 5. " RX14M5 ,Rx Buffer 14 Mask Bit 5" "Masked,Not masked" bitfld.long 0x04 4. " RX14M4 ,Rx Buffer 14 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x04 3. " RX14M3 ,Rx Buffer 14 Mask Bit 3" "Masked,Not masked" bitfld.long 0x04 2. " RX14M2 ,Rx Buffer 14 Mask Bit 2" "Masked,Not masked" bitfld.long 0x04 1. " RX14M1 ,Rx Buffer 14 Mask Bit 1" "Masked,Not masked" bitfld.long 0x04 0. " RX14M0 ,Rx Buffer 14 Mask Bit 0" "Masked,Not masked" line.long 0x08 "CAN1_RX15MASK,CAN1 Rx 15 Mask Register" bitfld.long 0x08 31. " RX15M31 ,Rx Buffer 15 Mask Bit 31" "Masked,Not masked" bitfld.long 0x08 30. " RX15M30 ,Rx Buffer 15 Mask Bit 30" "Masked,Not masked" bitfld.long 0x08 29. " RX15M29 ,Rx Buffer 15 Mask Bit 29" "Masked,Not masked" bitfld.long 0x08 28. " RX15M28 ,Rx Buffer 15 Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x08 27. " RX15M27 ,Rx Buffer 15 Mask Bit 27" "Masked,Not masked" bitfld.long 0x08 26. " RX15M26 ,Rx Buffer 15 Mask Bit 26" "Masked,Not masked" bitfld.long 0x08 25. " RX15M25 ,Rx Buffer 15 Mask Bit 25" "Masked,Not masked" bitfld.long 0x08 24. " RX15M24 ,Rx Buffer 15 Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x08 23. " RX15M23 ,Rx Buffer 15 Mask Bit 23" "Masked,Not masked" bitfld.long 0x08 22. " RX15M22 ,Rx Buffer 15 Mask Bit 22" "Masked,Not masked" bitfld.long 0x08 21. " RX15M21 ,Rx Buffer 15 Mask Bit 21" "Masked,Not masked" bitfld.long 0x08 20. " RX15M20 ,Rx Buffer 15 Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x08 19. " RX15M19 ,Rx Buffer 15 Mask Bit 19" "Masked,Not masked" bitfld.long 0x08 18. " RX15M18 ,Rx Buffer 15 Mask Bit 18" "Masked,Not masked" bitfld.long 0x08 17. " RX15M17 ,Rx Buffer 15 Mask Bit 17" "Masked,Not masked" bitfld.long 0x08 16. " RX15M16 ,Rx Buffer 15 Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x08 15. " RX15M15 ,Rx Buffer 15 Mask Bit 15" "Masked,Not masked" bitfld.long 0x08 14. " RX15M14 ,Rx Buffer 15 Mask Bit 14" "Masked,Not masked" bitfld.long 0x08 13. " RX15M13 ,Rx Buffer 15 Mask Bit 13" "Masked,Not masked" bitfld.long 0x08 12. " RX15M12 ,Rx Buffer 15 Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x08 11. " RX15M11 ,Rx Buffer 15 Mask Bit 11" "Masked,Not masked" bitfld.long 0x08 10. " RX15M10 ,Rx Buffer 15 Mask Bit 10" "Masked,Not masked" bitfld.long 0x08 9. " RX15M9 ,Rx Buffer 15 Mask Bit 9" "Masked,Not masked" bitfld.long 0x08 8. " RX15M8 ,Rx Buffer 15 Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x08 7. " RX15M7 ,Rx Buffer 15 Mask Bit 7" "Masked,Not masked" bitfld.long 0x08 6. " RX15M6 ,Rx Buffer 15 Mask Bit 6" "Masked,Not masked" bitfld.long 0x08 5. " RX15M5 ,Rx Buffer 15 Mask Bit 5" "Masked,Not masked" bitfld.long 0x08 4. " RX15M4 ,Rx Buffer 15 Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x08 3. " RX15M3 ,Rx Buffer 15 Mask Bit 3" "Masked,Not masked" bitfld.long 0x08 2. " RX15M2 ,Rx Buffer 15 Mask Bit 2" "Masked,Not masked" bitfld.long 0x08 1. " RX15M1 ,Rx Buffer 15 Mask Bit 1" "Masked,Not masked" bitfld.long 0x08 0. " RX15M0 ,Rx Buffer 15 Mask Bit 0" "Masked,Not masked" line.long 0x0c "CAN1_ECR,CAN1 Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_CNT ,Receive Error Counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_CNT ,Transmit Error Counter" endif hgroup.long 0x20++0x3 hide.long 0x00 "CAN1_ESR1,CAN1 Error and Status 1 Register" in group.long 0x28++0x3 line.long 0x00 "CAN1_IMASK1,CAN1 Interrupt Masks 1 Register" bitfld.long 0x00 31. " BUFHL31 ,Buffer MB31 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 30. " BUFHL30 ,Buffer MB30 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 29. " BUFHL29 ,Buffer MB29 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 28. " BUFHL28 ,Buffer MB28 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 27. " BUFHL27 ,Buffer MB27 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 26. " BUFHL26 ,Buffer MB26 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 25. " BUFHL25 ,Buffer MB25 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 24. " BUFHL24 ,Buffer MB24 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 23. " BUFHL23 ,Buffer MB23 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 22. " BUFHL22 ,Buffer MB22 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 21. " BUFHL21 ,Buffer MB21 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 20. " BUFHL20 ,Buffer MB20 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 19. " BUFHL19 ,Buffer MB19 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 18. " BUFHL18 ,Buffer MB18 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 17. " BUFHL17 ,Buffer MB17 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 16. " BUFHL16 ,Buffer MB16 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 15. " BUFHL15 ,Buffer MB15 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 14. " BUFHL14 ,Buffer MB14 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 13. " BUFHL13 ,Buffer MB13 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 12. " BUFHL12 ,Buffer MB12 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 11. " BUFHL11 ,Buffer MB11 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 10. " BUFHL10 ,Buffer MB10 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 9. " BUFHL9 ,Buffer MB9 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 8. " BUFHL8 ,Buffer MB8 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 7. " BUFHL7 ,Buffer MB7 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 6. " BUFHL6 ,Buffer MB6 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 5. " BUFHL5 ,Buffer MB5 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 4. " BUFHL4 ,Buffer MB4 Interrupt Mask" "Masked,Not masked" textline " " bitfld.long 0x00 3. " BUFHL3 ,Buffer MB3 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 2. " BUFHL2 ,Buffer MB2 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 1. " BUFHL1 ,Buffer MB1 Interrupt Mask" "Masked,Not masked" bitfld.long 0x00 0. " BUFHL0 ,Buffer MB0 Interrupt Mask" "Masked,Not masked" if ((per.l(ad:0x400A4000)&0x20000000)==0x0) group.long 0x30++0x3 line.long 0x00 "CAN1_IFLAG1,CAN1 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " BUF28I ,Buffer MB28 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer MB27 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BUF25I ,Buffer MB25 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer MB23 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " BUF22I ,Buffer MB22 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer MB19 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " BUF16I ,Buffer MB16 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer MB15 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " BUF13I ,Buffer MB13 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer MB11 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " BUF10I ,Buffer MB10 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " BUF7I ,Buffer MB7 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " BUF6I ,Buffer MB6 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " BUF5I ,Buffer MB5 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " BUF4I ,Buffer MB4 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " BUF3I ,Buffer MB3 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " BUF2I ,Buffer MB2 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " BUF1I ,Buffer MB1 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " BUF0I ,Buffer MB0 Interrupt" "No interrupt,Interrupt" else group.long 0x30++0x3 line.long 0x00 "CAN1_IFLAG1,CAN1 Interrupt Flags 1 Register" eventfld.long 0x00 31. " BUF31I ,Buffer MB31 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " BUF30I ,Buffer MB30 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 29. " BUF29I ,Buffer MB29 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " BUF28I ,Buffer MB28 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " BUF27I ,Buffer MB27 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " BUF26I ,Buffer MB26 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " BUF25I ,Buffer MB25 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " BUF24I ,Buffer MB24 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " BUF23I ,Buffer MB23 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " BUF22I ,Buffer MB22 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 21. " BUF21I ,Buffer MB21 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " BUF20I ,Buffer MB20 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " BUF19I ,Buffer MB19 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " BUF18I ,Buffer MB18 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 17. " BUF17I ,Buffer MB17 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " BUF16I ,Buffer MB16 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " BUF15I ,Buffer MB15 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " BUF14I ,Buffer MB14 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " BUF13I ,Buffer MB13 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " BUF12I ,Buffer MB12 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " BUF11I ,Buffer MB11 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " BUF10I ,Buffer MB10 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUF9I ,Buffer MB9 Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " BUF8I ,Buffer MB8 Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " RFO ,Rx FIFO Overflow" "No overflow,Overflow" eventfld.long 0x00 6. " RFW ,Rx FIFO Warning" "Not full,Almost full" eventfld.long 0x00 5. " FARF ,Frames available in Rx FIFO" "Not available,Available" endif group.long 0x34++0x3 line.long 0x00 "CAN1_CTRL2,CAN1 Control 2 Register" bitfld.long 0x00 28. " WRMFRZ ,Write-Access to Memory in Freeze mode" "Restricted,Unrestricted" bitfld.long 0x00 24.--27. " RFFN ,Number of Rx FIFO Filters" "8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128" bitfld.long 0x00 19.--23. " TASD ,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 18. " MRP ,Mailboxes Reception Priority" "Rx FIFO -> Mailboxes,Mailboxes -> Rx FIFO" bitfld.long 0x00 17. " RRS ,Remote Request Storing" "Generated,Stored" bitfld.long 0x00 16. " EACEN ,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes" "Disabled,Enabled" rgroup.long 0x38++0x3 line.long 0x00 "CAN1_ESR2,CAN1 Error and Status 2 Register" hexmask.long.byte 0x00 16.--22. 1. " LPTM ,Lowest Priority Tx Mailbox" bitfld.long 0x00 14. " VPS ,Valid Priority Status" "Invalid,Valid" bitfld.long 0x00 13. " IMB ,Inactive Mailbox" "No Mailbox,Mailbox" rgroup.long 0x44++0x3 line.long 0x00 "CAN1_CRCR,CAN1 CRC Register" hexmask.long.byte 0x00 16.--22. 1. " MBCRC ,CRC Mailbox" hexmask.long.word 0x00 0.--14. 1. " TXCRC ,CRC Transmitted" if ((per.l(ad:0x400A4000)&0x40000000)==0x0) rgroup.long 0x48++0x3 line.long 0x00 "CAN1_RXFGMASK,CAN1 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM31 ,Rx FIFO Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " FGM30 ,Rx FIFO Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " FGM29 ,Rx FIFO Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " FGM28 ,Rx FIFO Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " FGM27 ,Rx FIFO Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " FGM26 ,Rx FIFO Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " FGM25 ,Rx FIFO Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " FGM24 ,Rx FIFO Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " FGM23 ,Rx FIFO Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " FGM22 ,Rx FIFO Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " FGM21 ,Rx FIFO Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " FGM20 ,Rx FIFO Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " FGM19 ,Rx FIFO Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " FGM18 ,Rx FIFO Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " FGM17 ,Rx FIFO Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " FGM16 ,Rx FIFO Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " FGM15 ,Rx FIFO Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " FGM14 ,Rx FIFO Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " FGM13 ,Rx FIFO Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " FGM12 ,Rx FIFO Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " FGM11 ,Rx FIFO Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " FGM10 ,Rx FIFO Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " FGM9 ,Rx FIFO Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " FGM8 ,Rx FIFO Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " FGM7 ,Rx FIFO Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " FGM6 ,Rx FIFO Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " FGM5 ,Rx FIFO Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " FGM4 ,Rx FIFO Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " FGM3 ,Rx FIFO Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " FGM2 ,Rx FIFO Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " FGM1 ,Rx FIFO Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " FGM0 ,Rx FIFO Global Mask Bit 0" "Masked,Not masked" else group.long 0x48++0x3 line.long 0x00 "CAN1_RXFGMASK,CAN1 Rx FIFO Global Mask Register" bitfld.long 0x00 31. " FGM31 ,Rx FIFO Global Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " FGM30 ,Rx FIFO Global Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " FGM29 ,Rx FIFO Global Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " FGM28 ,Rx FIFO Global Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " FGM27 ,Rx FIFO Global Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " FGM26 ,Rx FIFO Global Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " FGM25 ,Rx FIFO Global Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " FGM24 ,Rx FIFO Global Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " FGM23 ,Rx FIFO Global Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " FGM22 ,Rx FIFO Global Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " FGM21 ,Rx FIFO Global Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " FGM20 ,Rx FIFO Global Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " FGM19 ,Rx FIFO Global Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " FGM18 ,Rx FIFO Global Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " FGM17 ,Rx FIFO Global Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " FGM16 ,Rx FIFO Global Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " FGM15 ,Rx FIFO Global Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " FGM14 ,Rx FIFO Global Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " FGM13 ,Rx FIFO Global Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " FGM12 ,Rx FIFO Global Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " FGM11 ,Rx FIFO Global Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " FGM10 ,Rx FIFO Global Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " FGM9 ,Rx FIFO Global Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " FGM8 ,Rx FIFO Global Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " FGM7 ,Rx FIFO Global Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " FGM6 ,Rx FIFO Global Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " FGM5 ,Rx FIFO Global Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " FGM4 ,Rx FIFO Global Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " FGM3 ,Rx FIFO Global Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " FGM2 ,Rx FIFO Global Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " FGM1 ,Rx FIFO Global Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " FGM0 ,Rx FIFO Global Mask Bit 0" "Masked,Not masked" endif hgroup.long 0x4c++0x3 hide.long 0x00 "CAN1_RXFIR,CAN1 Rx FIFO Information Register" in tree "CAN1 Rx Individual Mask Registers" width 14. if (((per.l(ad:0x400A4000)&0x40000000)==0x40000000)) group.long 0x80++0x3 line.long 0x00 "CAN1_RXIMR0,CAN1 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x84++0x3 line.long 0x00 "CAN1_RXIMR1,CAN1 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x88++0x3 line.long 0x00 "CAN1_RXIMR2,CAN1 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x8C++0x3 line.long 0x00 "CAN1_RXIMR3,CAN1 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x90++0x3 line.long 0x00 "CAN1_RXIMR4,CAN1 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x94++0x3 line.long 0x00 "CAN1_RXIMR5,CAN1 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x98++0x3 line.long 0x00 "CAN1_RXIMR6,CAN1 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0x9C++0x3 line.long 0x00 "CAN1_RXIMR7,CAN1 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA0++0x3 line.long 0x00 "CAN1_RXIMR8,CAN1 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA4++0x3 line.long 0x00 "CAN1_RXIMR9,CAN1 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xA8++0x3 line.long 0x00 "CAN1_RXIMR10,CAN1 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xAC++0x3 line.long 0x00 "CAN1_RXIMR11,CAN1 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB0++0x3 line.long 0x00 "CAN1_RXIMR12,CAN1 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB4++0x3 line.long 0x00 "CAN1_RXIMR13,CAN1 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xB8++0x3 line.long 0x00 "CAN1_RXIMR14,CAN1 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" group.long 0xBC++0x3 line.long 0x00 "CAN1_RXIMR15,CAN1 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" else rgroup.long 0x80++0x3 line.long 0x00 "CAN1_RXIMR0,CAN1 Rx Individual Mask Register 0 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x84++0x3 line.long 0x00 "CAN1_RXIMR1,CAN1 Rx Individual Mask Register 1 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x88++0x3 line.long 0x00 "CAN1_RXIMR2,CAN1 Rx Individual Mask Register 2 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x8C++0x3 line.long 0x00 "CAN1_RXIMR3,CAN1 Rx Individual Mask Register 3 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x90++0x3 line.long 0x00 "CAN1_RXIMR4,CAN1 Rx Individual Mask Register 4 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x94++0x3 line.long 0x00 "CAN1_RXIMR5,CAN1 Rx Individual Mask Register 5 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x98++0x3 line.long 0x00 "CAN1_RXIMR6,CAN1 Rx Individual Mask Register 6 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0x9C++0x3 line.long 0x00 "CAN1_RXIMR7,CAN1 Rx Individual Mask Register 7 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA0++0x3 line.long 0x00 "CAN1_RXIMR8,CAN1 Rx Individual Mask Register 8 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA4++0x3 line.long 0x00 "CAN1_RXIMR9,CAN1 Rx Individual Mask Register 9 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xA8++0x3 line.long 0x00 "CAN1_RXIMR10,CAN1 Rx Individual Mask Register 10 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xAC++0x3 line.long 0x00 "CAN1_RXIMR11,CAN1 Rx Individual Mask Register 11 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB0++0x3 line.long 0x00 "CAN1_RXIMR12,CAN1 Rx Individual Mask Register 12 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB4++0x3 line.long 0x00 "CAN1_RXIMR13,CAN1 Rx Individual Mask Register 13 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xB8++0x3 line.long 0x00 "CAN1_RXIMR14,CAN1 Rx Individual Mask Register 14 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" rgroup.long 0xBC++0x3 line.long 0x00 "CAN1_RXIMR15,CAN1 Rx Individual Mask Register 15 Register" bitfld.long 0x00 31. " MI31 ,Individual Mask Bit 31" "Masked,Not masked" bitfld.long 0x00 30. " MI30 ,Individual Mask Bit 30" "Masked,Not masked" bitfld.long 0x00 29. " MI29 ,Individual Mask Bit 29" "Masked,Not masked" bitfld.long 0x00 28. " MI28 ,Individual Mask Bit 28" "Masked,Not masked" textline " " bitfld.long 0x00 27. " MI27 ,Individual Mask Bit 27" "Masked,Not masked" bitfld.long 0x00 26. " MI26 ,Individual Mask Bit 26" "Masked,Not masked" bitfld.long 0x00 25. " MI25 ,Individual Mask Bit 25" "Masked,Not masked" bitfld.long 0x00 24. " MI24 ,Individual Mask Bit 24" "Masked,Not masked" textline " " bitfld.long 0x00 23. " MI23 ,Individual Mask Bit 23" "Masked,Not masked" bitfld.long 0x00 22. " MI22 ,Individual Mask Bit 22" "Masked,Not masked" bitfld.long 0x00 21. " MI21 ,Individual Mask Bit 21" "Masked,Not masked" bitfld.long 0x00 20. " MI20 ,Individual Mask Bit 20" "Masked,Not masked" textline " " bitfld.long 0x00 19. " MI19 ,Individual Mask Bit 19" "Masked,Not masked" bitfld.long 0x00 18. " MI18 ,Individual Mask Bit 18" "Masked,Not masked" bitfld.long 0x00 17. " MI17 ,Individual Mask Bit 17" "Masked,Not masked" bitfld.long 0x00 16. " MI16 ,Individual Mask Bit 16" "Masked,Not masked" textline " " bitfld.long 0x00 15. " MI15 ,Individual Mask Bit 15" "Masked,Not masked" bitfld.long 0x00 14. " MI14 ,Individual Mask Bit 14" "Masked,Not masked" bitfld.long 0x00 13. " MI13 ,Individual Mask Bit 13" "Masked,Not masked" bitfld.long 0x00 12. " MI12 ,Individual Mask Bit 12" "Masked,Not masked" textline " " bitfld.long 0x00 11. " MI11 ,Individual Mask Bit 11" "Masked,Not masked" bitfld.long 0x00 10. " MI10 ,Individual Mask Bit 10" "Masked,Not masked" bitfld.long 0x00 9. " MI9 ,Individual Mask Bit 9" "Masked,Not masked" bitfld.long 0x00 8. " MI8 ,Individual Mask Bit 8" "Masked,Not masked" textline " " bitfld.long 0x00 7. " MI7 ,Individual Mask Bit 7" "Masked,Not masked" bitfld.long 0x00 6. " MI6 ,Individual Mask Bit 6" "Masked,Not masked" bitfld.long 0x00 5. " MI5 ,Individual Mask Bit 5" "Masked,Not masked" bitfld.long 0x00 4. " MI4 ,Individual Mask Bit 4" "Masked,Not masked" textline " " bitfld.long 0x00 3. " MI3 ,Individual Mask Bit 3" "Masked,Not masked" bitfld.long 0x00 2. " MI2 ,Individual Mask Bit 2" "Masked,Not masked" bitfld.long 0x00 1. " MI1 ,Individual Mask Bit 1" "Masked,Not masked" bitfld.long 0x00 0. " MI0 ,Individual Mask Bit 0" "Masked,Not masked" endif tree.end width 11. tree.end tree.end tree.open "SPI (Serial Peripheral Interface)" tree "SPI0" base ad:0x4002c000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x4002c000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002c000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002c000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x4002c000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002c000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") rbitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else rbitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" rbitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" rbitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x4002c000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002c000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x4002c000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R")||cpuis("MK60DN512VMC10R") bitfld.long 0x00 20. " PCSIS[4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" newline bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline else bitfld.long 0x00 21. " PCSIS[5] ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " [4] ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " [3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" newline endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x4002c000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002c000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI0 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI0 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002c000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI0 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x4002c000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI0 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI0 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI0 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI0 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI0 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002c000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI0 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI0 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" newline sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif else bitfld.long 0x00 21. " PCS5 ,PCS 5 signal assertion" "Negated,Asserted" bitfld.long 0x00 20. " PCS4 ,PCS 4 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI0 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI0 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI0 POP RX FIFO Register" in endif if ((per.l(ad:0x4002c000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI0 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI0 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI0 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI0 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI0 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI0 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI0 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI0 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI0 Receive FIFO Register 3" in endif width 0x0B tree.end tree "SPI1" base ad:0x4002d000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x4002d000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002d000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" sif cpuis("MK40DN512ZVLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002d000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x4002d000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002d000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" rbitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" rbitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x4002d000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002d000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x4002d000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif !cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 19. " PCSIS[3] ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " [2] ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " [1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x4002d000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x4002d000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" newline endif bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI1 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI1 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" newline endif bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002d000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI1 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x4002d000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI1 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI1 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI1 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI1 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI1 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x4002d000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI1 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI1 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif !cpuis("KK60DN512ZCAB10R") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else sif !cpuis("MK*LH7") bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif else bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI1 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI1 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI1 POP RX FIFO Register" in endif if ((per.l(ad:0x4002d000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI1 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI1 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI1 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI1 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI1 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI1 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI1 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI1 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI1 Receive FIFO Register 3" in endif width 0x0B tree.end tree "SPI2" base ad:0x400ac000 width 19. sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10") if (((per.l(ad:0x400ac000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400ac000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") newline bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." newline bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif else if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") textfld " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline newline sif cpuis("MK40DN512ZVLL10") textfld " " bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" endif newline bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" newline rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif else if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif endif elif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400ac000+0x2C))&0x40000000)==0x40000000) if (((per.l(ad:0x400ac000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400ac000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else rbitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" rbitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" rbitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" rbitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." rbitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline rbitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") rbitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline rbitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") rbitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else rbitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" rbitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline rbitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline rbitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if (((per.l(ad:0x400ac000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400ac000+0x10))&0x2000000)==0x0000000) if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0 clocks,1 clock,2 clocks,?..." bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif else if ((per.l(ad:0x400ac000)&0x4000)==0x4000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" rbitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" rbitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" newline bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" sif !cpuis("MK60DN512ZVLL10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("KK60DN512ZCAB10R")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN512VMC10R")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" endif newline bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif cpuis("KK60DN512ZCAB10R") bitfld.long 0x00 16. " PCSIS[0] ,Peripheral chip select 0 inactive state" "Low,High" else bitfld.long 0x00 17. " PCSIS[1] ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " [0] ,Peripheral chip select 0 inactive state" "Low,High" endif newline bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline bitfld.long 0x00 11. " CLR_TXF ,Clear Tx FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear Rx FIFO" "No effect,Clear" bitfld.long 0x00 0. " HALT ,Start/stop DSPI transfers" "Start,Stop" endif endif endif else if (((per.l(ad:0x400ac000+0x0C))&0x2000000)==0x0000000)&&(((per.l(ad:0x400ac000+0x10))&0x2000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" newline endif bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 8.--9. " SMPL_PT ,Sample point" "0,1,2,?..." bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" else group.long 0x00++0x03 line.long 0x00 "MCR,DSPI2 Module Configuration Register" bitfld.long 0x00 31. " MSTR ,Master/Slave mode select" "Slave,Master" bitfld.long 0x00 30. " CONT_SCKE ,Continuous SCK enable" "Disabled,Enabled" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline else rbitfld.long 0x00 28.--29. " DCONF ,DSPI2 configuration" "SPI,?..." newline endif bitfld.long 0x00 27. " FRZ ,Freeze serial transfers" "Not halted,Halted" bitfld.long 0x00 26. " MTFE ,Modified timing format enable" "Disabled,Enabled" newline sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 25. " PCSSE ,Peripheral chip select strobe enable" "Disabled,Enabled" newline endif bitfld.long 0x00 24. " ROOE ,Receive FIFO overflow overwrite enable" "Disabled,Enabled" newline sif (cpuis("MK70*")||cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")) sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" newline endif bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline else sif cpuis("MKL82*") else sif cpuis("MK??F*")||(cpuis("MK30D????ZVLQ*"))||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15") bitfld.long 0x00 21. " PCSIS5 ,Peripheral chip select 5 inactive state" "Low,High" newline endif bitfld.long 0x00 20. " PCSIS4 ,Peripheral chip select 4 inactive state" "Low,High" newline endif bitfld.long 0x00 19. " PCSIS3 ,Peripheral chip select 3 inactive state" "Low,High" bitfld.long 0x00 18. " PCSIS2 ,Peripheral chip select 2 inactive state" "Low,High" bitfld.long 0x00 17. " PCSIS1 ,Peripheral chip select 1 inactive state" "Low,High" bitfld.long 0x00 16. " PCSIS0 ,Peripheral chip select 0 inactive state" "Low,High" newline endif bitfld.long 0x00 15. " DOZE ,Doze enable" "Disabled,Enabled" bitfld.long 0x00 14. " MDIS ,Module disable" "No,Yes" bitfld.long 0x00 13. " DIS_TXF ,Disable transmit FIFO" "No,Yes" bitfld.long 0x00 12. " DIS_RXF ,Disable receive FIFO" "No,Yes" newline sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10") rbitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" rbitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline else bitfld.long 0x00 11. " CLR_TXF ,Clear TX FIFO" "No effect,Clear" bitfld.long 0x00 10. " CLR_RXF ,Clear RX FIFO" "No effect,Clear" newline endif bitfld.long 0x00 0. " HALT ,Halt DSPI transfers" "Started,Stopped" endif endif newline sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400ac000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif else group.long 0x08++0x03 line.long 0x00 "TCR,DSPI2 Transfer Count Register" hexmask.long.word 0x00 16.--31. 1. " SPI_TCNT ,SPI transfer counter" endif sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x400ac000+0x2C))&0x40000000)==0x40000000) if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) rgroup.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" rgroup.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else rgroup.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif else if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register (In Slave Mode)" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Low,High" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" endif endif else if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) group.long 0xC++0x03 line.long 0x00 "CTAR0,DSPI2 Clock and Transfer Attributes Register 0" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" group.long 0x10++0x03 line.long 0x00 "CTAR1,DSPI2 Clock and Transfer Attributes Register 1" bitfld.long 0x00 31. " DBR ,Double baud rate" "Normal,Doubled" bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" newline bitfld.long 0x00 24. " LSBFE ,LBS First" "MSB,LSB" bitfld.long 0x00 22.--23. " PCSSCK ,PCS to SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 20.--21. " PASC ,After SCK delay prescaler" "/1,/3,/5,/7" bitfld.long 0x00 18.--19. " PDT ,Delay after transfer prescaler" "/1,/3,/5,/7" newline bitfld.long 0x00 16.--17. " PBR ,Baud rate prescaler" "/2,/3,/5,/7" bitfld.long 0x00 12.--15. " CSSCK ,PCS to SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 8.--11. " ASC ,After SCK delay scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" bitfld.long 0x00 4.--7. " DT ,Delay after transfer scaler" "/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768,/65536" newline bitfld.long 0x00 0.--3. " BR ,Baud rate scaler" "/2,/4,/6,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768" else group.long 0x0C++0x03 line.long 0x00 "CTAR0_SLAVE,DSPI2 Clock and Transfer Attributes Register 0" sif cpuis("MKL82*") bitfld.long 0x00 27.--30. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16" newline else bitfld.long 0x00 27.--31. " FMSZ ,Frame size" ",,,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" newline endif bitfld.long 0x00 26. " CPOL ,Clock polarity" "Inactive low,Inactive high" bitfld.long 0x00 25. " CPHA ,Clock phase" "Changed,Captured" sif !cpuis("MK8?FN256V*")&&!cpuis("MK40DN512ZVLL10")&&!cpuis("MKL82*")&&!cpuis("MK40DN512ZVLQ10")&&!cpuis("MK40DN512ZVMD10")&&!cpuis("MK40DX128ZVLQ10")&&!cpuis("MK40DX256ZVLQ10")&&!cpuis("MK40DX256ZVMD10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60DN512VMC10R") sif cpuis("MK60DN512ZCAB10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLQ10R") hgroup.long 0x10++0x03 hide.long 0x00 "CTAR1_SLAVE,DSPI2 Clock and Transfer Attributes Register 1" endif endif endif endif group.long 0x2C++0x03 line.long 0x00 "SR,DSPI2 Status Register" eventfld.long 0x00 31. " TCF ,Transfer complete flag" "Not completed,Completed" sif cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK8?FN256V*") newline eventfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" else newline rbitfld.long 0x00 30. " TXRXS ,TX and RX status" "Disabled,Enabled" endif newline eventfld.long 0x00 28. " EOQF ,End of queue flag" "Not occurred,Occurred" eventfld.long 0x00 27. " TFUF ,Transmit FIFO underflow flag" "No underflow,Underflow" eventfld.long 0x00 25. " TFFF ,Transmit FIFO fill flag" "Full,Not full" eventfld.long 0x00 19. " RFOF ,Receive FIFO overflow flag" "No overflow,Overflow" newline eventfld.long 0x00 17. " RFDF ,Receive FIFO drain flag" "Empty,Not empty" rbitfld.long 0x00 12.--15. " TXCTR ,TX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 8.--11. " TXNXTPTR ,Transmit next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 4.--7. " RXCTR ,RX FIFO counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline rbitfld.long 0x00 0.--3. " POPNXTPTR ,Pop next pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") if (((per.l(ad:0x400ac000+0x2C))&0x40000000)==0x40000000) rgroup.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif else group.long 0x30++0x03 line.long 0x00 "RSER,DSPI2 DMA/Interrupt Request Select and Enable Register" bitfld.long 0x00 31. " TCF_RE ,Transmission complete request enable" "Disabled,Enabled" bitfld.long 0x00 28. " EOQF_RE ,DSPI finished request enable" "Disabled,Enabled" bitfld.long 0x00 27. " TFUF_RE ,Transmit FIFO underflow request enable" "Disabled,Enabled" bitfld.long 0x00 25. " TFFF_RE ,Transmit FIFO fill request enable" "Disabled,Enabled" newline bitfld.long 0x00 24. " TFFF_DIRS ,Transmit FIFO fill DMA / Interrupt request select" "Interrupt,DMA" bitfld.long 0x00 19. " RFOF_RE ,Receive FIFO overflow request enable" "Disabled,Enabled" bitfld.long 0x00 17. " RFDF_RE ,Receive FIFO drain request enable" "Disabled,Enabled" newline bitfld.long 0x00 16. " RFDF_DIRS ,Receive FIFO drain DMA / Interrupt request select" "Interrupt,DMA" endif if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) group.long 0x34++0x3 line.long 0x00 "PUSHR,DSPI2 PUSH TX FIFO Register" bitfld.long 0x00 31. " CONT ,Continuous peripheral chip select enable" "Return to inactive,Keep asserted" bitfld.long 0x00 28.--30. " CTAS ,Clock and transfer attributes select" "CTAR0,CTAR1,?..." bitfld.long 0x00 27. " EOQ ,End Of queue" "Not ended,Ended" bitfld.long 0x00 26. " CTCNT ,Clear transfer counter" "No effect,Clear" newline sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK30DX256VLL7*")&&!cpuis("MK70*") sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") sif !cpuis("MK50DN512ZCLL10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline endif bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK*LL*")||cpuis("MK*MC*")||cpuis("MK*LQ*")||cpuis("MK*MD*")||cpuis("MK*VMJ*")||cpuis("MK*AB*")||cpuis("MK6*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK40DN512ZVLL10")||cpuis("MKL82*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DX256ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK50DN512ZCMD10") sif cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 19. " PCS3 ,PCS 3 signal assertion" "Negated,Asserted" bitfld.long 0x00 18. " PCS2 ,PCS 2 signal assertion" "Negated,Asserted" bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" newline bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline elif cpuis("MK60DN512ZCAB10R") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK40DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK63FN1M0VLQ12R") bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else sif cpuis("MK*VLL10")||cpuis("MK*AB*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif endif endif else endif else bitfld.long 0x00 17. " PCS1 ,PCS 1 signal assertion" "Negated,Asserted" bitfld.long 0x00 16. " PCS0 ,PCS 0 signal assertion" "Negated,Asserted" newline endif hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif (cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK70*")||cpuis("MK40DN512ZVLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10"))||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60FN1M0VLQ15") group.long 0x34++0x03 line.long 0x00 "PUSHR_SLAVE,DSPI2 PUSH TX FIFO Register" sif cpuis("MK?0D*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK30DX256VLL7*")||cpuis("MKL82*")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK60DN512VMC10R") hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" endif endif endif newline width 16. sif cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10") rgroup.long 0x38++0x03 line.long 0x00 "POPR,DSPI2 POP RX FIFO Register" else hgroup.long 0x38++0x03 hide.long 0x00 "POPR,DSPI2 POP RX FIFO Register" in endif if ((per.l(ad:0x400ac000)&0x80000000)==0x80000000) rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" hexmask.long.word 0x00 16.--31. 1. " TXCMD ,Transmit command" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data" else sif cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long 0x3C++0x03 line.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" rgroup.long 0x40++0x03 line.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" rgroup.long 0x44++0x03 line.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" rgroup.long 0x48++0x03 line.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" elif !cpuis("MK8?FN256V*") hgroup.long 0x3C++0x03 hide.long 0x00 "TXFR0,DSPI2 Transmit FIFO Register 0" in hgroup.long 0x40++0x03 hide.long 0x00 "TXFR1,DSPI2 Transmit FIFO Register 1" in hgroup.long 0x44++0x03 hide.long 0x00 "TXFR2,DSPI2 Transmit FIFO Register 2" in hgroup.long 0x48++0x03 hide.long 0x00 "TXFR3,DSPI2 Transmit FIFO Register 3" in endif endif sif cpuis("MK8?FN256V*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*")||cpuis("MK70*")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512VMC10R")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R")||cpuis("MK63FN1M0VLQ12R")||cpuis("MK65FN2M0VMI18R")||cpuis("KK65FN2M0CAC18R")||cpuis("MK66FN2M0VLQ18R") rgroup.long (0x7C+0x0)++0x03 line.long 0x00 "RXFR0,DSPI2 Receive FIFO Register 0" rgroup.long (0x7C+0x4)++0x03 line.long 0x00 "RXFR1,DSPI2 Receive FIFO Register 1" rgroup.long (0x7C+0x8)++0x03 line.long 0x00 "RXFR2,DSPI2 Receive FIFO Register 2" rgroup.long (0x7C+0xC)++0x03 line.long 0x00 "RXFR3,DSPI2 Receive FIFO Register 3" else hgroup.long 0x0++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR0,DSPI2 Receive FIFO Register 0" in hgroup.long 0x4++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR1,DSPI2 Receive FIFO Register 1" in hgroup.long 0x8++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR2,DSPI2 Receive FIFO Register 2" in hgroup.long 0xC++0x03 "DSPI2 Rx FIFO Registers" hide.long 0x00 "RXFR3,DSPI2 Receive FIFO Register 3" in endif width 0x0B tree.end tree.end tree.open "I2C (Inter-Integrated Circuit)" tree "I2C0" base ad:0x40066000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC0 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC0 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC0 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC0 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC0 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC0 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC0 Data I/O Register" in if ((per.b(ad:0x40066000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC0 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC0 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC0 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC0 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC0 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC0 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC0 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC0 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC0 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC0 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC0 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree "I2C1" base ad:0x40067000 width 6. group.byte 0x00++0x03 line.byte 0x00 "A1,IIC1 Address Register 1" hexmask.byte 0x00 1.--7. 0x02 " AD ,Slave address bits [7:1]" line.byte 0x01 "F,IIC1 Frequency Divider Register" bitfld.byte 0x01 6.--7. " MULT ,Multiplier factor" "1,2,4,?..." bitfld.byte 0x01 0.--5. " ICR ,Clock rate (I2C baud rate/SDA hold time/SCL start hold time/SCL stop hold time)" "20/7/6/11,22/7/7/12,24/8/8/13,26/8/9/14,28/9/10/15,30/9/11/16,34/10/13/18,40/10/16/21,28/7/10/15,32/7/12/17,36/9/14/19,40/9/16/21,44/11/18/23,48/11/20/25,56/13/24/29,68/13/30/35,48/9/18/25,56/9/22/29,64/13/26/33,72/13/30/37,80/17/34/41,88/17/38/45,104/21/46/53,128/21/58/65,80/9/38/41,96/9/46/49,112/17/54/57,128/17/62/65,144/25/70/73,160/25/78/81,192/33/94/97,240/33/118/121,160/17/78/81,192/17/94/97,224/33/110/113,256/33/126/129,288/49/142/145,320/49/158/161,384/65/190/193,480/65/238/241,320/33/158/161,384/33/190/193,448/65/222/225,512/65/254/257,576/97/286/289,640/97/318/321,768/129/382/385,960/129/478/481,640/65/318/321,768/65/382/385,896/129/446/449,1024/129/510/513,1152/193/574/577,1280/193/638/641,1536/257/766/769,1920/257/958/961,1280/129/638/641,1536/129/766/769,1792/257/894/897,2048/257/1022/1025,2304/385/1150/1153,2560/385/1278/1281,3072/513/1534/1537,3840/513/1918/1921" line.byte 0x02 "C1,IIC1 Control Register 1" bitfld.byte 0x02 7. " IICEN ,IIC1 enable" "Disabled,Enabled" bitfld.byte 0x02 6. " IICIE ,IIC1 interrupt enable" "Disabled,Enabled" bitfld.byte 0x02 5. " MST ,Master mode select" "Slave,Master" bitfld.byte 0x02 4. " TX ,Transmit mode select" "Receive,Transmit" newline bitfld.byte 0x02 3. " TXAK ,Transmit acknowledge enable" "Disabled,Enabled" bitfld.byte 0x02 2. " RSTA ,Repeat START" "No effect,Start" bitfld.byte 0x02 1. " WUEN ,Wakeup enable" "Disabled,Enabled" bitfld.byte 0x02 0. " DMAEN ,DMA enable" "Disabled,Enabled" line.byte 0x03 "S,IIC1 Status Register" rbitfld.byte 0x03 7. " TCF ,Transfer complete flag" "Not completed,Completed" bitfld.byte 0x03 6. " IAAS ,Addressed as a slave" "Not addressed,Addressed" rbitfld.byte 0x03 5. " BUSY ,Bus busy" "Idle,Busy" eventfld.byte 0x03 4. " ARBL ,Arbitration lost" "Not lost,Lost" newline bitfld.byte 0x03 3. " RAM ,Range address match" "Not matched,Matched" rbitfld.byte 0x03 2. " SRW ,Slave read/write" "Write,Read" eventfld.byte 0x03 1. " IICIF ,Interrupt flag" "No interrupt,Interrupt" rbitfld.byte 0x03 0. " RXAK ,Receive acknowledge" "Acknowledged,Not acknowledged" newline hgroup.byte 0x04++0x00 hide.byte 0x00 "D,IIC1 Data I/O Register" in if ((per.b(ad:0x40067000+0x05)&0x40)==0x40) group.byte 0x05++0x00 line.byte 0x00 "C2,IIC1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control" "Master baud rate,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" bitfld.byte 0x00 0.--2. " AD[10:8] ,Slave address bits [10:8]" "000,001,010,011,100,101,110,111" else group.byte 0x05++0x00 line.byte 0x00 "C2,IIC1 Control Register 2" bitfld.byte 0x00 7. " GCAEN ,Enables general call address" "Disabled,Enabled" bitfld.byte 0x00 6. " ADEXT ,Controls the number of bits used for the slave address" "7-bit,10-bit" bitfld.byte 0x00 5. " HDRS ,Controls the drive capability of the I2C pads" "Normal,High" bitfld.byte 0x00 4. " SBRC ,Slave baud rate control. Enables independent slave mode baud rate at maximum frequency" "Master's,Independent" newline bitfld.byte 0x00 3. " RMEN ,Controls slave address matching for addresses between the values of the A1 and RA registers" "Disabled,Enabled" endif group.byte 0x06++0x05 line.byte 0x00 "FLT,IIC1 Programmable Input Glitch Filter Register" sif cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else sif cpuis("MK21F*")||cpuis("MK22F*")||cpuis("MK02*")||cpuis("MK6*")||cpuis("MK24FN*")||cpuis("MK26FN*")||cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("KK22FN256CAP12R")||cpuis("KK22FN512CBP12R")||cpuis("KK22FN128CAH12R")||cpuis("KK22FN256CAH12R")||cpuis("KK26FN2M0CAC18R")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15")||cpuis("KK65FN2M0CAC18R") bitfld.byte 0x00 7. " SHEN ,Stop hold enable" "Disabled,Enabled" eventfld.byte 0x00 6. " STOPF ,IIC1 bus stop detect flag" "Not detected,Detected" bitfld.byte 0x00 5. " SSIE ,I2C bus stop or start interrupt enable" "Disabled,Enabled" eventfld.byte 0x00 4. " STARTF ,I2C bus start detect flag" "Not started,Started" newline bitfld.byte 0x00 0.--3. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else bitfld.byte 0x00 0.--4. " FLT ,IIC1 programmable filter factor" "No filter,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif line.byte 0x01 "RA,IIC1 Range Address Register" hexmask.byte 0x01 1.--7. 0x02 " RAD ,Range slave address" line.byte 0x02 "SMB,IIC1 SMBus Control and Status Register" bitfld.byte 0x02 7. " FACK ,Fast NACK/ACK enable" "NACK/ACK on following,ACK/NACK by TXAK" bitfld.byte 0x02 6. " ALERTEN ,SMBus alert response address enable" "Disabled,Enabled" bitfld.byte 0x02 5. " SIICAEN ,Second IIC1 address enable" "Disabled,Enabled" bitfld.byte 0x02 4. " TCKSEL ,Timeout counter clock select" "Clock / 64,Clock" newline eventfld.byte 0x02 3. " SLTF ,SCL low timeout flag" "Not occurred,Occurred" rbitfld.byte 0x02 2. " SHTF1 ,SCL high timeout flag 1" "Not occurred,Occurred" eventfld.byte 0x02 1. " SHTF2 ,SCL high timeout flag 2" "Not occurred,Occurred" bitfld.byte 0x02 0. " SHTF2IE ,SHTF2 interrupt enable" "Disabled,Enabled" line.byte 0x03 "A2,IIC1 Address Register 2" hexmask.byte 0x03 1.--7. 0x02 " SAD ,SMBus address" line.byte 0x04 "SLTH,IIC1 SCL Low Timeout High Register" line.byte 0x05 "SLTL,IIC1 SCL Low Timeout Low Register" sif cpuis("MK84FN2M0CAU15R")||cpuis("MK8?FN256V*")||cpuis("MK27FN2M0VMI15")||cpuis("KK28FN2M0CAU15R")||cpuis("MK28FN2M0CAU15R")||cpuis("MK28FN2M0VMI15") group.byte 0x0C++0x00 line.byte 0x00 "S2,IIC1 Status Register 2" eventfld.byte 0x00 1. " ERROR ,Read or write errors with the Tx and Rx buffers" "No error,Error" rbitfld.byte 0x00 0. " EMPTY ,Tx or Rx buffer is empty" "Not empty,Empty" endif width 0x0B tree.end tree.end tree.open "UART (Universal asynchronous receiver/transmitter)" tree "UART 0" base ad:0x4006A000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 0 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART0_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART0_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART0_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART0_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART0_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART0_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006A000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x4006A000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006A000+0x0A)&0x20)==0x00))||(((per.b(ad:0x4006A000+0x02)&0x12)==0x10)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006A000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006A000+0x02)&0x12)==0x12)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006A000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006A000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006A000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006A000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART0_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART0_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART0_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART0_MA1,UART Match Address Register 1" line.byte 0x01 "UART0_MA2,UART Match Address Register 2" line.byte 0x02 "UART0_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART0_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART0_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART0_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART0_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 0 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006A000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART0_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART0_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART0_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006A000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART0_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART0_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006A000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART0_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART0_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. tree "UART 0 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART0_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART0_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART0_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006A000+0x18)&0x02)==0x00) sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006A000+0x18)&0x01)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register" endif else group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T0,UART 7816 Wait Parameter Register" endif else sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006A000+0x18)&0x01)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.byte 0x1B++0x00 line.byte 0x00 "UART0_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006A000+0x18)&0x01)==0x00) group.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" else rgroup.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" endif else group.byte 0x1C++0x01 line.byte 0x00 "UART0_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART0_WF7816,UART 7816 Wait FD Register" endif group.byte 0x1E++0x00 line.byte 0x00 "UART0_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.b(ad:0x4006A000+0x18)&0x02)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART0_TL7816,UART 7816 Transmit Length Register" endif tree.end width 20. sif !cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK53DN512ZCLQ10")&&!cpuis("MK53DN512ZCMD10")&&!cpuis("MK53DX256ZCLQ10")&&!cpuis("MK53DX256ZCMD10")&&!cpuis("MK50DX256ZCLL10")&&!cpuis("MK50DN512ZCLL10")&&!cpuis("MK52DN512ZCLQ10")&&!cpuis("MK52DN512ZCMD10")&&!cpuis("MK51DN256ZCLQ10")&&!cpuis("MK51DN256ZCMD10")&&!cpuis("MK51DN512ZCLQ10")&&!cpuis("MK51DN512ZCMD10")&&!cpuis("MK51DX256ZCMC10")&&!cpuis("MK51DN512ZCMC10")&&!cpuis("MK51DX256ZCLL10")&&!cpuis("MK51DN512ZCLL10")&&!cpuis("MK50DN512ZCLQ10")&&!cpuis("MK50DN512ZCMD10")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10") sif cpuis("MK?0D*")||cpuis("MK5*")||cpuis("MK6*")||cpuis("MK70*") tree "UART 0 CEA709.1-B Registers" sif !cpuis("MK?0DN*AB10") group.byte 0x21++0x8 line.byte 0x00 "UART0_C6,UART CEA709.1-B Control Register 6" bitfld.byte 0x00 7. " EN709 ,Enable CEA709.1-B feature" "Disabled,Enabled" bitfld.byte 0x00 6. " TX709 ,Enable CEA709.1-B transmission" "Disabled,Enabled" textline " " bitfld.byte 0x00 5. " CE ,Collision enable" "Disabled,Enabled" bitfld.byte 0x00 4. " CP ,Collision signal polarity" "Active low,Active high" line.byte 0x01 "UART0_PCTH,UART CEA709.1-B Packet Cycle Time Counter High Register" line.byte 0x02 "UART0_PCTL,UART CEA709.1-B Packet Cycle Time Counter Low Register" sif !cpuis("MK?0D*10")&&!cpuis("MK5*10") line.byte 0x03 "UART0_B1T,UART CEA709.1-B Beta1 Timer Register" else line.byte 0x03 "UART0_IE0,UART CEA709.1-B Interrupt Enable Register 0" bitfld.byte 0x03 2. " RPLOFIE ,Receive packer length overflow interrupt enable" "Disabled,Enabled" bitfld.byte 0x03 1. " CTXDIE ,Collision during transmission of byte sync or later packet Interrupt Enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 0. " CPTXIE ,Collision during preamble transmission Interrupt Enable" "Disabled,Enabled" endif line.byte 0x04 "UART0_SDTH,UART CEA709.1-B Secondary Delay Timer High Register" line.byte 0x05 "UART0_SDTL,UART CEA709.1-B Secondary Delay Timer Low Register" line.byte 0x06 "UART0_PRE,UART CEA709.1-B Preamble Register" line.byte 0x07 "UART0_TPL,UART CEA709.1-B Transmit Packet Length Register" line.byte 0x08 "UART0_IE,UART CEA709.1-B Interrupt Enable Register" sif cpuis("MK?0D*10")||cpuis("MK5*10")||cpuis("MK60DN512VMC10R") bitfld.byte 0x08 7. " PEIE ,Preamble error interrupt enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x08 6. " WBEIE ,Wbase expired interrupt enable" "Disabled,Enabled" bitfld.byte 0x08 5. " ISDIE ,Initial sync detection interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x08 4. " PRXIE ,Packet received interrupt enable" "Disabled,Enabled" bitfld.byte 0x08 3. " PTXIE ,Packet transmitted interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x08 2. " PCTEIE ,Packet cycle timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x08 1. " PSIE ,Preamble start interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x08 0. " TXFIE ,Transmission fail interrupt enable" "Disabled,Enabled" group.byte 0x2A++0x02 line.byte 0x00 "UART0_WB,UART CEA709.1-B WBASE Register" line.byte 0x01 "UART0_S3,UART CEA709.1-B Status Register" eventfld.byte 0x01 7. " PEF ,Preamble error flag" "No error,Error" eventfld.byte 0x01 6. " WBEF ,Wbase expired flag" "Not expired,Expired" textline " " rbitfld.byte 0x01 5. " ISD ,Initial sync detection enable" "Not detected,Detected" eventfld.byte 0x01 4. " PRXF ,Packet received flag" "Not received,Received" textline " " eventfld.byte 0x01 3. " PTXF ,Packet transmitted flag" "Not completed,Completed" eventfld.byte 0x01 2. " PCTEF ,Packet cycle timer expired flag" "Not expired,Expired" textline " " eventfld.byte 0x01 1. " PSF ,Preamble start flag" "Not detected,Detected" eventfld.byte 0x01 0. " TXFF ,Transmission fail flag" "Not failed,Failed" line.byte 0x02 "UART0_S4,UART CEA709.1-B Status Register" sif cpuis("MK?0D*10")||cpuis("MK5*10") eventfld.byte 0x02 5. " LNF ,LON noise flag" "No noise,Noise detected" eventfld.byte 0x02 4. " RPLOF ,Received packet length overflow flag" "No overflow,Overflow" textline " " bitfld.byte 0x02 2.--3. " CDET ,Collision occurring during transmission" "No collision,Preamble,Byte sync or data,Line code violation" eventfld.byte 0x02 1. " TXDF ,Transmission delay flag" "Not delayed,Delayed" textline " " else rbitfld.byte 0x02 4. " INITF ,Initial synchronization fail flag" "Not failed,Failed" bitfld.byte 0x02 2.--3. " CDET ,Collision occurring during transmission" "No collision,Preamble,Byte sync or data,Line code violation" textline " " eventfld.byte 0x02 1. " ILCV ,Improper line code violation" "Proper,Not proper" textline " " endif eventfld.byte 0x02 0. " FE ,Framing error" "No error,Error" rgroup.byte 0x2D++0x01 line.byte 0x00 "UART0_RPL,UART CEA709.1-B Received Packet Length Register" line.byte 0x01 "UART0_RPREL,UART CEA709.1-B Received Preamble Length Register" group.byte 0x2F++0x01 line.byte 0x00 "UART0_CPW,UART CEA709.1-B Collision Pulse Width Register" sif cpuis("MK?0D*10")||cpuis("MK5*10") group.byte 0x30++0x08 line.byte 0x00 "UART0_RIDTH,UART CEA709.1-B Receive Indeterminate Time High Register" line.byte 0x01 "UART0_RIDTL,UART CEA709.1-B Receive Indeterminate Time Low Register" line.byte 0x02 "UART0_TIDTH,UART CEA709.1-B Transmit Indeterminate Time High Register" line.byte 0x03 "UART0_TIDTL,UART CEA709.1-B Transmit Indeterminate Time Low Register" line.byte 0x04 "UART0_RB1TH,UART CEA709.1-B Receive Beta1 Timer High" line.byte 0x05 "UART0_RB1TL,UART CEA709.1-B Receive Beta1 Timer Low" line.byte 0x06 "UART0_TB1TH,UART CEA709.1-B Transmit Beta1 Timer High" line.byte 0x07 "UART0_TB1TL,UART CEA709.1-B Transmit Beta1 Timer Low" line.byte 0x08 "UART0_PROG_REG,UART CEA709.1-B Programmable register" bitfld.byte 0x08 4.--7. " LCV_LEN ,Line code violation length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x08 0.--3. " MIN_DMC1 ,Minimum DMC-1s" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x39++0x00 line.byte 0x00 "UART0_STATE_REG,UART CEA709.1-B State register" bitfld.byte 0x00 3.--5. " TX_STATE ,LON TX State" "0,1,2,3,4,5,6,7" bitfld.byte 0x00 0.--2. " SM_STATE ,LON SM State" "0,1,2,3,4,5,6,7" else group.byte 0x30++0x01 line.byte 0x00 "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time Register" line.byte 0x01 "UART0_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register" endif else group.byte 0x24++0x00 line.byte 0x00 "UART0_B1T,UART CEA709.1-B Beta1 Timer Register" group.byte 0x30++0x01 line.byte 0x00 "UART0_RIDT,UART CEA709.1-B Receive Indeterminate Time Register" line.byte 0x01 "UART0_TIDT,UART CEA709.1-B Transmit Indeterminate Time Register" endif tree.end endif endif elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 0 ISO7816 Registers" width 19. tree.end endif width 0x0B tree.end tree "UART 1" base ad:0x4006B000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 1 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART1_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART1_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART1_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART1_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART1_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART1_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006B000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x4006B000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006B000+0x0A)&0x20)==0x00))||(((per.b(ad:0x4006B000+0x02)&0x12)==0x10)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006B000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006B000+0x02)&0x12)==0x12)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006B000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006B000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006B000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006B000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART1_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART1_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART1_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART1_MA1,UART Match Address Register 1" line.byte 0x01 "UART1_MA2,UART Match Address Register 2" line.byte 0x02 "UART1_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART1_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART1_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART1_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART1_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 1 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006B000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART1_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART1_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART1_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006B000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART1_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART1_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006B000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART1_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART1_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. tree "UART 1 ISO7816 Registers" group.byte 0x18++0x02 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" if ((per.b(ad:0x4006B000+0x18)&0x02)==0x00) sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006B000+0x18)&0x01)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" endif else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" endif else sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006B000+0x18)&0x01)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006B000+0x18)&0x01)==0x00) group.byte 0x1C++0x01 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" else rgroup.byte 0x1C++0x01 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" endif else group.byte 0x1C++0x01 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" endif group.byte 0x1E++0x00 line.byte 0x00 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x00 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((per.b(ad:0x4006B000+0x18)&0x02)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif tree.end elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 1 ISO7816 Registers" width 19. group.byte 0x18++0x02 line.byte 0x00 "UART1_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART1_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART1_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.byte 0x02 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt" textline " " endif eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" endif else if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816,UART 7816 Wait Parameter Register" endif endif else if (((per.b(ad:0x4006B000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART1_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) rgroup.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.b(ad:0x4006B000+0x03)&0x08)==0x08)) if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else rgroup.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif else if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif endif else group.byte 0x1C++0x02 line.byte 0x00 "UART1_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART1_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART1_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART1_TL7816,UART 7816 Transmit Length Register" endif endif textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006B000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) rgroup.byte 0x3A++0x03 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART1_WP7816A_T0,UART 7816 Wait Parameter Register A" hexmask.byte 0x02 0.--7. 1. " WI_H ,Wait time integer high" line.byte 0x03 "UART1_WP7816B_T0,UART 7816 Wait Parameter Register B" hexmask.byte 0x03 0.--7. 1. " WI_L ,Wait time integer low" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in rgroup.byte 0x3C++0x03 line.byte 0x00 "UART1_WP7816A_T1,UART 7816 Wait Parameter Register A" hexmask.byte 0x00 0.--7. 1. " BWI_H ,Block wait time integer high" line.byte 0x01 "UART1_WP7816B_T1,UART 7816 Wait Parameter Register B" hexmask.byte 0x01 0.--7. 1. " BWI_L ,Block wait time integer low" line.byte 0x02 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else if (((per.b(ad:0x4006B000+0x18))&0x2)==0x00) group.byte 0x3A++0x03 line.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART1_WP7816A_T0,UART 7816 Wait Parameter Register A" hexmask.byte 0x02 0.--7. 1. " WI_H ,Wait time integer high" line.byte 0x03 "UART1_WP7816B_T0,UART 7816 Wait Parameter Register B" hexmask.byte 0x03 0.--7. 1. " WI_L ,Wait time integer low" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART1_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART1_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART1_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in group.byte 0x3C++0x03 line.byte 0x00 "UART1_WP7816A_T1,UART 7816 Wait Parameter Register A" hexmask.byte 0x00 0.--7. 1. " BWI_H ,Block wait time integer high" line.byte 0x01 "UART1_WP7816B_T1,UART 7816 Wait Parameter Register B" hexmask.byte 0x01 0.--7. 1. " BWI_L ,Block wait time integer low" line.byte 0x02 "UART1_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART1_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif endif tree.end endif width 0x0B tree.end tree "UART 2" base ad:0x4006C000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 2 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART2_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART2_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART2_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART2_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART2_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART2_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006c000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x4006c000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006c000+0x0A)&0x20)==0x00))||(((per.b(ad:0x4006c000+0x02)&0x12)==0x10)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006c000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006c000+0x02)&0x12)==0x12)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006c000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006c000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006c000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006c000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART2_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART2_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART2_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART2_MA1,UART Match Address Register 1" line.byte 0x01 "UART2_MA2,UART Match Address Register 2" line.byte 0x02 "UART2_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART2_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART2_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART2_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART2_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 2 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006c000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART2_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART2_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART2_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006c000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART2_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART2_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006c000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART2_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART2_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 2 ISO7816 Registers" width 19. tree.end endif width 0x0B tree.end tree "UART 3" base ad:0x4006D000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 3 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART3_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART3_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART3_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART3_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART3_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART3_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x4006d000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x4006d000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006d000+0x0A)&0x20)==0x00))||(((per.b(ad:0x4006d000+0x02)&0x12)==0x10)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006d000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006d000+0x02)&0x12)==0x12)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x00)&&((per.b(ad:0x4006d000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006d000+0x02)&0x10)==0x00)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x4006d000+0x02)&0x10)==0x10)&&((per.b(ad:0x4006d000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART3_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART3_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART3_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART3_MA1,UART Match Address Register 1" line.byte 0x01 "UART3_MA2,UART Match Address Register 2" line.byte 0x02 "UART3_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART3_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART3_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART3_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART3_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 3 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006d000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART3_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART3_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART3_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006d000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART3_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART3_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x4006d000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART3_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART3_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 3 ISO7816 Registers" width 19. group.byte 0x18++0x02 line.byte 0x00 "UART3_C7816,UART 7816 Control Register" bitfld.byte 0x00 4. " ONACK ,Generate NACK on overflow" "Not generated,Generated" bitfld.byte 0x00 3. " ANACK ,Generate NACK on error" "Not generated,Generated" bitfld.byte 0x00 2. " INIT ,Detect initial character" "Not detected,Detected" textline " " bitfld.byte 0x00 1. " TTYPE ,Transfer type" "0 per the ISO-7816,1 per the ISO-7816" bitfld.byte 0x00 0. " ISO_7816E ,ISO-7816 functionality enabled" "Disabled,Enabled" line.byte 0x01 "UART3_IE7816,UART 7816 Interrupt Enable Register" bitfld.byte 0x01 7. " WTE ,Wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 6. " CWTE ,Character wait timer interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 5. " BWTE ,Block wait timer interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x01 4. " INITDE ,Initial character detected interrupt enable" "Disabled,Enabled" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) bitfld.byte 0x01 3. " ADTE ,ATR duration timer interrupt enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x01 2. " GTVE ,Guard timer violated interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 1. " TXTE ,Transmit threshold exceeded interrupt enable" "Disabled,Enabled" bitfld.byte 0x01 0. " RXTE ,Receive threshold exceeded interrupt enable" "Disabled,Enabled" line.byte 0x02 "UART3_IS7816,UART 7816 Interrupt Status Register" eventfld.byte 0x02 7. " WT ,Wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 6. " CWT ,Character wait timer interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 5. " BWT ,Block wait timer interrupt" "No interrupt,Interrupt" textline " " eventfld.byte 0x02 4. " INITD ,Initial character detected interrupt" "No interrupt,Interrupt" textline " " sif (cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) eventfld.byte 0x02 3. " ADT ,ATR duration time interrupt" "No interrupt,Interrupt" textline " " endif eventfld.byte 0x02 2. " GTV ,Guard timer violated interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 1. " TXT ,Transmit threshold exceeded interrupt" "No interrupt,Interrupt" eventfld.byte 0x02 0. " RXT ,Receive threshold exceeded interrupt" "No interrupt,Interrupt" sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*") if (((per.b(ad:0x4006d000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006d000+0x18))&0x02)==0x00) rgroup.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T0,UART 7816 Wait Parameter Register" else rgroup.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.b(ad:0x4006d000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006d000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006d000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" endif else if (((per.b(ad:0x4006d000+0x18))&0x02)==0x00) hgroup.byte 0x1B++0x00 hide.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" in else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816,UART 7816 Wait Parameter Register" endif endif else if (((per.b(ad:0x4006d000+0x18))&0x02)==0x00) group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T0,UART 7816 Wait Parameter Register" else group.byte 0x1B++0x00 line.byte 0x00 "UART3_WP7816T1,UART 7816 Wait Parameter Register" bitfld.byte 0x00 4.--7. " CWI ,Character wait time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " BWI ,Block wait timer integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif sif cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006d000+0x18)&0x01)==0x01)) rgroup.byte 0x1C++0x02 line.byte 0x00 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.byte 0x1C++0x02 line.byte 0x00 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif if (((per.b(ad:0x4006d000+0x03)&0x08)==0x08)) if (((per.b(ad:0x4006d000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else rgroup.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif else if (((per.b(ad:0x4006d000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif endif else group.byte 0x1C++0x02 line.byte 0x00 "UART3_WN7816,UART 7816 Wait N Register" line.byte 0x01 "UART3_WF7816,UART 7816 Wait FD Register" line.byte 0x02 "UART3_ET7816,UART 7816 Error Threshold Register" bitfld.byte 0x02 4.--7. " TXTHRESHOLD ,Transmit NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " RXTHRESHOLD ,Receive NACK threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((per.b(ad:0x4006d000+0x18))&0x2)==0x00) hgroup.byte 0x1F++0x00 hide.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" else group.byte 0x1F++0x00 line.byte 0x00 "UART3_TL7816,UART 7816 Transmit Length Register" endif endif textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") if (((per.b(ad:0x4006d000+0x18)&0x01)==0x01)) if (((per.b(ad:0x4006d000+0x18))&0x2)==0x00) rgroup.byte 0x3A++0x03 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART3_WP7816A_T0,UART 7816 Wait Parameter Register A" hexmask.byte 0x02 0.--7. 1. " WI_H ,Wait time integer high" line.byte 0x03 "UART3_WP7816B_T0,UART 7816 Wait Parameter Register B" hexmask.byte 0x03 0.--7. 1. " WI_L ,Wait time integer low" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in rgroup.byte 0x3C++0x03 line.byte 0x00 "UART3_WP7816A_T1,UART 7816 Wait Parameter Register A" hexmask.byte 0x00 0.--7. 1. " BWI_H ,Block wait time integer high" line.byte 0x01 "UART3_WP7816B_T1,UART 7816 Wait Parameter Register B" hexmask.byte 0x01 0.--7. 1. " BWI_L ,Block wait time integer low" line.byte 0x02 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif else if (((per.b(ad:0x4006d000+0x18))&0x2)==0x00) group.byte 0x3A++0x03 line.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" line.byte 0x01 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" line.byte 0x02 "UART3_WP7816A_T0,UART 7816 Wait Parameter Register A" hexmask.byte 0x02 0.--7. 1. " WI_H ,Wait time integer high" line.byte 0x03 "UART3_WP7816B_T0,UART 7816 Wait Parameter Register B" hexmask.byte 0x03 0.--7. 1. " WI_L ,Wait time integer low" hgroup.byte 0x3E++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" in hgroup.byte 0x3F++0x00 hide.byte 0x00 "UART3_WGP7816_T1,UART 7816 Wait Parameter Register C" in else hgroup.byte 0x3A++0x00 hide.byte 0x00 "UART3_AP7816A_T0,UART 7816 ATR Duration Timer Register A" in hgroup.byte 0x3B++0x00 hide.byte 0x00 "UART3_AP7816B_T0,UART 7816 ATR Duration Timer Register B" in group.byte 0x3C++0x03 line.byte 0x00 "UART3_WP7816A_T1,UART 7816 Wait Parameter Register A" hexmask.byte 0x00 0.--7. 1. " BWI_H ,Block wait time integer high" line.byte 0x01 "UART3_WP7816B_T1,UART 7816 Wait Parameter Register B" hexmask.byte 0x01 0.--7. 1. " BWI_L ,Block wait time integer low" line.byte 0x02 "UART3_WGP7816_T1,UART 7816 Wait and Guard Parameter Register" bitfld.byte 0x02 4.--7. " CWI1 ,Character wait time integer 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x02 0.--3. " BGI ,Block guard time integer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x03 "UART3_WP7816C_T1,UART 7816 Wait Parameter Register C" bitfld.byte 0x03 0.--4. " CWI2 ,Character wait time integer 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif endif endif tree.end endif width 0x0B tree.end tree "UART 4" base ad:0x400EA000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 4 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART4_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART4_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART4_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART4_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART4_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART4_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x400ea000+0x02)&0x10)==0x00)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x400ea000+0x02)&0x10)==0x10)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x00)&&((per.b(ad:0x400ea000+0x0A)&0x20)==0x00))||(((per.b(ad:0x400ea000+0x02)&0x12)==0x10)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x00)&&((per.b(ad:0x400ea000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400ea000+0x02)&0x12)==0x12)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x00)&&((per.b(ad:0x400ea000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400ea000+0x02)&0x10)==0x00)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400ea000+0x02)&0x10)==0x10)&&((per.b(ad:0x400ea000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART4_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART4_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART4_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART4_MA1,UART Match Address Register 1" line.byte 0x01 "UART4_MA2,UART Match Address Register 2" line.byte 0x02 "UART4_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART4_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART4_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART4_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART4_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 4 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400ea000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART4_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART4_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART4_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400ea000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART4_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART4_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART4_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART4_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400ea000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART4_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART4_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART4_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART4_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 4 ISO7816 Registers" width 19. tree.end endif width 0x0B tree.end tree "UART 5" base ad:0x400EB000 width 16. sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree "UART 5 Standard Features Registers" endif group.byte 0x00++0x03 line.byte 0x00 "UART5_BDH,UART Baud Rate Register High" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 7. " LBKDIE ,LIN break detect interrupt or DMA request enable" "Disabled,Enabled" textline " " endif bitfld.byte 0x00 6. " RXEDGIE ,RxD Input active edge interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0.--4. " SBR ,UART baud rate bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.byte 0x01 "UART5_BDL,UART Baud Rate Register Low" line.byte 0x02 "UART5_C1,UART Control Register 1" bitfld.byte 0x02 7. " LOOPS ,Loop mode select" "Not selected,Selected" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") textline " " bitfld.byte 0x02 6. " UARTSWAI ,UART stops in wait mode" "Not stopped,Stopped" endif textline " " bitfld.byte 0x02 5. " RSRC ,Receiver source select" "Internal loop-back mode,Single-wire UART" bitfld.byte 0x02 4. " M ,9-bit or 8-bit mode select" "8 bit mode,9 bit mode" bitfld.byte 0x02 3. " WAKE ,Receiver wakeup method select" "Idle-line,Address-mark" textline " " bitfld.byte 0x02 2. " ILT ,Idle line type select" "After start bit,After stop bit" bitfld.byte 0x02 1. " PE ,Parity enable" "Disabled,Enabled" bitfld.byte 0x02 0. " PT ,Parity type" "Even,Odd" line.byte 0x03 "UART5_C2,UART Control Register 2" bitfld.byte 0x03 7. " TIE ,Transmitter interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 6. " TCIE ,Transmission complete interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 5. " RIE ,Receiver full interrupt or DMA transfer enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 4. " ILIE ,Idle line interrupt or DMA transfer enable" "Disabled,Enabled" bitfld.byte 0x03 3. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.byte 0x03 2. " RE ,Receiver enable" "Disabled,Enabled" textline " " bitfld.byte 0x03 1. " RWU ,Receiver wakeup control" "Normal,Wake-Up" bitfld.byte 0x03 0. " SBK ,Send break" "Normal,Break" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") hgroup.byte 0x04++0x00 hide.byte 0x00 "UART5_S1,UART Status Register 1" in else rgroup.byte 0x04++0x00 line.byte 0x00 "UART5_S1,UART Status Register 1" bitfld.byte 0x00 7. " TDRE ,Transmit data register empty flag" "Not occurred,Occurred" bitfld.byte 0x00 6. " TC ,Transmit complete flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " RDRF ,Receive data register full flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 4. " IDLE ,Idle line flag" "Not occurred,Occurred" bitfld.byte 0x00 3. " OR ,Receiver overrun flag" "Not occurred,Occurred" bitfld.byte 0x00 2. " NF ,Noise flag" "Not occurred,Occurred" textline " " bitfld.byte 0x00 1. " FE ,Framing error flag" "Not occurred,Occurred" bitfld.byte 0x00 0. " PF ,Parity error flag" "Not occurred,Occurred" endif sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if ((per.b(ad:0x400eb000+0x02)&0x10)==0x00)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x00) group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif (((per.b(ad:0x400eb000+0x02)&0x10)==0x10)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x00)&&((per.b(ad:0x400eb000+0x0A)&0x20)==0x00))||(((per.b(ad:0x400eb000+0x02)&0x12)==0x10)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x00)&&((per.b(ad:0x400eb000+0x0A)&0x20)==0x20)) group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "11 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400eb000+0x02)&0x12)==0x12)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x00)&&((per.b(ad:0x400eb000+0x0A)&0x20)==0x20) group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "12 bits,?..." textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "12 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400eb000+0x02)&0x10)==0x00)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",13 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10 bits,11 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" elif ((per.b(ad:0x400eb000+0x02)&0x10)==0x10)&&((per.b(ad:0x400eb000+0x05)&0x04)==0x04) group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" textline " " bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" ",14 bits" textline " " bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "11 bits,12 bits" rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif else group.byte 0x05++0x00 line.byte 0x00 "UART5_S2,UART Status Register 2" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") eventfld.byte 0x00 7. " LBKDIF ,LIN break detect interrupt flag" "Not occurred,Occurred" textline " " endif textline " " eventfld.byte 0x00 6. " RXEDGIF ,RxD pin active edge interrupt flag" "Not occurred,Occurred" bitfld.byte 0x00 5. " MSBF ,Most significant bit first" "LSB first,MSB first" bitfld.byte 0x00 4. " RXINV ,Receive data inversion" "Not inverted,Inverted" textline " " bitfld.byte 0x00 3. " RWUID ,Receive wakeup idle detect" "Not detected,Detected" bitfld.byte 0x00 2. " BRK13 ,Break transmit character length" "10/11/12 bit long,13/14 bit long" textline " " sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") bitfld.byte 0x00 1. " LBKDE ,LIN break detection enable" "10/11/12 bit times,11/12 bit times" textline " " endif rbitfld.byte 0x00 0. " RAF ,Receiver active flag" "Idle,Active" endif group.byte 0x06++0x00 line.byte 0x00 "UART5_C3,UART Control Register 3" rbitfld.byte 0x00 7. " R8 ,Received bit 8" "No RX,RX" bitfld.byte 0x00 6. " T8 ,Transmit bit 8" "No TX,TX" bitfld.byte 0x00 5. " TXDIR ,Transmitter pin data direction in single-wire mode" "Input,Output" textline " " bitfld.byte 0x00 4. " TXINV ,Transmit data inversion" "Not inverted,Inverted" bitfld.byte 0x00 3. " ORIE ,Overrun error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 2. " NEIE ,Noise error interrupt enable" "Disabled,Enabled" textline " " bitfld.byte 0x00 1. " FEIE ,Framing error interrupt enable" "Disabled,Enabled" bitfld.byte 0x00 0. " PEIE ,Parity error interrupt enable" "Disabled,Enabled" hgroup.byte 0x07++0x00 hide.byte 0x00 "UART5_D,UART Data Register" in group.byte 0x08++0x03 line.byte 0x00 "UART5_MA1,UART Match Address Register 1" line.byte 0x01 "UART5_MA2,UART Match Address Register 2" line.byte 0x02 "UART5_C4,UART Control Register 4" bitfld.byte 0x02 7. " MAEN1 ,Match address mode enable 1" "Disabled,Enabled" bitfld.byte 0x02 6. " MAEN2 ,Match address mode enable 2" "Disabled,Enabled" bitfld.byte 0x02 5. " M10 ,10-bit mode select" "Not selected,Selected" textline " " bitfld.byte 0x02 0.--4. " BRFA ,Baud rate fine adjust" "0,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32" line.byte 0x03 "UART5_C5,UART Control Register 5" bitfld.byte 0x03 7. " TDMAS ,Transmitter DMA select" "Interrupt service,DMA transfer" bitfld.byte 0x03 5. " RDMAS ,Receiver full DMA select" "Interrupt service,DMA transfer" textline " " sif cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7") bitfld.byte 0x03 4. " ILDMAS ,Idle line DMA select" "Interrupt service,DMA transfer" endif rgroup.byte 0x0C++0x00 line.byte 0x00 "UART5_ED,UART Extended Data Register" bitfld.byte 0x00 7. " NOISY ,The current received dataword contained in D and C3[R8] was received with noise" "Without noise,With noise" bitfld.byte 0x00 6. " PARITYE ,The current received dataword contained in D and C3[R8] was received with a parity error" "Without parity error,With parity error" group.byte 0x0D++0x01 line.byte 0x00 "UART5_MODEM,UART Modem Register" bitfld.byte 0x00 3. " RXRTSE ,Receiver request-to-send enable (Num of char in RCV data reg FIFO>=RWFIFO(RXWATER)/Num of char in RCV data reg FIFO<=RWFIFO(RXWATER))" "No effect,Deasserted/Asserted" bitfld.byte 0x00 2. " TXRTSPOL ,Transmitter request-to-send polarity" "Active low,Active high" bitfld.byte 0x00 1. " TXRTSE ,Transmitter request-to-send enable (char placed in empty FIFO/after all characters placed to FIFO)" "No effect,Asserted/Deasserted" textline " " bitfld.byte 0x00 0. " TXCTSE ,Transmitter clear-to-send enable" "No effect,Enabled" sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) line.byte 0x01 "UART5_IR,UART Infrared Register" bitfld.byte 0x01 2. " IREN ,Infrared enable" "Disabled,Enabled" bitfld.byte 0x01 0.--1. " TNP ,Transmitter narrow pulse" "3/16,1/16,1/32,1/4" endif sif !(cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")) tree.end tree "UART 5 FIFO Registers" else textline " " endif width 17. sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400eb000+0x03))&0x0C)==0x00) group.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." else rgroup.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif else group.byte 0x10++0x00 line.byte 0x00 "UART5_PFIFO,UART FIFO Parameters" bitfld.byte 0x00 7. " TXFE ,Transmit FIFO enable" "Disabled,Enabled" rbitfld.byte 0x00 4.--6. " TXFIFOSIZE ,Transmit FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." bitfld.byte 0x00 3. " RXFE ,Receive FIFO enable" "Disabled,Enabled" textline " " rbitfld.byte 0x00 0.--2. " RXFIFOSIZE ,Receive FIFO buffer depth" "1 dataword,4 datawords,8 datawords,16 datawords,32 datawords,64 datawords,128 datawords,?..." endif group.byte 0x11++0x01 line.byte 0x00 "UART5_CFIFO,UART FIFO Control Register" bitfld.byte 0x00 7. " TXFLUSH ,Transmit FIFO/Buffer flush" "Not flushed,Flushed" bitfld.byte 0x00 6. " RXFLUSH ,Receive FIFO/Buffer flush" "Not flushed,Flushed" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif sif (cpuis("MK70*")) bitfld.byte 0x00 2. " RXOFE ,Receive FIFO overflow interrupt enable" "Not generated,Generated" textline " " endif bitfld.byte 0x00 1. " TXOFE ,Transmit FIFO overflow interrupt enable" "Not generated,Generated" bitfld.byte 0x00 0. " RXUFE ,Receive FIFO underflow interrupt enable" "Not generated,Generated" line.byte 0x01 "UART5_SFIFO,UART FIFO Status Register" rbitfld.byte 0x01 7. " TXEMPT ,Transmit buffer/FIFO empty" "Not empty,Empty" rbitfld.byte 0x01 6. " RXEMPT ,Receive buffer/FIFO empty" "Not empty,Empty" textline " " sif !cpuis("MK??F*")&&!cpuis("MK30DN512ZVLK10")&&!cpuis("MK30D????ZVLQ*")&&!cpuis("MK60DX256ZVMC10")&&!cpuis("MK60DN512ZVMC10")&&!cpuis("MK60DN256ZVLQ10")&&!cpuis("MK60DN512ZVLQ10")&&!cpuis("MK60DN512ZVMD10")&&!cpuis("MK60DX256ZVLQ10")&&!cpuis("MK60DX256ZVMD10")&&!cpuis("MK60DN512ZVLQ10R")&&!cpuis("MK60DX256ZVLL10")&&!cpuis("MK60FN1M0VLQ15") eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif sif (cpuis("MK70*")) eventfld.byte 0x01 2. " RXOF ,Receiver buffer overflow flag" "No overflow,Overflow" textline " " endif eventfld.byte 0x01 1. " TXOF ,Transmitter buffer overflow flag" "No overflow,Overflow" eventfld.byte 0x01 0. " RXUF ,Receiver buffer underflow flag" "No overflew,Overflow" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400eb000+0x03))&0x08)==0x00) group.byte 0x13++0x00 line.byte 0x00 "UART5_TWFIFO,UART FIFO Transmit Watermark" else rgroup.byte 0x13++0x00 line.byte 0x00 "UART5_TWFIFO,UART FIFO Transmit Watermark" endif else group.byte 0x13++0x00 line.byte 0x00 "UART5_TWFIFO,UART FIFO Transmit Watermark" endif rgroup.byte 0x14++0x00 line.byte 0x00 "UART5_TCFIFO,UART FIFO Transmit Count" sif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.b(ad:0x400eb000+0x03))&0x04)==0x00) group.byte 0x15++0x00 line.byte 0x00 "UART5_RWFIFO,UART FIFO Receive Watermark" else rgroup.byte 0x15++0x00 line.byte 0x00 "UART5_RWFIFO,UART FIFO Receive Watermark" endif else group.byte 0x15++0x00 line.byte 0x00 "UART5_RWFIFO,UART FIFO Receive Watermark" endif rgroup.byte 0x16++0x00 line.byte 0x00 "UART5_RCFIFO,UART FIFO Receive Count" sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") tree.end endif sif !cpuis("MKM33Z128CLL5")&&!cpuis("MKM14Z128ACHH5*")&&!cpuis("MKM14Z64ACHH5")&&!cpuis("MKM33Z128ACLH5*")&&!cpuis("MKM33Z64ACLH5*")&&!cpuis("MKM33Z64ACLL5*")&&!cpuis("MKM33Z128ACLL5")&&!cpuis("MKM34Z128ACLL5*")&&!cpuis("MKM33Z64CLL5*")&&!cpuis("MKM14Z128CHH5*")&&!cpuis("MKM34Z256VLL7*")&&!cpuis("MKM34Z256VLQ7")&&!cpuis("MKM33Z64CLL5")&&!cpuis("MKM34Z128CLL5")&&!cpuis("MKM33Z128CLH5")&&!cpuis("MKM33Z64CLH5")&&!cpuis("MKM14Z128CHH5")&&!cpuis("MKM14Z64CHH5") width 20. elif (cpuis("MKM33Z128CLL5")||cpuis("MKM33Z64CLL5")||cpuis("MKM34Z128CLL5")||cpuis("MKM33Z128CLH5")||cpuis("MKM33Z64CLH5")||cpuis("MKM14Z128CHH5")||cpuis("MKM14Z64CHH5")||cpuis("MKM14Z128ACHH5*")||cpuis("MKM14Z64ACHH5")||cpuis("MKM33Z128ACLH5*")||cpuis("MKM33Z64ACLH5*")||cpuis("MKM33Z64ACLL5*")||cpuis("MKM33Z128ACLL5")||cpuis("MKM34Z128ACLL5*")||cpuis("MKM33Z64CLL5*")||cpuis("MKM14Z128CHH5*")||cpuis("MKM34Z256VLL7*")||cpuis("MKM34Z256VLQ7")) tree "UART 5 ISO7816 Registers" width 19. tree.end endif width 0x0B tree.end tree.end tree "SDHC (Secured digital host controller)" base ad:0x400B1000 width 12. group.long 0x00++0x0F line.long 0x00 "DSADDR,DMA System Address Register" sif !cpuis("K32W0?2S1M*") hexmask.long 0x00 2.--31. 0x04 " DSADDR ,DMA system address" endif line.long 0x04 "BLKATTR,Block Attributes Register" hexmask.long.word 0x04 16.--31. 1. " BLKCNT ,Blocks count for current transfer" hexmask.long.word 0x04 0.--12. 1. " BLKSIZE ,Transfer block size" line.long 0x08 "CMDARG,Command Argument Register" line.long 0x0C "XFERTYP,Transfer Type Register" bitfld.long 0x0C 24.--29. " CMDINX ,Command index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0C 22.--23. " CMDTYP ,Command type" "Normal,Suspend,Resume,Abort" bitfld.long 0x0C 21. " DPSEL ,Data present select" "Not present,Present" newline bitfld.long 0x0C 20. " CICEN ,Command index check enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CCCEN ,Command crc check enable" "Disabled,Enabled" bitfld.long 0x0C 16.--17. " RSPTYP ,Response type select" "No response,Response length 136,Response length 48,Response length 48/check busy" sif !cpuis("K32W0?2S1M*") newline bitfld.long 0x0C 5. " MSBSEL ,Multi/Single block select" "Single,Multi" bitfld.long 0x0C 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x0C 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" newline bitfld.long 0x0C 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x0C 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif rgroup.long 0x10++0x03 line.long 0x00 "CMDRSP0,Command Response 0" rgroup.long 0x14++0x03 line.long 0x00 "CMDRSP1,Command Response 1" rgroup.long 0x18++0x03 line.long 0x00 "CMDRSP2,Command Response 2" rgroup.long 0x1C++0x03 line.long 0x00 "CMDRSP3,Command Response 3" group.long 0x20++0x03 line.long 0x00 "DATPORT,Buffer Data Port Register" rgroup.long 0x24++0x03 line.long 0x00 "PRSSTAT,Present State Register" bitfld.long 0x00 31. " DLSL[7] ,Data 7 line signal level" "Low,High" bitfld.long 0x00 30. " [6] ,Data 6 line signal level" "Low,High" bitfld.long 0x00 29. " [5] ,Data 5 line signal level" "Low,High" newline bitfld.long 0x00 28. " [4] ,Data 4 line signal level" "Low,High" bitfld.long 0x00 27. " [3] ,Data 3 line signal level" "Low,High" bitfld.long 0x00 26. " [2] ,Data 2 line signal level" "Low,High" newline bitfld.long 0x00 25. " [1] ,Data 1 line signal level" "Low,High" bitfld.long 0x00 24. " [0] ,Data 0 line signal level" "Low,High" bitfld.long 0x00 23. " CLSL ,CMD line signal level" "Low,High" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x00 19. " WPSPL ,Write protect switch pin level" "Disabled,Enabled" bitfld.long 0x00 18. " CDPL ,Card detect pin level" "Not detected,Detected" newline endif bitfld.long 0x00 16. " CINS ,Card inserted" "Not inserted,Inserted" bitfld.long 0x00 11. " BREN ,Buffer read enable" "Disabled,Enabled" bitfld.long 0x00 10. " BWEN ,Buffer write enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " RTA ,Read transfer active" "Not active,Active" bitfld.long 0x00 8. " WTA ,Write transfer active" "Not active,Active" bitfld.long 0x00 7. " SDOFF ,SD clock gated off internally" "Active,Gated off" newline bitfld.long 0x00 6. " PEROFF ,Ipg_perclk gated off internally" "Active,Gated off" bitfld.long 0x00 5. " HCKOFF ,Hclk gated off internally" "Active,Gated off" bitfld.long 0x00 4. " IPGOFF ,Lpg_clk gated off internally" "Active,Gated off" newline bitfld.long 0x00 3. " SDSTB ,SD clock stable" "Not stable,Stable" bitfld.long 0x00 2. " DLA ,Data line active" "Not active,Active" bitfld.long 0x00 1. " CDIHB ,Command inhibit (DAT)" "Not generated,Generated" newline bitfld.long 0x00 0. " CIHB ,Command inhibit (CMD)" "Not generated,Generated" group.long 0x28++0x13 line.long 0x00 "PROCTL,Protocol Control Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 29. " BURST_LEN_EN ,BURST length enable for INCR" "Disabled,Enabled" bitfld.long 0x00 28. " BURST_LEN_EN ,BURST length enable for INCR4 / INCR8 / INCR16" "Disabled,Enable" bitfld.long 0x00 27. " BURST_LEN_EN ,BURST length enable for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP" "Disabled,Enabled" endif bitfld.long 0x00 26. " WECRM ,Wakeup event enable on SD card removal" "Disabled,Enabled" bitfld.long 0x00 25. " WECINS ,Wakeup event enable on SD card insertion" "Disabled,Enabled" bitfld.long 0x00 24. " WECINT ,Wakeup event enable on card interrupt" "Disabled,Enabled" newline bitfld.long 0x00 19. " IABG ,Interrupt at block gap" "Disabled,Enabled" bitfld.long 0x00 18. " RWCTL ,Read wait control" "Disabled,Enabled" bitfld.long 0x00 17. " CREQ ,Continue request" "No effect,Restart" newline bitfld.long 0x00 16. " SABGREQ ,Stop at block gap request" "Transfer,Stopped" bitfld.long 0x00 8.--9. " DMAS ,DMA select" "No DMA/Simple DMA,ADMA1,ADMA2,?..." bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "Level,Test" newline bitfld.long 0x00 6. " CDTL ,Card detect test level" "Low,High" bitfld.long 0x00 4.--5. " EMODE ,Endian mode" "Big endian,Half word big endian,Little endian,?..." bitfld.long 0x00 3. " D3CD ,DAT3 as card detection pin" "Not act,Act" newline bitfld.long 0x00 1.--2. " DTW ,Data transfer width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 0. " LCTL ,LED control" "Off,On" line.long 0x04 "SYSCTL,System Control Register" bitfld.long 0x04 27. " INITA ,Initialization active" "Not active,Active" bitfld.long 0x04 26. " RSTD ,Software reset for data line" "No reset,Reset" bitfld.long 0x04 25. " RSTC ,Software reset for cmd line" "No reset,Reset" newline bitfld.long 0x04 24. " RSTA ,Software reset for all" "No reset,Reset" bitfld.long 0x04 16.--19. " DTOCV ,Data timeout counter value" "SDCLK x (2^13),SDCLK x (2^14),SDCLK x (2^15),SDCLK x (2^16),SDCLK x (2^17),SDCLK x (2^18),SDCLK x (2^19),SDCLK x (2^20),SDCLK x (2^21),SDCLK x (2^22),SDCLK x (2^23),SDCLK x (2^24),SDCLK x (2^25),SDCLK x (2^26),SDCLK x (2^27),?..." hexmask.long.byte 0x04 8.--15. 1. " SDCLKFS ,SDCLK frequency select" newline bitfld.long 0x04 4.--7. " DVS ,Divisor" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16" sif !cpuis("K32W0?2S1M*") newline bitfld.long 0x04 3. " SDCLKEN ,SD clock enable" "Disabled,Enabled" bitfld.long 0x04 2. " PEREN ,Peripheral clock enable" "Disabled,Enabled" bitfld.long 0x04 1. " HCKEN ,System clock enable" "Disabled,Enabled" newline bitfld.long 0x04 0. " IPGEN ,IPG clock enable" "Disabled,Enabled" endif line.long 0x08 "IRQSTAT,Interrupt Status Register" eventfld.long 0x08 28. " DMAE ,DMA error" "No error,Error" eventfld.long 0x08 24. " AC12E ,Auto CMD12 error" "No error,Error" eventfld.long 0x08 22. " DEBE ,Data end bit error" "No error,Error" newline eventfld.long 0x08 21. " DCE ,Data CRC error" "No error,Error" eventfld.long 0x08 20. " DTOE ,Data timeout error" "No error,Error" eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error" newline eventfld.long 0x08 18. " CEBE ,Command end bit error" "No error,Error" eventfld.long 0x08 17. " CCE ,Command CRC error" "No error,Error" eventfld.long 0x08 16. " CTOE ,Command timeout error" "No error,Error" newline eventfld.long 0x08 8. " CINT ,Card interrupt" "No interrupt,Interrupt" eventfld.long 0x08 7. " CRM ,Card removal" "Not removed,Removed" eventfld.long 0x08 6. " CINS ,Card insertion" "Not inserted,Inserted" newline eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready" eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready" eventfld.long 0x08 3. " DINT ,DMA interrupt" "No interrupt,Interrupt" newline eventfld.long 0x08 2. " BGE ,Block gap event" "Not stopped,Stopped" eventfld.long 0x08 1. " TC ,Transfer complete" "Not completed,Completed" eventfld.long 0x08 0. " CC ,Command complete" "Not completed,Completed" line.long 0x0C "IRQSTATEN,Interrupt Status Enable Register" bitfld.long 0x0C 28. " DMAESEN ,DMA error status enable" "Disabled,Enabled" bitfld.long 0x0C 24. " AC12ESEN ,Auto CMD12 error status enable" "Disabled,Enabled" bitfld.long 0x0C 22. " DEBESEN ,Data end bit error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 21. " DCESEN ,Data CRC error status enable" "Disabled,Enabled" bitfld.long 0x0C 20. " DTOESEN ,Data timeout error status enable" "Disabled,Enabled" bitfld.long 0x0C 19. " CIESEN ,Command index error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 18. " CEBESEN ,Command end bit error status enable" "Disabled,Enabled" bitfld.long 0x0C 17. " CCESEN ,Command CRC error status enable" "Disabled,Enabled" bitfld.long 0x0C 16. " CTOESEN ,Command timeout error status enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " CINTSEN ,Card interrupt status enable" "Disabled,Enabled" bitfld.long 0x0C 7. " CRMSEN ,Card removal status enable" "Disabled,Enabled" bitfld.long 0x0C 6. " CINSEN ,Card insertion status enable" "Disabled,Enabled" newline bitfld.long 0x0C 5. " BRRSEN ,Buffer read ready status enable" "Disabled,Enabled" bitfld.long 0x0C 4. " BWRSEN ,Buffer write ready status enable" "Disabled,Enabled" bitfld.long 0x0C 3. " DINTSEN ,DMA interrupt status enable" "Disabled,Enabled" newline bitfld.long 0x0C 2. " BGESEN ,Block gap event status enable" "Disabled,Enabled" bitfld.long 0x0C 1. " TCSEN ,Transfer complete status enable" "Disabled,Enabled" bitfld.long 0x0C 0. " CCSEN ,Command complete status enable" "Disabled,Enabled" line.long 0x10 "IRQSIGEN,Interrupt Signal Enable Register" bitfld.long 0x10 28. " DMAEIEN ,DMA error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " AC12EIEN ,Auto CMD12 error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " DEBEIEN ,Data end bit error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 21. " DCEIEN ,Data CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " DTOEIEN ,Data timeout error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 19. " CIEIEN ,Command index error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 18. " CEBEIEN ,Command end bit error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 17. " CCEIEN ,Command CRC error interrupt enable" "Disabled,Enabled" bitfld.long 0x10 16. " CTOEIEN ,Command timeout error interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 8. " CINTIEN ,Card interrupt enable" "Disabled,Enabled" bitfld.long 0x10 7. " CRMIEN ,Card removal interrupt enable" "Disabled,Enabled" bitfld.long 0x10 6. " CINSIEN ,Card insertion interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 5. " BRRIEN ,Buffer read ready interrupt enable" "Disabled,Enabled" bitfld.long 0x10 4. " BWRIEN ,Buffer write ready interrupt enable" "Disabled,Enabled" bitfld.long 0x10 3. " DINTIEN ,DMA interrupt enable" "Disabled,Enabled" newline bitfld.long 0x10 2. " BGEIEN ,Block gap event interrupt enable" "Disabled,Enabled" bitfld.long 0x10 1. " TCIEN ,Transfer complete interrupt enable" "Disabled,Enabled" bitfld.long 0x10 0. " CCIEN ,Command complete interrupt enable" "Disabled,Enabled" if ((per.l(ad:0x400B1000+0x30)&0x1000000)==0x00) hgroup.long 0x3C++0x03 hide.long 0x00 "AC12ERR,Auto CMD12 Error Status Register" else rgroup.long 0x3C++0x03 line.long 0x00 "AC12ERR,Auto CMD12 Error Status Register" bitfld.long 0x00 7. " CNIBAC12E ,Command not issued by auto CMD12 error" "No error,Not issued" bitfld.long 0x00 4. " AC12IE ,Auto CMD12 index error" "No error,Error" bitfld.long 0x00 3. " AC12CE ,Auto CMD12 CRC error" "No error,Error" newline bitfld.long 0x00 2. " AC12EBE ,Auto CMD12 end bit error" "No error,Error" bitfld.long 0x00 1. " AC12TOE ,Auto CMD12 timeout error" "No error,Error" bitfld.long 0x00 0. " AC12NE ,Auto CMD12 not executed" "Executed,Not executed" endif rgroup.long 0x40++0x03 line.long 0x00 "HTCAPBLT,Host Controller Capabilities" sif cpuis("MK?0F*")||cpuis("MK?0D*10")||cpuis("MK20DN512*AB10R")||cpuis("MK5*10")||cpuis("MK6*")||cpuis("MK7*")||cpuis("MK20DX256VLQ10R")||cpuis("MK20DX256VLK10R")||cpuis("K32W0?2S1M*")||cpuis("MK10DN512ZVLL10")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DX256VLL7*")||cpuis("MK40DN512ZVLL10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("KK20DN512ZCAB10R")||cpuis("MK20DN512ZVLL10")||cpuis("MK20DX256ZVLL10")||cpuis("MK20DN512ZVLQ10")||cpuis("MK20DN512ZVLQ10R")||cpuis("MK20DN512ZVMD10")||cpuis("MK20DX128ZVLQ10")||cpuis("MK20DX256ZVLQ10")||cpuis("MK20DX256ZVLQ10R")||cpuis("MK20DX256ZVMD10")||cpuis("MK20DN512ZVLK10")||cpuis("MK20DX256ZVLK10")||cpuis("MK20DN512ZVMC10")||cpuis("MK20DN512ZVMC10R")||cpuis("MK20DN512VLK10R")||cpuis("KK20DN512ZCAB10R")||cpuis("KK60FN1M0VLQ15")||cpuis("KK60DN512ZCAB10R") sif !cpuis("MK8?FN256V*")&&!cpuis("MK63FN1M0VLQ12R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("KK65FN2M0CAC18R")&&!cpuis("MK66FN2M0VLQ18R") bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported" bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported" newline endif endif bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported" bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported" bitfld.long 0x00 22. " DMAS ,DMA support" "Not supported,Supported" newline bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported" bitfld.long 0x00 20. " ADMAS ,ADMA support" "Not supported,Supported" bitfld.long 0x00 16.--18. " MBL ,Max block length" "512 bytes,1024 bytes,2048 bytes,4096 bytes,?..." group.long 0x44++0x03 line.long 0x00 "WML,Watermark Level Register" sif cpuis("MK63FN1M0VLQ12R")||cpuis("K32W0?2S1M*") bitfld.long 0x00 24.--28. " WRBRSTLEN ,Write Burst Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." endif newline hexmask.long.byte 0x00 16.--23. 1. " WRWML ,Write watermark level" sif cpuis("MK63FN1M0VLQ12R")||cpuis("K32W0?2S1M*") bitfld.long 0x00 8.--12. " RDBRSTLEN ,Read burst length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." endif newline hexmask.long.byte 0x00 0.--7. 1. " RDWML ,Read watermark level" sif cpuis("K32W0?2S1M*") group.long 0x48++0x03 line.long 0x00 "MIX_CTRL,Mixer Control Register" bitfld.long 0x00 7. " AC23EN ,Auto CMD23 enable" "Disabled,Enabled" bitfld.long 0x00 6. " NIBBLE_POS ,Nibble position indication" "Low,High" bitfld.long 0x00 5. " MSBSEL ,Multi/Single block select" "Single,Multi" newline bitfld.long 0x00 4. " DTDSEL ,Data transfer direction select" "Write,Read" bitfld.long 0x00 3. " DDR_EN ,Dual data rate mode selection enable" "Disabled,Enabled" bitfld.long 0x00 2. " AC12EN ,Auto CMD12 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " BCEN ,Block count enable" "Disabled,Enabled" bitfld.long 0x00 0. " DMAEN ,DMA enable" "Disabled,Enabled" endif wgroup.long 0x50++0x03 line.long 0x00 "FEVT,Force Event Register" bitfld.long 0x00 31. " CINT ,Force event card interrupt" "No effect,Force" bitfld.long 0x00 28. " DMAE ,Force event DMA error" "No effect,Force" bitfld.long 0x00 24. " AC12E ,Force event auto command 12 error" "No effect,Force" newline bitfld.long 0x00 22. " DEBE ,Force event data end bit error" "No effect,Force" bitfld.long 0x00 21. " DCE ,Force event data crc error" "No effect,Force" bitfld.long 0x00 20. " DTOE ,Force event data time out error" "No effect,Force" newline bitfld.long 0x00 19. " CIE ,Force event command index error" "No effect,Force" bitfld.long 0x00 18. " CEBE ,Force event command end bit error" "No effect,Force" bitfld.long 0x00 17. " CCE ,Force event command crc error" "No effect,Force" newline bitfld.long 0x00 16. " CTOE ,Force event command time out error" "No effect,Force" bitfld.long 0x00 7. " CNIBAC12E ,Force event command not executed by auto command 12 error" "No effect,Force" bitfld.long 0x00 4. " AC12IE ,Force event auto command 12 index error" "No effect,Force" newline bitfld.long 0x00 3. " AC12EBE ,Force event auto command 12 end bit error" "No effect,Force" bitfld.long 0x00 2. " AC12CE ,Force event auto command 12 crc error" "No effect,Force" bitfld.long 0x00 1. " AC12TOE ,Force event auto command 12 time out error" "No effect,Force" newline bitfld.long 0x00 0. " AC12NE ,Force event auto command 12 not executed" "No effect,Force" rgroup.long 0x54++0x03 line.long 0x00 "ADMAES,ADMA Error Status Register" bitfld.long 0x00 3. " ADMADCE ,ADMA descriptor error" "No error,Error" bitfld.long 0x00 2. " ADMALME ,ADMA length mismatch error" "No error,Error" bitfld.long 0x00 0.--1. " ADMAES ,ADMA error state" "ST_STOP,ST_FDS,ST_CADR,ST_TFR" group.long 0x58++0x03 line.long 0x00 "ADSADDR,ADMA System Address Register" hexmask.long 0x00 2.--31. 0x04 " ADSADDR ,ADMA system address" group.long 0xC0++0x07 line.long 0x00 "VENDOR,Vendor Specific Register" sif cpuis("K32W0?2S1M*") bitfld.long 0x00 31. " CMD_BYTE_EN ,Byte access enable" "Disabled,Enabled" bitfld.long 0x00 15. " CRC_CHK_DIS ,CRC check disable" "Enabled,Disabled" bitfld.long 0x00 8. " FRC_SDCLK_ON ,Force CLK output active" "Not forced,Forced" newline bitfld.long 0x00 3. " AC12_WR_CHKBUSY_EN ,Check busy enable after auto CMD12 for write data packet" "Not checked,Checked" bitfld.long 0x00 2. " CONFLICT_CHK_EN ,Conflict check enable" "Disabled,Enabled" bitfld.long 0x00 1. " VSELECT ,Voltage selection" "3.0V,1.8V" newline else hexmask.long.byte 0x00 16.--23. 1. " INTSTVAL ,Internal state value" bitfld.long 0x00 1. " EXBLKNU ,Exact block number block read enable" "Disabled,Enabled" sif !cpuis("MK65*")&&!cpuis("MK66*")&&!cpuis("MK26FN*")&&!cpuis("MK84FN2M0CAU15R")&&!cpuis("MK8?FN256V*")&&!cpuis("KK28FN2M0CAU15R")&&!cpuis("MK28FN2M0CAU15R")&&!cpuis("MK28FN2M0VMI15")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("MK27FN2M0VMI15")&&!cpuis("MK66FN2M0VLQ18R")&&!cpuis("KK65FN2M0CAC18R") newline bitfld.long 0x00 0. " EXTDMAEN ,External DMA request enable" "Disabled,Enabled" endif endif line.long 0x04 "MMCBOOT,MMC Boot Register" hexmask.long.word 0x04 16.--31. 1. " BOOTBLKCNT ,Boot block counter" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x04 8. " DISABLE_TIME_OUT ,Disable time out" "Enabled,Disabled" newline endif bitfld.long 0x04 7. " AUTOSABGEN ,Auto stop at boost gap enable" "Disabled,Enabled" bitfld.long 0x04 6. " BOOTEN ,Fast boot mode enable" "Disabled,Enabled" bitfld.long 0x04 5. " BOOTMODE ,Boot ACK mode select" "Normal,Alternative" newline bitfld.long 0x04 4. " BOOTACK ,Boot ACK mode select" "No ACK,ACK" newline sif cpuis("K32W0?2S1M*") bitfld.long 0x04 0.--3. " DTOCVACK ,Boot ACK time out counter value" "2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,,,,,,,2^28,2^29" else bitfld.long 0x04 0.--3. " DTOCVACK ,Boot ACK time out counter value" "2^8,2^9,2^10,2^11,2^12,2^13,2^14,2^15,2^16,2^17,2^18,2^19,2^20,2^21,2^22,?..." endif sif cpuis("K32W0?2S1M*") group.long 0xC8++0x03 line.long 0x00 "VEND_SPEC2,Vendor Specific 2 Register" bitfld.long 0x00 14. " AHB_RST ,AHB BUS reset" "No reset,Reset" bitfld.long 0x00 12. " ACMD23_ARGU2_EN ,Argument2 register enable for ACMD23" "Disabled,Enabled" bitfld.long 0x00 3. " CARD_INT_D3_TEST ,Card interrupt detection test" "Check when DATA3 is high,Ignore DATA3 status" else rgroup.long 0xFC++0x03 line.long 0x00 "HOSTVER,Host Controller Version" hexmask.long.byte 0x00 8.--15. 1. " VVN ,Vendor version number" hexmask.long.byte 0x00 0.--7. 1. " SVN ,Specification version number" endif width 0x0B tree.end tree.open "I2S/SAI" tree "I2S0/SAI0" base ad:0x4002F000 width 14. group.long 0x00++0x17 line.long 0x00 "I2S0_TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S0_TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" line.long 0x08 "I2S0_TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swap" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External clock" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0c "I2S0_TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x0c 17. " TCE1 ,Transmit channel 1 enable" "Disabled,Enabled" bitfld.long 0x0c 16. " TCE0 ,Transmit channel 0 enable" "Disabled,Enabled" bitfld.long 0x0c 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x10 "I2S0_TCR4,SAI Transmit Configuration 4 Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 28. " FCONT ,FIFO Continue on Error" "Continued from the start of the next frame,Continued from the same word" bitfld.long 0x10 26.--27. " FCOMB ,FIFO Combine Mode" "Disabled,Enabled reading,Enabled writing,Enabled reading and writing" bitfld.long 0x10 24.--25. " FCOMB ,FIFO Combine Mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" textline " " bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 2. " ONDEM ,On Demand Mode" "continuously,when the FIFO warning flag is clear" textline " " endif bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "I2S0_TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " wgroup.long 0x20++0x7 line.long 0x00 "I2S0_TDR0,SAI Transmit Data Register 0" line.long 0x04 "I2S0_TDR1,SAI Transmit Data Register 1" rgroup.long 0x40++0x7 line.long 0x00 "I2S0_TFR0,SAI Transmit FIFO Register 0" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 31. " WCP ,Write Channel Pointer" "No effect,Enabled FIFO combine for FIFO writes" textline " " endif hexmask.long.byte 0x00 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 0x01 " RFP ,Read FIFO pointer" line.long 0x04 "I2S0_TFR1,SAI Transmit FIFO Register 1" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x04 31. " WCP ,Write Channel Pointer" "No effect,Enabled FIFO combine for FIFO writes" textline " " endif hexmask.long.byte 0x04 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 0x01 " RFP ,Read FIFO pointer" textline " " group.long 0x60++0x3 line.long 0x00 "I2S0_TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Mask bit[31]" "Not masked,Masked" bitfld.long 0x00 30. " TWM[30] ,Mask bit[30]" "Not masked,Masked" bitfld.long 0x00 29. " TWM[29] ,Mask bit[29]" "Not masked,Masked" bitfld.long 0x00 28. " TWM[28] ,Mask bit[28]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " TWM[27] ,Mask bit[27]" "Not masked,Masked" bitfld.long 0x00 26. " TWM[26] ,Mask bit[26]" "Not masked,Masked" bitfld.long 0x00 25. " TWM[25] ,Mask bit[25]" "Not masked,Masked" bitfld.long 0x00 24. " TWM[24] ,Mask bit[24]" "Not masked,Masked" textline " " bitfld.long 0x00 23. " TWM[23] ,Mask bit[23]" "Not masked,Masked" bitfld.long 0x00 22. " TWM[22] ,Mask bit[22]" "Not masked,Masked" bitfld.long 0x00 21. " TWM[21] ,Mask bit[21]" "Not masked,Masked" bitfld.long 0x00 20. " TWM[20] ,Mask bit[20]" "Not masked,Masked" textline " " bitfld.long 0x00 19. " TWM[19] ,Mask bit[19]" "Not masked,Masked" bitfld.long 0x00 18. " TWM[18] ,Mask bit[18]" "Not masked,Masked" bitfld.long 0x00 17. " TWM[17] ,Mask bit[17]" "Not masked,Masked" bitfld.long 0x00 16. " TWM[16] ,Mask bit[16]" "Not masked,Masked" textline " " bitfld.long 0x00 15. " TWM[15] ,Mask bit[15]" "Not masked,Masked" bitfld.long 0x00 14. " TWM[14] ,Mask bit[14]" "Not masked,Masked" bitfld.long 0x00 13. " TWM[13] ,Mask bit[13]" "Not masked,Masked" bitfld.long 0x00 12. " TWM[12] ,Mask bit[12]" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TWM[11] ,Mask bit[11]" "Not masked,Masked" bitfld.long 0x00 10. " TWM[10] ,Mask bit[10]" "Not masked,Masked" bitfld.long 0x00 9. " TWM[9] ,Mask bit[9]" "Not masked,Masked" bitfld.long 0x00 8. " TWM[8] ,Mask bit[8]" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TWM[7] ,Mask bit[7]" "Not masked,Masked" bitfld.long 0x00 6. " TWM[6] ,Mask bit[6]" "Not masked,Masked" bitfld.long 0x00 5. " TWM[5] ,Mask bit[5]" "Not masked,Masked" bitfld.long 0x00 4. " TWM[4] ,Mask bit[4]" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TWM[3] ,Mask bit[3]" "Not masked,Masked" bitfld.long 0x00 2. " TWM[2] ,Mask bit[2]" "Not masked,Masked" bitfld.long 0x00 1. " TWM[1] ,Mask bit[1]" "Not masked,Masked" bitfld.long 0x00 0. " TWM[0] ,Mask bit[0]" "Not masked,Masked" group.long 0x80++0x17 line.long 0x00 "I2S0_RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S0_RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" line.long 0x08 "I2S0_RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swap" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External clock" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0c "I2S0_RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x0c 17. " RCE1 ,Receive channel 1 enable" "Disabled,Enabled" bitfld.long 0x0c 16. " RCE0 ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x0c 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x10 "I2S0_RCR4,SAI Receive Configuration 4 Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 28. " FCONT ,FIFO Continue on Error" "Continued from the start of the next frame,Continued from the same word" textline " " bitfld.long 0x10 26.--27. " FCOMB ,FIFO Combine Mode" "Disabled,Enabled writing,Enabled reading,Enabled reading and writing" bitfld.long 0x10 24.--25. " FCOMB ,FIFO Combine Mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 2. " ONDEM ,On Demand Mode" "continuously,when the FIFO warning flag is clear" textline " " endif bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "I2S0_RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hgroup.long 0xa0++0x3 hide.long 0x00 "I2S0_RDR0,SAI Receive Data 0 Register" in hgroup.long 0xa4++0x3 hide.long 0x00 "I2S0_RDR1,SAI Receive Data 1 Register" in rgroup.long 0xc0++0x7 line.long 0x00 "I2S0_RFR0,SAI Receive FIFO 0 Register" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 15. " RCP ,Receive Channel Pointer" "No effect,Enabled FIFO combine for FIFO reads" textline " " endif bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "I2S0_RFR1,SAI Receive FIFO 1 Register" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x04 15. " RCP ,Receive Channel Pointer" "No effect,Enabled FIFO combine for FIFO reads" textline " " endif bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long 0xe0++0x3 line.long 0x00 "I2S0_RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive Mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive Mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " RWM27 ,Receive Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive Mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive Mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " RWM23 ,Receive Mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RWM19 ,Receive Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive Mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive Mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " RWM15 ,Receive Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive Mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive Mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RWM11 ,Receive Mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RWM7 ,Receive Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive Mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive Mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive Mask bit 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RWM3 ,Receive Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive Mask bit 2" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive Mask bit 0" "Not masked,Masked" textline " " group.long 0x100++0x7 line.long 0x00 "I2S0_MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider Update Flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK Output Enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK Input Clock Select" "MCLK divider input clock 0,MCLK divider input clock 1,MCLK divider input clock 2,MCLK divider input clock 3" line.long 0x04 "I2S0_MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree "I2S1/SAI1" base ad:0x400AF000 width 14. group.long 0x00++0x17 line.long 0x00 "I2S1_TCSR,SAI Transmit Control Register" bitfld.long 0x00 31. " TE ,Transmitter enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO empty warning flag" "Not empty,Empty" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S1_TCR1,SAI Transmit Configuration 1 Register" bitfld.long 0x04 0.--2. " TFW ,Transmit FIFO watermark" "0,1,2,3,4,5,6,7" line.long 0x08 "I2S1_TCR2,SAI Transmit Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Receiver,SAI transmitter,SAI receiver" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swap" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External clock" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0c "I2S1_TCR3,SAI Transmit Configuration 3 Register" bitfld.long 0x0c 17. " TCE1 ,Transmit channel 1 enable" "Disabled,Enabled" bitfld.long 0x0c 16. " TCE0 ,Transmit channel 0 enable" "Disabled,Enabled" bitfld.long 0x0c 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x10 "I2S1_TCR4,SAI Transmit Configuration 4 Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 28. " FCONT ,FIFO Continue on Error" "Continued from the start of the next frame,Continued from the same word" bitfld.long 0x10 26.--27. " FCOMB ,FIFO Combine Mode" "Disabled,Enabled reading,Enabled writing,Enabled reading and writing" bitfld.long 0x10 24.--25. " FCOMB ,FIFO Combine Mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is transmitted first" "LSB,MSB" textline " " bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 2. " ONDEM ,On Demand Mode" "continuously,when the FIFO warning flag is clear" textline " " endif bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "I2S1_TCR5,SAI Transmit Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " wgroup.long 0x20++0x7 line.long 0x00 "I2S1_TDR0,SAI Transmit Data Register 0" line.long 0x04 "I2S1_TDR1,SAI Transmit Data Register 1" rgroup.long 0x40++0x7 line.long 0x00 "I2S1_TFR0,SAI Transmit FIFO Register 0" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 31. " WCP ,Write Channel Pointer" "No effect,Enabled FIFO combine for FIFO writes" textline " " endif hexmask.long.byte 0x00 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x00 0.--3. 0x01 " RFP ,Read FIFO pointer" line.long 0x04 "I2S1_TFR1,SAI Transmit FIFO Register 1" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x04 31. " WCP ,Write Channel Pointer" "No effect,Enabled FIFO combine for FIFO writes" textline " " endif hexmask.long.byte 0x04 16.--19. 0x01 " WFP ,Write FIFO pointer" hexmask.long.byte 0x04 0.--3. 0x01 " RFP ,Read FIFO pointer" textline " " group.long 0x60++0x3 line.long 0x00 "I2S1_TMR,SAI Transmit Mask Register" bitfld.long 0x00 31. " TWM[31] ,Mask bit[31]" "Not masked,Masked" bitfld.long 0x00 30. " TWM[30] ,Mask bit[30]" "Not masked,Masked" bitfld.long 0x00 29. " TWM[29] ,Mask bit[29]" "Not masked,Masked" bitfld.long 0x00 28. " TWM[28] ,Mask bit[28]" "Not masked,Masked" textline " " bitfld.long 0x00 27. " TWM[27] ,Mask bit[27]" "Not masked,Masked" bitfld.long 0x00 26. " TWM[26] ,Mask bit[26]" "Not masked,Masked" bitfld.long 0x00 25. " TWM[25] ,Mask bit[25]" "Not masked,Masked" bitfld.long 0x00 24. " TWM[24] ,Mask bit[24]" "Not masked,Masked" textline " " bitfld.long 0x00 23. " TWM[23] ,Mask bit[23]" "Not masked,Masked" bitfld.long 0x00 22. " TWM[22] ,Mask bit[22]" "Not masked,Masked" bitfld.long 0x00 21. " TWM[21] ,Mask bit[21]" "Not masked,Masked" bitfld.long 0x00 20. " TWM[20] ,Mask bit[20]" "Not masked,Masked" textline " " bitfld.long 0x00 19. " TWM[19] ,Mask bit[19]" "Not masked,Masked" bitfld.long 0x00 18. " TWM[18] ,Mask bit[18]" "Not masked,Masked" bitfld.long 0x00 17. " TWM[17] ,Mask bit[17]" "Not masked,Masked" bitfld.long 0x00 16. " TWM[16] ,Mask bit[16]" "Not masked,Masked" textline " " bitfld.long 0x00 15. " TWM[15] ,Mask bit[15]" "Not masked,Masked" bitfld.long 0x00 14. " TWM[14] ,Mask bit[14]" "Not masked,Masked" bitfld.long 0x00 13. " TWM[13] ,Mask bit[13]" "Not masked,Masked" bitfld.long 0x00 12. " TWM[12] ,Mask bit[12]" "Not masked,Masked" textline " " bitfld.long 0x00 11. " TWM[11] ,Mask bit[11]" "Not masked,Masked" bitfld.long 0x00 10. " TWM[10] ,Mask bit[10]" "Not masked,Masked" bitfld.long 0x00 9. " TWM[9] ,Mask bit[9]" "Not masked,Masked" bitfld.long 0x00 8. " TWM[8] ,Mask bit[8]" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TWM[7] ,Mask bit[7]" "Not masked,Masked" bitfld.long 0x00 6. " TWM[6] ,Mask bit[6]" "Not masked,Masked" bitfld.long 0x00 5. " TWM[5] ,Mask bit[5]" "Not masked,Masked" bitfld.long 0x00 4. " TWM[4] ,Mask bit[4]" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TWM[3] ,Mask bit[3]" "Not masked,Masked" bitfld.long 0x00 2. " TWM[2] ,Mask bit[2]" "Not masked,Masked" bitfld.long 0x00 1. " TWM[1] ,Mask bit[1]" "Not masked,Masked" bitfld.long 0x00 0. " TWM[0] ,Mask bit[0]" "Not masked,Masked" group.long 0x80++0x17 line.long 0x00 "I2S1_RCSR,SAI Receive Control Register" bitfld.long 0x00 31. " RE ,Receiver enable" "Disabled,Enabled" bitfld.long 0x00 30. " STOPE ,Stop enable" "Disabled,Enabled" bitfld.long 0x00 29. " DBGE ,Debug enable" "Disabled,Enabled" bitfld.long 0x00 28. " BCE ,Bit Clock Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " FR ,FIFO reset" "No reset,Reset" bitfld.long 0x00 24. " SR ,Software reset" "No reset,Reset" eventfld.long 0x00 20. " WSF ,Word start flag" "Not started,Started" eventfld.long 0x00 19. " SEF ,Sync error flag" "No error,Error" textline " " eventfld.long 0x00 18. " FEF ,FIFO error flag" "No error,Error" rbitfld.long 0x00 17. " FWF ,FIFO warning flag" "Not full,Full" rbitfld.long 0x00 16. " FRF ,FIFO watermark reach" "Not reached,Reached" bitfld.long 0x00 12. " WSIE ,Word start interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SEIE ,Sync error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 10. " FEIE ,FIFO error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " FWIE ,FIFO warning interrupt enable" "Disabled,Enabled" bitfld.long 0x00 8. " FRIE ,FIFO request interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " FWDE ,FIFO warning DMA enable" "Disabled,Enabled" bitfld.long 0x00 0. " FRDE ,FIFO request DMA enable" "Disabled,Enabled" line.long 0x04 "I2S1_RCR1,SAI Receive Configuration 1 Register" bitfld.long 0x04 0.--2. " RFW ,Receive FIFO watermark" "0,1,2,3,4,5,6,7" line.long 0x08 "I2S1_RCR2,SAI Receive Configuration 2 Register" bitfld.long 0x08 30.--31. " SYNC ,Synchronous Mode" "Asynchronous,Transmitter,SAI receiver,SAI transmitter" bitfld.long 0x08 29. " BCS ,Bit Clock Swap" "Normal,Swap" bitfld.long 0x08 28. " BCI ,Bit Clock Input" "No effect,External clock" bitfld.long 0x08 26.--27. " MSEL ,MCLK Select" "Bus clock,Master clock 1,Master clock 2,Master clock 3" textline " " bitfld.long 0x08 25. " BCP ,Bit clock polarity" "Active high,Active low" bitfld.long 0x08 24. " BCD ,Bit clock direction" "External,Internal" hexmask.long.byte 0x08 0.--7. 1. " DIV ,Bit clock divide" line.long 0x0c "I2S1_RCR3,SAI Receive Configuration 3 Register" bitfld.long 0x0c 17. " RCE1 ,Receive channel 1 enable" "Disabled,Enabled" bitfld.long 0x0c 16. " RCE0 ,Receive channel 0 enable" "Disabled,Enabled" bitfld.long 0x0c 0.--4. " WDFL ,Word flag configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " line.long 0x10 "I2S1_RCR4,SAI Receive Configuration 4 Register" sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 28. " FCONT ,FIFO Continue on Error" "Continued from the start of the next frame,Continued from the same word" textline " " bitfld.long 0x10 26.--27. " FCOMB ,FIFO Combine Mode" "Disabled,Enabled writing,Enabled reading,Enabled reading and writing" bitfld.long 0x10 24.--25. " FCOMB ,FIFO Combine Mode" "Disabled,,8-bit FIFO,16-bit FIFO" textline " " endif bitfld.long 0x10 16.--20. " FRSZ ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x10 8.--12. " SYWD ,Sync width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x10 4. " MF ,Specify whether the LSB or the MSB is received first" "LSB,MSB" bitfld.long 0x10 3. " FSE ,Frame sync assertion" "First bit of frame,Before first bit of frame" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x10 2. " ONDEM ,On Demand Mode" "continuously,when the FIFO warning flag is clear" textline " " endif bitfld.long 0x10 1. " FSP ,Frame sync polarity" "Active high,Active low" bitfld.long 0x10 0. " FSD ,Frame sync direction" "External,Internal" line.long 0x14 "I2S1_RCR5,SAI Receive Configuration 5 Register" bitfld.long 0x14 24.--28. " WNW ,Word N width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x14 16.--20. " W0W ,Word 0 width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x14 8.--12. " FBT ,First bit shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hgroup.long 0xa0++0x3 hide.long 0x00 "I2S1_RDR0,SAI Receive Data 0 Register" in hgroup.long 0xa4++0x3 hide.long 0x00 "I2S1_RDR1,SAI Receive Data 1 Register" in rgroup.long 0xc0++0x7 line.long 0x00 "I2S1_RFR0,SAI Receive FIFO 0 Register" bitfld.long 0x00 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x00 15. " RCP ,Receive Channel Pointer" "No effect,Enabled FIFO combine for FIFO reads" textline " " endif bitfld.long 0x00 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "I2S1_RFR1,SAI Receive FIFO 1 Register" bitfld.long 0x04 16.--19. " WFP ,Write FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R") bitfld.long 0x04 15. " RCP ,Receive Channel Pointer" "No effect,Enabled FIFO combine for FIFO reads" textline " " endif bitfld.long 0x04 0.--3. " RFP ,Read FIFO pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long 0xe0++0x3 line.long 0x00 "I2S1_RMR,SAI Receive Mask Register" bitfld.long 0x00 31. " RWM31 ,Receive Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " RWM30 ,Receive Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " RWM29 ,Receive Mask bit 29" "Not masked,Masked" bitfld.long 0x00 28. " RWM28 ,Receive Mask bit 28" "Not masked,Masked" textline " " bitfld.long 0x00 27. " RWM27 ,Receive Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " RWM26 ,Receive Mask bit 26" "Not masked,Masked" bitfld.long 0x00 25. " RWM25 ,Receive Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " RWM24 ,Receive Mask bit 24" "Not masked,Masked" textline " " bitfld.long 0x00 23. " RWM23 ,Receive Mask bit 23" "Not masked,Masked" bitfld.long 0x00 22. " RWM22 ,Receive Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " RWM21 ,Receive Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " RWM20 ,Receive Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RWM19 ,Receive Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " RWM18 ,Receive Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " RWM17 ,Receive Mask bit 17" "Not masked,Masked" bitfld.long 0x00 16. " RWM16 ,Receive Mask bit 16" "Not masked,Masked" textline " " bitfld.long 0x00 15. " RWM15 ,Receive Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " RWM14 ,Receive Mask bit 14" "Not masked,Masked" bitfld.long 0x00 13. " RWM13 ,Receive Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " RWM12 ,Receive Mask bit 12" "Not masked,Masked" textline " " bitfld.long 0x00 11. " RWM11 ,Receive Mask bit 11" "Not masked,Masked" bitfld.long 0x00 10. " RWM10 ,Receive Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " RWM9 ,Receive Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " RWM8 ,Receive Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " RWM7 ,Receive Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " RWM6 ,Receive Mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " RWM5 ,Receive Mask bit 5" "Not masked,Masked" bitfld.long 0x00 4. " RWM4 ,Receive Mask bit 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " RWM3 ,Receive Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " RWM2 ,Receive Mask bit 2" "Not masked,Masked" bitfld.long 0x00 1. " RWM1 ,Receive Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " RWM0 ,Receive Mask bit 0" "Not masked,Masked" textline " " group.long 0x100++0x7 line.long 0x00 "I2S1_MCR,SAI MCLK Control Register" rbitfld.long 0x00 31. " DUF ,Divider Update Flag" "Not updated,Updated" bitfld.long 0x00 30. " MOE ,MCLK Output Enable" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MICS ,MCLK Input Clock Select" "MCLK divider input clock 0,MCLK divider input clock 1,MCLK divider input clock 2,MCLK divider input clock 3" line.long 0x04 "I2S1_MDR,SAI MCLK Divide Register" hexmask.long.byte 0x04 12.--19. 1. " FRACT ,MCLK fraction" hexmask.long.word 0x04 0.--11. 1. " DIVIDE ,MCLK divide" width 0x0B tree.end tree.end tree.end tree.open "Human-Machine Interfaces" tree.open "GPIO (GPIO Controller)" tree "GPIO_A" base ad:0x400FF000 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOA_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 29. 0x04 29. 0x08 29. " PDO[29] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOA_PTOR,Port Toggle Output Register" bitfld.long 0x00 29. " PTTO[29] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 28. " PTTO[28] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 27. " PTTO[27] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 25. " PTTO[25] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 24. " PTTO[24] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOA_PDIR,Port Data Input Register" bitfld.long 0x00 29. " PDI[29] ,Port Data Input" "Low level,High level" bitfld.long 0x00 28. " PDI[28] ,Port Data Input" "Low level,High level" bitfld.long 0x00 27. " PDI[27] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 26. " PDI[26] ,Port Data Input" "Low level,High level" bitfld.long 0x00 25. " PDI[25] ,Port Data Input" "Low level,High level" bitfld.long 0x00 24. " PDI[24] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOA_PDDR,Port Data Direction Register" bitfld.long 0x00 29. " PDD[29] ,Port Data Direction" "Input,Output" bitfld.long 0x00 28. " PDD[28] ,Port Data Direction" "Input,Output" bitfld.long 0x00 27. " PDD[27] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 26. " PDD[26] ,Port Data Direction" "Input,Output" bitfld.long 0x00 25. " PDD[25] ,Port Data Direction" "Input,Output" bitfld.long 0x00 24. " PDD[24] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_B" base ad:0x400FF040 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOB_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOB_PTOR,Port Toggle Output Register" bitfld.long 0x00 23. " PTTO[23] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 22. " PTTO[22] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 21. " PTTO[21] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 20. " PTTO[20] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOB_PDIR,Port Data Input Register" bitfld.long 0x00 23. " PDI[23] ,Port Data Input" "Low level,High level" bitfld.long 0x00 22. " PDI[22] ,Port Data Input" "Low level,High level" bitfld.long 0x00 21. " PDI[21] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 20. " PDI[20] ,Port Data Input" "Low level,High level" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOB_PDDR,Port Data Direction Register" bitfld.long 0x00 23. " PDD[23] ,Port Data Direction" "Input,Output" bitfld.long 0x00 22. " PDD[22] ,Port Data Direction" "Input,Output" bitfld.long 0x00 21. " PDD[21] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 20. " PDD[20] ,Port Data Direction" "Input,Output" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_C" base ad:0x400FF080 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOC_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOC_PTOR,Port Toggle Output Register" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "Not toggled,Toggled" bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOC_PDIR,Port Data Input Register" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOC_PDDR,Port Data Direction Register" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_D" base ad:0x400FF0c0 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOD_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOD_PTOR,Port Toggle Output Register" bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOD_PDIR,Port Data Input Register" bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOD_PDDR,Port Data Direction Register" bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_E" base ad:0x400FF100 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOE_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " PDO[28] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOE_PTOR,Port Toggle Output Register" bitfld.long 0x00 28. " PTTO[28] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 27. " PTTO[27] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 25. " PTTO[25] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 24. " PTTO[24] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOE_PDIR,Port Data Input Register" bitfld.long 0x00 28. " PDI[28] ,Port Data Input" "Low level,High level" bitfld.long 0x00 27. " PDI[27] ,Port Data Input" "Low level,High level" bitfld.long 0x00 26. " PDI[26] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 25. " PDI[25] ,Port Data Input" "Low level,High level" bitfld.long 0x00 24. " PDI[24] ,Port Data Input" "Low level,High level" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOE_PDDR,Port Data Direction Register" bitfld.long 0x00 28. " PDD[28] ,Port Data Direction" "Input,Output" bitfld.long 0x00 27. " PDD[27] ,Port Data Direction" "Input,Output" bitfld.long 0x00 26. " PDD[26] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 25. " PDD[25] ,Port Data Direction" "Input,Output" bitfld.long 0x00 24. " PDD[24] ,Port Data Direction" "Input,Output" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree "GPIO_F" base ad:0x400FF140 width 20. sif (cpu()=="MK70FX512VMJ12")||(cpu()=="MK70FN1M0VMJ12")||(cpu()=="MK70FX512VMJ15")||(cpu()=="MK70FN1M0VMJ15")||(cpu()=="MK70FN1M0VMJ15R")||(cpu()=="MK70FN1M0VMJ12R") group.long 0x00++0x03 line.long 0x00 "GPIOF_PDOR_SET/CLR,Port Data Output Set/Clear Register" setclrfld.long 0x00 27. 0x04 27. 0x08 27. " PDO[27] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " PDO[26] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 25. 0x04 25. 0x08 25. " PDO[25] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 24. 0x04 24. 0x08 24. " PDO[24] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 23. 0x04 23. 0x08 23. " PDO[23] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " PDO[22] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 21. 0x04 21. 0x08 21. " PDO[21] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " PDO[20] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 19. 0x04 19. 0x08 19. " PDO[19] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 18. 0x04 18. 0x08 18. " PDO[18] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " PDO[17] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " PDO[16] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 15. 0x04 15. 0x08 15. " PDO[15] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " PDO[14] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " PDO[13] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 12. 0x04 12. 0x08 12. " PDO[12] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " PDO[11] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " PDO[10] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 9. 0x04 9. 0x08 9. " PDO[9] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " PDO[8] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " PDO[7] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " PDO[6] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " PDO[5] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " PDO[4] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDO[3] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDO[2] ,Port Data Output" "Low level,High level" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDO[1] ,Port Data Output" "Low level,High level" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDO[0] ,Port Data Output" "Low level,High level" wgroup.long 0x0C++0x03 line.long 0x00 "GPIOF_PTOR,Port Toggle Output Register" bitfld.long 0x00 27. " PTTO[27] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 26. " PTTO[26] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 25. " PTTO[25] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 24. " PTTO[24] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 23. " PTTO[23] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 22. " PTTO[22] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 21. " PTTO[21] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 20. " PTTO[20] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 19. " PTTO[19] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 18. " PTTO[18] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 17. " PTTO[17] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 16. " PTTO[16] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 15. " PTTO[15] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 14. " PTTO[14] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 13. " PTTO[13] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 12. " PTTO[12] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 11. " PTTO[11] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 10. " PTTO[10] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 9. " PTTO[9] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 8. " PTTO[8] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 7. " PTTO[7] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 6. " PTTO[6] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 5. " PTTO[5] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 4. " PTTO[4] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 3. " PTTO[3] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 2. " PTTO[2] ,Port Toggle Output" "No effect,Toggle" bitfld.long 0x00 1. " PTTO[1] ,Port Toggle Output" "No effect,Toggle" textline " " bitfld.long 0x00 0. " PTTO[0] ,Port Toggle Output" "No effect,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "GPIOF_PDIR,Port Data Input Register" bitfld.long 0x00 27. " PDI[27] ,Port Data Input" "Low level,High level" bitfld.long 0x00 26. " PDI[26] ,Port Data Input" "Low level,High level" bitfld.long 0x00 25. " PDI[25] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 24. " PDI[24] ,Port Data Input" "Low level,High level" bitfld.long 0x00 23. " PDI[23] ,Port Data Input" "Low level,High level" bitfld.long 0x00 22. " PDI[22] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 21. " PDI[21] ,Port Data Input" "Low level,High level" bitfld.long 0x00 20. " PDI[20] ,Port Data Input" "Low level,High level" bitfld.long 0x00 19. " PDI[19] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 18. " PDI[18] ,Port Data Input" "Low level,High level" bitfld.long 0x00 17. " PDI[17] ,Port Data Input" "Low level,High level" bitfld.long 0x00 16. " PDI[16] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 15. " PDI[15] ,Port Data Input" "Low level,High level" bitfld.long 0x00 14. " PDI[14] ,Port Data Input" "Low level,High level" bitfld.long 0x00 13. " PDI[13] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 12. " PDI[12] ,Port Data Input" "Low level,High level" bitfld.long 0x00 11. " PDI[11] ,Port Data Input" "Low level,High level" bitfld.long 0x00 10. " PDI[10] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 9. " PDI[9] ,Port Data Input" "Low level,High level" bitfld.long 0x00 8. " PDI[8] ,Port Data Input" "Low level,High level" bitfld.long 0x00 7. " PDI[7] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 6. " PDI[6] ,Port Data Input" "Low level,High level" bitfld.long 0x00 5. " PDI[5] ,Port Data Input" "Low level,High level" bitfld.long 0x00 4. " PDI[4] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 3. " PDI[3] ,Port Data Input" "Low level,High level" bitfld.long 0x00 2. " PDI[2] ,Port Data Input" "Low level,High level" bitfld.long 0x00 1. " PDI[1] ,Port Data Input" "Low level,High level" textline " " bitfld.long 0x00 0. " PDI[0] ,Port Data Input" "Low level,High level" group.long 0x14++0x03 line.long 0x00 "GPIOF_PDDR,Port Data Direction Register" bitfld.long 0x00 27. " PDD[27] ,Port Data Direction" "Input,Output" bitfld.long 0x00 26. " PDD[26] ,Port Data Direction" "Input,Output" bitfld.long 0x00 25. " PDD[25] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 24. " PDD[24] ,Port Data Direction" "Input,Output" bitfld.long 0x00 23. " PDD[23] ,Port Data Direction" "Input,Output" bitfld.long 0x00 22. " PDD[22] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 21. " PDD[21] ,Port Data Direction" "Input,Output" bitfld.long 0x00 20. " PDD[20] ,Port Data Direction" "Input,Output" bitfld.long 0x00 19. " PDD[19] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 18. " PDD[18] ,Port Data Direction" "Input,Output" bitfld.long 0x00 17. " PDD[17] ,Port Data Direction" "Input,Output" bitfld.long 0x00 16. " PDD[16] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 15. " PDD[15] ,Port Data Direction" "Input,Output" bitfld.long 0x00 14. " PDD[14] ,Port Data Direction" "Input,Output" bitfld.long 0x00 13. " PDD[13] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 12. " PDD[12] ,Port Data Direction" "Input,Output" bitfld.long 0x00 11. " PDD[11] ,Port Data Direction" "Input,Output" bitfld.long 0x00 10. " PDD[10] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 9. " PDD[9] ,Port Data Direction" "Input,Output" bitfld.long 0x00 8. " PDD[8] ,Port Data Direction" "Input,Output" bitfld.long 0x00 7. " PDD[7] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 6. " PDD[6] ,Port Data Direction" "Input,Output" bitfld.long 0x00 5. " PDD[5] ,Port Data Direction" "Input,Output" bitfld.long 0x00 4. " PDD[4] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 3. " PDD[3] ,Port Data Direction" "Input,Output" bitfld.long 0x00 2. " PDD[2] ,Port Data Direction" "Input,Output" bitfld.long 0x00 1. " PDD[1] ,Port Data Direction" "Input,Output" textline " " bitfld.long 0x00 0. " PDD[0] ,Port Data Direction" "Input,Output" endif width 0x0B tree.end tree.end tree "TSI (Touch sense input)" base ad:0x40045000 width 13. sif cpuis("MK30DX256VLL7*")||cpuis("MK60FN1M0VLQ15")||cpuis("KK26FN2M0CAC18R") if (((per.l(ad:0x40045000)&0x80)==0x80)) group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" rbitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" endif elif cpuis("MK60DN512VMC10R")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40045000)&0x80)==0x80)) group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" rbitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" rbitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" rbitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline rbitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" rbitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" endif elif cpuis("MK70*") if (((per.l(ad:0x40045000)&0x80)==0x80)) group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" rbitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" rbitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline rbitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" rbitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" endif elif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10*")||cpuis("MK10DN512ZVMD10*")||cpuis("MK10DN512ZVMC10*")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10*")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" bitfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline bitfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" bitfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" bitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" endif elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("KK65FN2M0CAC18R") if (((per.l(ad:0x40045000)&0x80)==0x80)) group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" eventfld.long 0x00 31. " OUTRGF ,Out of Range Flag" "Not occurred,Occurred" bitfld.long 0x00 28. " ESOR ,End-of-scan or Out-of-Range Interrupt Selection" "Out-of-range,End-of-scan" newline bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Capacitive sensing(non-noise detection) mode,,,Single threshold noise detection and disabled frequency limitation circuit,,,,Single threshold noise detection and enabled frequency limitation circuit,,,,automatic noise detection mode,,,," newline bitfld.long 0x00 21.--23. " REFCHRG ,Reference oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" bitfld.long 0x00 19.--20. " DVOLT ,the oscillator's voltage rails" "DV = 1.026 V and VP = 1.328 V and Vm = 0.302 V,DV = 0.592 V and VP = 1.111 V and Vm = 0.519 V,DV = 0.342 V and VP = 0.986 V and Vm = 0.644 V,DV = 0.197 V and VP = 0.914 V and Vm = 0.716 V." bitfld.long 0x00 16.--18. " EXTCHRG ,Electrode oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" newline bitfld.long 0x00 13.--15. " PS ,Prescaler of the output of electrode oscillator" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" bitfld.long 0x00 8.--12. " NSCN ,Scan number for each electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" rbitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" newline rbitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" bitfld.long 0x00 5. " STPE ,TSI STOP Enable" "Disabled,Enabled" rbitfld.long 0x00 4. " STM ,Scan Trigger Mode" "Software,Hardware" newline rbitfld.long 0x00 3. " SCNIP ,Scan In Progress Status" "No scan,Scan in progress" eventfld.long 0x00 2. " EOSF ,End of Scan Flag" "No scan,Scan in progress" bitfld.long 0x00 1. " CURSW ,Swapping of current sources of electrode oscillator and reference oscillator" "Not swapped,Swapped" newline bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA Transfer Request Enable Only" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" eventfld.long 0x00 31. " OUTRGF ,Out of Range Flag" "Not occurred,Occurred" bitfld.long 0x00 28. " ESOR ,End-of-scan or Out-of-Range Interrupt Selection" "Out-of-range,End-of-scan" newline bitfld.long 0x00 24.--27. " MODE ,TSI analog modes setup and status bits" "Capacitive sensing(non-noise detection) mode,,,Single threshold noise detection and disabled frequency limitation circuit,,,,Single threshold noise detection and enabled frequency limitation circuit,,,,automatic noise detection mode,,,," newline bitfld.long 0x00 21.--23. " REFCHRG ,Reference oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" bitfld.long 0x00 19.--20. " DVOLT ,the oscillator's voltage rails" "DV = 1.026 V and VP = 1.328 V and Vm = 0.302 V,DV = 0.592 V and VP = 1.111 V and Vm = 0.519 V,DV = 0.342 V and VP = 0.986 V and Vm = 0.644 V,DV = 0.197 V and VP = 0.914 V and Vm = 0.716 V." bitfld.long 0x00 16.--18. " EXTCHRG ,Electrode oscillator charge and discharge current value" "500 nA,1 uA,2 uA,4 uA,8 uA,16 uA,32 uA,64 uA" newline bitfld.long 0x00 13.--15. " PS ,Prescaler of the output of electrode oscillator" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" bitfld.long 0x00 8.--12. " NSCN ,Scan number for each electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" bitfld.long 0x00 5. " STPE ,TSI STOP Enable" "Disabled,Enabled" bitfld.long 0x00 4. " STM ,Scan Trigger Mode" "Software,Hardware" newline rbitfld.long 0x00 3. " SCNIP ,Scan In Progress Status" "No scan,Scan in progress" eventfld.long 0x00 2. " EOSF ,End of Scan Flag" "No scan,Scan in progress" bitfld.long 0x00 1. " CURSW ,Swapping of current sources of electrode oscillator and reference oscillator" "Not swapped,Swapped" newline bitfld.long 0x00 0. " EOSDMEO ,End-of-Scan DMA Transfer Request Enable Only" "Disabled,Enabled" endif else group.long 0x00++0x03 line.long 0x00 "GENCS,General Control And Status Register" bitfld.long 0x00 28. " LPCLKS ,Low power mode clock source selection" "LPOCLK,VLPOSCCLK" bitfld.long 0x00 24.--27. " LPSCNITV ,TSI low power mode scan interval" "1 ms,5 ms,10 ms,15 ms,20 ms,30 ms,40 ms,50 ms,75 ms,100 ms,125 ms,150 ms,200 ms,300 ms,400 ms,500 ms" bitfld.long 0x00 19.--23. " NSCN ,Number of consecutive scans per electrode" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times,17 times,18 times,19 times,20 times,21 times,22 times,23 times,24 times,25 times,26 times,27 times,28 times,29 times,30 times,31 times,32 times" newline bitfld.long 0x00 16.--18. " PS ,Electrode oscillator prescaler" "Div by 1,Div by 2,Div by 4,Div by 8,Div by 16,Div by 32,Div by 64,Div by 128" eventfld.long 0x00 15. " EOSF ,End of scan flag" "Not occurred,Occurred" eventfld.long 0x00 14. " OUTRGF ,Out of range flag" "Not occurred,Occurred" newline eventfld.long 0x00 13. " EXTERF ,External electrode error occurred" "Not occurred,Occurred" eventfld.long 0x00 12. " OVRF ,Overrun error flag" "No overrun,Overrun" rbitfld.long 0x00 9. " SCNIP ,Scan in progress status" "Idle,In progress" newline bitfld.long 0x00 8. " SWTS ,Software trigger start" "No effect,Start" bitfld.long 0x00 7. " TSIEN ,Touch sensing input module enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSIIE ,Touch sensing input interrupt module enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " ERIE ,Error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ESOR ,End-of-Scan or Out-of-Range interrupt select" "Out of range,End of scan" bitfld.long 0x00 1. " STM ,Scan trigger mode" "Software,Periodical" newline bitfld.long 0x00 0. " STPE ,TSI STOP enable while in low power modes" "Not allowed,Allowed" endif sif cpuis("MK*AB10")||cpuis("MK20DN512*AB10R")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*") group.long 0x04++0x03 line.long 0x00 "SCANC,SCAN Control Register" bitfld.long 0x00 27.--31. " REFCHRG ,Ref OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" bitfld.long 0x00 24.--26. " CAPTRM ,Internal capacitance trim value" "0.5 pF,0.6 pF,0.7 pF,0.8 pF,0.9 pF,1.0 pF,1.1 pF,1.2 pF" bitfld.long 0x00 19.--23. " EXTCHRG ,External OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" newline bitfld.long 0x00 16.--18. " DELVOL ,Delta voltage select applied to analog oscillators" "100 mV,150 mV,200 mV,250 mV,300 mV,400 mV,500 mV,600 mV" hexmask.long.byte 0x00 8.--15. 1. " SMOD ,Scan module" sif (!cpuis("MK30DX256VLL7*")) newline bitfld.long 0x00 5. " AMCLKDIV ,Active mode clock divider" "Set to 1,Set to 2048" endif sif cpuis("MK20DN512*AB10R")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DN512ZVLK10")||cpuis("MK30DX256VLL7*") newline bitfld.long 0x00 3.--4. " AMCLKS ,Active mode clock source" "Bus clock,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 0.--2. " AMPSC ,Active mode prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else newline bitfld.long 0x00 3.--4. " AMCLKS ,Active mode clock source" "LPOSCCLK,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 0.--2. " AMPSC ,Active mode prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" endif elif cpuis("MK20*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK10DN512ZVMC10*")||cpuis("MK10DN512ZVLL10")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x04++0x03 line.long 0x00 "SCANC,SCAN Control Register" bitfld.long 0x00 27.--31. " REFCHRG ,Ref OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" bitfld.long 0x00 24.--26. " CAPTRM ,Internal capacitance trim value" "0.5 pF,0.6 pF,0.7 pF,0.8 pF,0.9 pF,1.0 pF,1.1 pF,1.2 pF" bitfld.long 0x00 19.--23. " EXTCHRG ,External OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" newline bitfld.long 0x00 16.--18. " DELVOL ,Delta voltage select applied to analog oscillators" "100 mV,150 mV,200 mV,250 mV,300 mV,400 mV,500 mV,600 mV" hexmask.long.byte 0x00 8.--15. 1. " SMOD ,Scan module" newline bitfld.long 0x00 5. " AMCLKDIV ,Active mode clock divider" "/1,/2048" newline bitfld.long 0x00 3.--4. " AMCLKS ,Active mode clock source" "Bus clock,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 0.--2. " AMPSC ,Active mode prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" else group.long 0x04++0x03 line.long 0x00 "SCANC,SCAN Control Register" bitfld.long 0x00 27.--31. " REFCHRG ,Ref OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" bitfld.long 0x00 24.--26. " CAPTRM ,Internal capacitance trim value" "0.5 pF,0.6 pF,0.7 pF,0.8 pF,0.9 pF,1.0 pF,1.1 pF,1.2 pF" bitfld.long 0x00 19.--23. " EXTCHRG ,External OSC charge current select" "1 uA,2 uA,3 uA,4 uA,5 uA,6 uA,7 uA,8 uA,9 uA,10 uA,11 uA,12 uA,13 uA,14 uA,15 uA,16 uA,17 uA,18 uA,19 uA,20 uA,21 uA,22 uA,23 uA,24 uA,25 uA,26 uA,27 uA,28 uA,29 uA,30 uA,31 uA,32 uA" newline bitfld.long 0x00 16.--18. " DELVOL ,Delta voltage select applied to analog oscillators" "100 mV,150 mV,200 mV,250 mV,300 mV,400 mV,500 mV,600 mV" hexmask.long.byte 0x00 8.--15. 1. " SMOD ,Scan module" newline bitfld.long 0x00 5. " AMCLKDIV ,Active mode clock divider" "/1,/2048" newline bitfld.long 0x00 3.--4. " AMCLKS ,Active mode clock source" "Bus clock,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 0.--2. " AMPSC ,Active mode prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" endif elif cpuis("KK26FN2M0CAC18R") group.long 0x04++0x03 line.long 0x00 "DATA,DATA Register" bitfld.long 0x00 28.--31. " TSICH ,Current measured channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15" bitfld.long 0x00 23. " DMAEN ,DMA Transfer Enabled" "Selected interrupt,Selected DMA transfer request" bitfld.long 0x00 22. " SWTS ,Software Trigger Start" "No effect,Start a scan" newline hexmask.long.word 0x00 0.--15. 1. " TSICNT ,TSI Conversion Counter Value" else group.long 0x04++0x03 line.long 0x00 "SCANC,SCAN Control Register" bitfld.long 0x00 24.--27. " REFCHRG ,Ref OSC charge current select" "2 uA,4 uA,6 uA,8 uA,10 uA,12 uA,14 uA,16 uA,18 uA,20 uA,22 uA,24 uA,26 uA,28 uA,30 uA,32 uA" bitfld.long 0x00 16.--19. " EXTCHRG ,External OSC charge current select" "2 uA,4 uA,6 uA,8 uA,10 uA,12 uA,14 uA,16 uA,18 uA,20 uA,22 uA,24 uA,26 uA,28 uA,30 uA,32 uA" hexmask.long.byte 0x00 8.--15. 1. " SMOD ,Scan module" newline bitfld.long 0x00 3.--4. " AMCLKS ,Active mode clock source" "LPOSCCLK,MCGIRCLK,OSCERCLK,?..." bitfld.long 0x00 0.--2. " AMPSC ,Active mode prescaler" "/1,/2,/4,/8,/16,/32,/64,/128" endif newline sif cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK53DX256ZCMD10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK20*")||cpuis("MK10DN512ZVLK10*")||cpuis("MK10DN512ZVLL10*")||cpuis("MK10DN512ZVLQ10*")||cpuis("MK10DN512ZVMD10*")||cpuis("MK10DN512ZVMC10*")||cpuis("MK10DX256ZVLQ10*")||cpuis("MK10DX256ZVMD10*")||cpuis("MK60DN512ZVLL10")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x40045000)&0x280)==(0x280||0x200||0x80))) rgroup.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin selection" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" newline bitfld.long 0x00 15. " PEN[15] ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Touch sensing input pin enable register 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Touch sensing input pin enable register 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Touch sensing input pin enable register 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Touch sensing input pin enable register 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Touch sensing input pin enable register 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Touch sensing input pin enable register 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Touch sensing input pin enable register 0" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin selection" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" newline bitfld.long 0x00 15. " PEN[15] ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Touch sensing input pin enable register 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Touch sensing input pin enable register 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Touch sensing input pin enable register 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Touch sensing input pin enable register 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Touch sensing input pin enable register 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Touch sensing input pin enable register 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Touch sensing input pin enable register 0" "Disabled,Enabled" endif elif cpuis("MK50DN512ZCLL10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10") if (((per.l(ad:0x40045000)&0x280)==(0x280||0x200||0x80))) rgroup.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" bitfld.long 0x00 15. " PEN15 ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,Touch sensing input pin enable register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " PEN13 ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,Touch sensing input pin enable register 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,Touch sensing input pin enable register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " PEN10 ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " PEN7 ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,Touch sensing input pin enable register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEN4 ,Touch sensing input pin enable register 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,Touch sensing input pin enable register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " PEN1 ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,Touch sensing input pin enable register 0" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" bitfld.long 0x00 15. " PEN15 ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,Touch sensing input pin enable register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " PEN13 ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,Touch sensing input pin enable register 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,Touch sensing input pin enable register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " PEN10 ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " PEN7 ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,Touch sensing input pin enable register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEN4 ,Touch sensing input pin enable register 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,Touch sensing input pin enable register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " PEN1 ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,Touch sensing input pin enable register 0" "Disabled,Enabled" endif elif cpuis("MK60DN512VMC10R")||cpuis("MK60FN1M0VLQ15")||cpuis("KK60FN1M0VLQ15")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMD10") if (((per.l(ad:0x40045000)&0x80)==(0x80))) rgroup.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin selection" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" newline bitfld.long 0x00 15. " PEN[15] ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Touch sensing input pin enable register 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Touch sensing input pin enable register 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Touch sensing input pin enable register 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Touch sensing input pin enable register 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Touch sensing input pin enable register 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Touch sensing input pin enable register 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Touch sensing input pin enable register 0" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin selection" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" newline bitfld.long 0x00 15. " PEN[15] ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,Touch sensing input pin enable register 14" "Disabled,Enabled" bitfld.long 0x00 13. " [13] ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,Touch sensing input pin enable register 12" "Disabled,Enabled" newline bitfld.long 0x00 11. " [11] ,Touch sensing input pin enable register 11" "Disabled,Enabled" bitfld.long 0x00 10. " [10] ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Touch sensing input pin enable register 5" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Touch sensing input pin enable register 4" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Touch sensing input pin enable register 2" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Touch sensing input pin enable register 0" "Disabled,Enabled" endif elif cpuis("MK66FN2M0VLQ18R")||cpuis("MK65FN2M0VMI18R")||cpuis("MK65FN2M0CAC18R")||cpuis("KK65FN2M0CAC18R") group.long 0x08++0x03 line.long 0x00 "TSHD,Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TSI Wakeup Channel High-threshold" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TSI Wakeup Channel Low-threshold" elif cpuis("MK70*") if (((per.l(ad:0x40045000)&0x80)==0x80)) rgroup.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" bitfld.long 0x00 15. " PEN15 ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,Touch sensing input pin enable register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " PEN13 ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,Touch sensing input pin enable register 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,Touch sensing input pin enable register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " PEN10 ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " PEN7 ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,Touch sensing input pin enable register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEN4 ,Touch sensing input pin enable register 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,Touch sensing input pin enable register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " PEN1 ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,Touch sensing input pin enable register 0" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" bitfld.long 0x00 15. " PEN15 ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,Touch sensing input pin enable register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " PEN13 ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,Touch sensing input pin enable register 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,Touch sensing input pin enable register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " PEN10 ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " PEN7 ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,Touch sensing input pin enable register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEN4 ,Touch sensing input pin enable register 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,Touch sensing input pin enable register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " PEN1 ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,Touch sensing input pin enable register 0" "Disabled,Enabled" endif else group.long 0x08++0x03 line.long 0x00 "PEN,Pin Enable Register" bitfld.long 0x00 16.--19. " LPSP ,Low power scan pin" "TSI_IN[0],TSI_IN[1],TSI_IN[2],TSI_IN[3],TSI_IN[4],TSI_IN[5],TSI_IN[6],TSI_IN[7],TSI_IN[8],TSI_IN[9],TSI_IN[10],TSI_IN[11],TSI_IN[12],TSI_IN[13],TSI_IN[14],TSI_IN[15]" bitfld.long 0x00 15. " PEN15 ,Touch sensing input pin enable register 15" "Disabled,Enabled" bitfld.long 0x00 14. " PEN14 ,Touch sensing input pin enable register 14" "Disabled,Enabled" newline bitfld.long 0x00 13. " PEN13 ,Touch sensing input pin enable register 13" "Disabled,Enabled" bitfld.long 0x00 12. " PEN12 ,Touch sensing input pin enable register 12" "Disabled,Enabled" bitfld.long 0x00 11. " PEN11 ,Touch sensing input pin enable register 11" "Disabled,Enabled" newline bitfld.long 0x00 10. " PEN10 ,Touch sensing input pin enable register 10" "Disabled,Enabled" bitfld.long 0x00 9. " PEN9 ,Touch sensing input pin enable register 9" "Disabled,Enabled" bitfld.long 0x00 8. " PEN8 ,Touch sensing input pin enable register 8" "Disabled,Enabled" newline bitfld.long 0x00 7. " PEN7 ,Touch sensing input pin enable register 7" "Disabled,Enabled" bitfld.long 0x00 6. " PEN6 ,Touch sensing input pin enable register 6" "Disabled,Enabled" bitfld.long 0x00 5. " PEN5 ,Touch sensing input pin enable register 5" "Disabled,Enabled" newline bitfld.long 0x00 4. " PEN4 ,Touch sensing input pin enable register 4" "Disabled,Enabled" bitfld.long 0x00 3. " PEN3 ,Touch sensing input pin enable register 3" "Disabled,Enabled" bitfld.long 0x00 2. " PEN2 ,Touch sensing input pin enable register 2" "Disabled,Enabled" newline bitfld.long 0x00 1. " PEN1 ,Touch sensing input pin enable register 1" "Disabled,Enabled" bitfld.long 0x00 0. " PEN0 ,Touch sensing input pin enable register 0" "Disabled,Enabled" endif sif !cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("KK65FN2M0CAC18R") sif cpuis("MK*AB10")||cpuis("MK20DN512*AB10R")||cpuis("MK20DX256ZVLL10*")||cpuis("MK20DN512ZVLL10*")||cpuis("MK20DX128ZVLQ10*")||cpuis("MK20DX128ZVMD10*")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10*")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10*")||cpuis("MK20DX256ZVLK10*")||cpuis("MK20DN512ZVLK10*")||cpuis("MK20DX256ZVMB10*")||cpuis("MK20DN512ZVMB10*")||cpuis("MK20DX256ZVMC10*")||cpuis("MK20DN512ZVMC10*")||cpuis("MK10DN512ZVLL10")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK30D????ZVLQ*")||cpuis("MK30DN512ZVLK10")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK60DN512ZCAB10R")||cpuis("MK10DN512ZVLK10*")||cpuis("KK60DN512ZCAB10R") group.long 0x0C++0x03 line.long 0x00 "STATUS,Status Register" eventfld.long 0x00 31. " ERRORF[15] ,TouchSensing error flag 15" "No error,Error" eventfld.long 0x00 30. " [14] ,TouchSensing error flag 14" "No error,Error" eventfld.long 0x00 29. " [13] ,TouchSensing error flag 13" "No error,Error" eventfld.long 0x00 28. " [12] ,TouchSensing error flag 12" "No error,Error" newline eventfld.long 0x00 27. " [11] ,TouchSensing error flag 11" "No error,Error" eventfld.long 0x00 26. " [10] ,TouchSensing error flag 10" "No error,Error" eventfld.long 0x00 25. " [9] ,TouchSensing error flag 9" "No error,Error" eventfld.long 0x00 24. " [8] ,TouchSensing error flag 8" "No error,Error" newline eventfld.long 0x00 23. " [7] ,TouchSensing error flag 7" "No error,Error" eventfld.long 0x00 22. " [6] ,TouchSensing error flag 6" "No error,Error" eventfld.long 0x00 21. " [5] ,TouchSensing error flag 5" "No error,Error" eventfld.long 0x00 20. " [4] ,TouchSensing error flag 4" "No error,Error" newline eventfld.long 0x00 19. " [3] ,TouchSensing error flag 3" "No error,Error" eventfld.long 0x00 18. " [2] ,TouchSensing error flag 2" "No error,Error" eventfld.long 0x00 17. " [1] ,TouchSensing error flag 1" "No error,Error" eventfld.long 0x00 16. " [0] ,TouchSensing error flag 0" "No error,Error" newline eventfld.long 0x00 15. " ORNGF[15] ,TouchSensing electrode out-of-range flag 15" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,TouchSensing electrode out-of-range flag 14" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,TouchSensing electrode out-of-range flag 13" "No interrupt,Interrupt" eventfld.long 0x00 12. " [12] ,TouchSensing electrode out-of-range flag 12" "No interrupt,Interrupt" newline eventfld.long 0x00 11. " [11] ,TouchSensing electrode out-of-range flag 11" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,TouchSensing electrode out-of-range flag 10" "No interrupt,Interrupt" eventfld.long 0x00 9. " [9] ,TouchSensing electrode out-of-range flag 9" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,TouchSensing electrode out-of-range flag 8" "No interrupt,Interrupt" newline eventfld.long 0x00 7. " [7] ,TouchSensing electrode out-of-range flag 7" "No interrupt,Interrupt" eventfld.long 0x00 6. " [6] ,TouchSensing electrode out-of-range flag 6" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,TouchSensing electrode out-of-range flag 5" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,TouchSensing electrode out-of-range flag 4" "No interrupt,Interrupt" newline eventfld.long 0x00 3. " [3] ,TouchSensing electrode out-of-range flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,TouchSensing electrode out-of-range flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,TouchSensing electrode out-of-range flag 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " [0] ,TouchSensing electrode out-of-range flag 0" "No interrupt,Interrupt" else sif !cpuis("KK26FN2M0CAC18R") rgroup.long 0x0C++0x03 line.long 0x00 "WUCNTR,Wake-Up Channel Counter Register" hexmask.long.word 0x00 0.--15. 1. " WUCNT ,TouchSensing Wake-Up channel 16-bit counter value" endif endif endif newline sif !cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("KK26FN2M0CAC18R")&&!cpuis("KK65FN2M0CAC18R") rgroup.long 0x100++0x03 line.long 0x00 "CNTR1,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 1 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 0 16-bit counter value" rgroup.long 0x104++0x03 line.long 0x00 "CNTR3,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 3 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 2 16-bit counter value" rgroup.long 0x108++0x03 line.long 0x00 "CNTR5,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 5 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 4 16-bit counter value" rgroup.long 0x10C++0x03 line.long 0x00 "CNTR7,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 7 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 6 16-bit counter value" rgroup.long 0x110++0x03 line.long 0x00 "CNTR9,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 9 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 8 16-bit counter value" rgroup.long 0x114++0x03 line.long 0x00 "CNTR11,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 11 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 10 16-bit counter value" rgroup.long 0x118++0x03 line.long 0x00 "CNTR13,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 13 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 12 16-bit counter value" rgroup.long 0x11C++0x03 line.long 0x00 "CNTR15,Counter Register" hexmask.long.word 0x00 16.--31. 1. " CTN ,TouchSensing channel 15 16-bit counter value" hexmask.long.word 0x00 0.--15. 1. " CTN1 ,TouchSensing channel 14 16-bit counter value" endif sif !cpuis("MK66FN2M0VLQ18R")&&!cpuis("MK65FN2M0VMI18R")&&!cpuis("MK65FN2M0CAC18R")&&!cpuis("KK65FN2M0CAC18R") sif cpuis("MK*AB10")||cpuis("MK10DN512ZVLL10")||cpuis("MK10DN512ZVLL10R")||cpuis("MK10DN512ZVMC10")||cpuis("MK10DN512ZVLQ10")||cpuis("MK10DN512ZVMD10")||cpuis("MK10DX256ZVLQ10")||cpuis("MK10DX256ZVLQ10R")||cpuis("MK10DX256ZVMD10")||cpuis("MK30DN512ZVLK10")||cpuis("MK30D????ZVLQ*")||cpuis("MK10DN512ZVLK10*") group.long 0x120++0x03 line.long 0x00 "THRESHOLD0,Channel 0 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x124++0x03 line.long 0x00 "THRESHOLD1,Channel 1 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x128++0x03 line.long 0x00 "THRESHOLD2,Channel 2 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x12C++0x03 line.long 0x00 "THRESHOLD3,Channel 3 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x130++0x03 line.long 0x00 "THRESHOLD4,Channel 4 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x134++0x03 line.long 0x00 "THRESHOLD5,Channel 5 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x138++0x03 line.long 0x00 "THRESHOLD6,Channel 6 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x13C++0x03 line.long 0x00 "THRESHOLD7,Channel 7 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x140++0x03 line.long 0x00 "THRESHOLD8,Channel 8 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x144++0x03 line.long 0x00 "THRESHOLD9,Channel 9 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x148++0x03 line.long 0x00 "THRESHOLD10,Channel 10 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x14C++0x03 line.long 0x00 "THRESHOLD11,Channel 11 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x150++0x03 line.long 0x00 "THRESHOLD12,Channel 12 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x154++0x03 line.long 0x00 "THRESHOLD13,Channel 13 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x158++0x03 line.long 0x00 "THRESHOLD14,Channel 14 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" group.long 0x15C++0x03 line.long 0x00 "THRESHOLD15,Channel 15 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" elif cpuis("MK20DX256ZVLL10*")||cpuis("MK20DN512ZVLL10*")||cpuis("MK20DX128ZVLQ10*")||cpuis("MK20DX128ZVMD10*")||cpuis("MK20DX256ZVLQ10*")||cpuis("MK20DX256ZVMD10*")||cpuis("MK20DN512ZVLQ10*")||cpuis("MK20DN512ZVMD10*")||cpuis("MK20DX256ZVLK10*")||cpuis("MK20DN512ZVLK10*")||cpuis("MK20DX256ZVMB10*")||cpuis("MK20DN512ZVMB10*")||cpuis("MK40DN512ZVLQ10")||cpuis("MK40DN512ZVMD10")||cpuis("MK40DX128ZVLQ10")||cpuis("MK40DX256ZVLQ10")||cpuis("MK40DX256ZVMD10")||cpuis("MK40DN512ZVLL10")||cpuis("MK50DX256ZCLQ10")||cpuis("MK50DN512ZCLQ10")||cpuis("MK50DN512ZCMD10")||cpuis("MK51DX256ZCLL10")||cpuis("MK51DN512ZCLL10")||cpuis("MK51DX256ZCMC10")||cpuis("MK51DN512ZCMC10")||cpuis("MK51DN256ZCLQ10")||cpuis("MK51DN256ZCMD10")||cpuis("MK51DN512ZCLQ10")||cpuis("MK51DN512ZCMD10")||cpuis("MK52DN512ZCLQ10")||cpuis("MK52DN512ZCMD10")||cpuis("MK50DX256ZCLL10")||cpuis("MK50DN512ZCLL10")||cpuis("MK53DN512ZCLQ10")||cpuis("MK53DN512ZCMD10")||cpuis("MK53DX256ZCLQ10")||cpuis("MK53DX256ZCMD10")||cpuis("MK60FN1M0VLQ15")||cpuis("MK60DN512ZCAB10R")||cpuis("KK60DN512ZCAB10R") if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x120++0x03 line.long 0x00 "THRESHOLD0,Channel 0 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x120++0x03 line.long 0x00 "THRESHOLD0,Channel 0 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x124++0x03 line.long 0x00 "THRESHOLD1,Channel 1 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x124++0x03 line.long 0x00 "THRESHOLD1,Channel 1 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x128++0x03 line.long 0x00 "THRESHOLD2,Channel 2 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x128++0x03 line.long 0x00 "THRESHOLD2,Channel 2 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x12C++0x03 line.long 0x00 "THRESHOLD3,Channel 3 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x12C++0x03 line.long 0x00 "THRESHOLD3,Channel 3 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x130++0x03 line.long 0x00 "THRESHOLD4,Channel 4 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x130++0x03 line.long 0x00 "THRESHOLD4,Channel 4 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x134++0x03 line.long 0x00 "THRESHOLD5,Channel 5 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x134++0x03 line.long 0x00 "THRESHOLD5,Channel 5 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x138++0x03 line.long 0x00 "THRESHOLD6,Channel 6 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x138++0x03 line.long 0x00 "THRESHOLD6,Channel 6 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x13C++0x03 line.long 0x00 "THRESHOLD7,Channel 7 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x13C++0x03 line.long 0x00 "THRESHOLD7,Channel 7 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x140++0x03 line.long 0x00 "THRESHOLD8,Channel 8 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x140++0x03 line.long 0x00 "THRESHOLD8,Channel 8 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x144++0x03 line.long 0x00 "THRESHOLD9,Channel 9 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x144++0x03 line.long 0x00 "THRESHOLD9,Channel 9 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x148++0x03 line.long 0x00 "THRESHOLD10,Channel 10 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x148++0x03 line.long 0x00 "THRESHOLD10,Channel 10 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x14C++0x03 line.long 0x00 "THRESHOLD11,Channel 11 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x14C++0x03 line.long 0x00 "THRESHOLD11,Channel 11 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x150++0x03 line.long 0x00 "THRESHOLD12,Channel 12 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x150++0x03 line.long 0x00 "THRESHOLD12,Channel 12 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x154++0x03 line.long 0x00 "THRESHOLD13,Channel 13 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x154++0x03 line.long 0x00 "THRESHOLD13,Channel 13 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x158++0x03 line.long 0x00 "THRESHOLD14,Channel 14 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x158++0x03 line.long 0x00 "THRESHOLD14,Channel 14 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif if (((per.l(ad:0x40045000)&0x200)==0x200)) rgroup.long 0x15C++0x03 line.long 0x00 "THRESHOLD15,Channel 15 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x15C++0x03 line.long 0x00 "THRESHOLD15,Channel 15 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif elif cpuis("KK60FN1M0VLQ15")||cpuis("MK60DN256ZVLQ10")||cpuis("MK60DN512VMC10R")||cpuis("MK60DN512ZVLL10")||cpuis("MK60DN512ZVLQ10")||cpuis("MK60DN512ZVLQ10R")||cpuis("MK60DN512ZVMC10")||cpuis("MK60DN512ZVMD10")||cpuis("MK60DX256ZVLL10")||cpuis("MK60DX256ZVLQ10")||cpuis("MK60DX256ZVMC10")||cpuis("MK60DX256ZVMD10") rgroup.long 0x120++0x03 line.long 0x00 "THRESHOLD0,Channel 0 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x124++0x03 line.long 0x00 "THRESHOLD1,Channel 1 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x128++0x03 line.long 0x00 "THRESHOLD2,Channel 2 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x12C++0x03 line.long 0x00 "THRESHOLD3,Channel 3 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x130++0x03 line.long 0x00 "THRESHOLD4,Channel 4 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x134++0x03 line.long 0x00 "THRESHOLD5,Channel 5 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x138++0x03 line.long 0x00 "THRESHOLD6,Channel 6 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x13C++0x03 line.long 0x00 "THRESHOLD7,Channel 7 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x140++0x03 line.long 0x00 "THRESHOLD8,Channel 8 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x144++0x03 line.long 0x00 "THRESHOLD9,Channel 9 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x148++0x03 line.long 0x00 "THRESHOLD10,Channel 10 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x14C++0x03 line.long 0x00 "THRESHOLD11,Channel 11 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x150++0x03 line.long 0x00 "THRESHOLD12,Channel 12 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x154++0x03 line.long 0x00 "THRESHOLD13,Channel 13 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x158++0x03 line.long 0x00 "THRESHOLD14,Channel 14 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" rgroup.long 0x15C++0x03 line.long 0x00 "THRESHOLD15,Channel 15 Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" else group.long 0x120++0x03 line.long 0x00 "THRESHOLD,Channel Threshold Register" hexmask.long.word 0x00 16.--31. 1. " LTHH ,TouchSensing channel low threshold value" hexmask.long.word 0x00 0.--15. 1. " HTHH ,TouchSensing channel high threshold value" endif endif width 0x0B tree.end tree "LCDC (Liquid Crystal Display Controller)" base ad:0x400B6000 width 14. group.long 0x00++0x0B line.long 0x00 "LCDC_LSSAR,LCDC Screen Start Address Register" hexmask.long 0x00 2.--31. 0x4 " SSA ,Screen start address" line.long 0x04 "LCDC_LSR,LCDC Size Register" hexmask.long.byte 0x04 20.--26. 1. " XMAX ,Screen width divided by 16" hexmask.long.word 0x04 0.--9. 1. " YMAX ,Screen height" line.long 0x08 "LCDC_LVPWR,LCDC Virtual Page Width Register" hexmask.long.word 0x08 0.--10. 1. " VPW ,Virtual page width" textline " " if ((((per.l(ad:0x400B6000+0xc))&0x10000000)==0x10000000)&&(((per.l(ad:0x400B6000+0x18))&0x40000000)==0x40000000)) group.long 0x0c++0x3 line.long 0x00 "LCDC_LCPR,LCDC Cursor Position Register" sif (cpuis("MK70*")) bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,OR(LCD-cursor),XOR(LCD-cursor),AND(LCD-cursor)" textline " " else bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,LCDC color,,AND(background-cursor)" textline " " endif bitfld.long 0x00 28. " OP ,Enable arithmetic operation" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " CXP ,Cursor X position" hexmask.long.word 0x00 0.--9. 1. " CYP ,Cursor Y position" elif ((((per.l(ad:0x400B6000+0xc))&0x10000000)==0x10000000)&&(((per.l(ad:0x400B6000+0x18))&0x40000000)==0x00000000)) group.long 0x0c++0x3 line.long 0x00 "LCDC_LCPR,LCDC Cursor Position Register" sif (!cpuis("MK70*")) bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,1,,0" textline " " endif bitfld.long 0x00 28. " OP ,Enable arithmetic operation" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " CXP ,Cursor X position" hexmask.long.word 0x00 0.--9. 1. " CYP ,Cursor Y position" elif ((((per.l(ad:0x400B6000+0xc))&0x10000000)==0x00000000)&&(((per.l(ad:0x400B6000+0x18))&0x40000000)==0x40000000)) group.long 0x0c++0x3 line.long 0x00 "LCDC_LCPR,LCDC Cursor Position Register" sif (cpuis("MK70*")) bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,LCDC,INV color LCDC,AND(LCD-cursor)" textline " " else bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,OR(background-cursor),XOR(background-cursor),AND(background-cursor)" textline " " endif bitfld.long 0x00 28. " OP ,Enable arithmetic operation" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " CXP ,Cursor X position" hexmask.long.word 0x00 0.--9. 1. " CYP ,Cursor Y position" else group.long 0x0c++0x3 line.long 0x00 "LCDC_LCPR,LCDC Cursor Position Register" sif (cpuis("MK70*")) bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,1,,0" textline " " else bitfld.long 0x00 30.--31. " CC ,Cursor control" "Disabled,OR(background-cursor),XOR(background-cursor),AND(background-cursor)" textline " " endif bitfld.long 0x00 28. " OP ,Enable arithmetic operation" "Disabled,Enabled" hexmask.long.word 0x00 16.--25. 1. " CXP ,Cursor X position" hexmask.long.word 0x00 0.--9. 1. " CYP ,Cursor Y position" endif textline " " group.long 0x10++0x17 line.long 0x00 "LCDC_LCWHB,LCDC Cursor Width Height and Blink Register" bitfld.long 0x00 31. " BK_EN ,Blink enable" "Disabled,Enabled" bitfld.long 0x00 24.--28. " CW ,Cursor width" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--20. " CH ,Cursor height" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--7. 1. " BD ,Blink divisor" line.long 0x04 "LCDC_LCCMR,LCDC Color Cursor Mapping Register" bitfld.long 0x04 12.--17. " CUR_COL_R ,Cursor red field" "No red,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full red" bitfld.long 0x04 6.--11. " CUR_COL_G ,Cursor green field" "No green,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full green" textline " " bitfld.long 0x04 0.--5. " CUR_COL_B ,Cursor blue field" "No blue,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full blue" line.long 0x08 "LCDC_LPCR,LCDC Panel Configuration Register" bitfld.long 0x08 31. " TFT ,LCD Panel display state" "Passive,Active" bitfld.long 0x08 30. " COLOR ,Display color select" "Monochrome,Color" textline " " bitfld.long 0x08 28.--29. " PBSIZ ,Panel bus width" "1-bit,2-bit,4-bit,8-bit" bitfld.long 0x08 25.--27. " BPIX ,Bits per pixel" "1,2,4,8,12,16,18,24" textline " " bitfld.long 0x08 24. " PIXPOL ,Pixel polarity" "Active high,Active low" bitfld.long 0x08 23. " FLMPOL ,First line market polarity" "Active high,Active low" textline " " bitfld.long 0x08 22. " LPPOL ,Line pulse polarity" "Active high,Active low" bitfld.long 0x08 21. " CLKPOL ,LCD shift clock polarity" "Negative,Positive" textline " " bitfld.long 0x08 20. " OEPOL ,Output enable polarity" "Active high,Active low" bitfld.long 0x08 19. " SCLKIDLE ,LSCLK idle enable" "Disabled,Enabled" textline " " bitfld.long 0x08 18. " END_SEL ,Endian select" "Little,Big" bitfld.long 0x08 17. " SWAP_SEL ,Swap select" "24 18 16 12 bpp,8 4 2 1 bpp" textline " " bitfld.long 0x08 16. " REV_VS ,Select the vertical scan direction" "Normal,Reverse" bitfld.long 0x08 15. " ACDSEL ,ACD clock source select" "FLM,LP/HSYN" textline " " hexmask.long.byte 0x08 8.--14. 1. " ACD ,Alternate crystal direction" bitfld.long 0x08 7. " SCLKSEL ,LSCLK mode select" "Disabled when no data,Always enabled" textline " " bitfld.long 0x08 0.--5. " PCD ,Pixel clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" line.long 0x0c "LCDC_LHCR,LCDC Horizontal Configuration Register" bitfld.long 0x0c 26.--31. " H_WIDTH ,Horizontal sync pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0c 8.--15. 1. " H_WAIT_1 ,Number of SCLK periods between the OE and HSYNC" textline " " hexmask.long.byte 0x0c 0.--7. 1. " H_WAIT_2 ,Number of SCLK periods between HSYNC and next line" line.long 0x10 "LCDC_LVCR,LCDC Vertical Configuration Register" bitfld.long 0x10 26.--31. " V_WIDTH ,Vertical sync pulse width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x10 8.--15. 1. " V_WAIT_1 ,Number of SCLK periods between the OE and VSYNC" textline " " hexmask.long.byte 0x10 0.--7. 1. " V_WAIT_2 ,Number of SCLK periods between VSYNC and next line" line.long 0x14 "LCDC_LPOR,LCDC Panning Offset Register" bitfld.long 0x14 0.--4. " POS ,Panning offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x2c++0xb line.long 0x00 "LCDC_LPCCR,LCDC PWM Contrast Control Register" bitfld.long 0x00 15. " LDMSK ,LD mask" "Not masked,Masked" bitfld.long 0x00 9.--10. " SCR ,Source select" "Line pulse,Pixel clock,LCD clock,?..." textline " " bitfld.long 0x00 8. " CC_EN ,Contrast control enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " PW ,Pulse-width" line.long 0x04 "LCDC_LDCR,LCDC DMA Control Register" bitfld.long 0x04 31. " BURST ,Burst length" "Dynamic,Fixed" hexmask.long.byte 0x04 16.--22. 1. " HM ,DMA high mark" textline " " hexmask.long.byte 0x04 0.--6. 1. " TM ,DMA trigger mark" line.long 0x08 "LCDC_LRMCR,LCDC Refresh Mode Control Register" bitfld.long 0x08 0. " SELF_REF ,Self-refresh enable" "Disabled,Enabled" textline " " if (((per.l(ad:0x400B6000+0x38))&0x1)==0x1) group.long 0x38++0x3 line.long 0x00 "LCDC_LICR,LCDC Interrupt Configuration Register" bitfld.long 0x00 4. " GW_INT_CON ,Graphic window interrupt condition" "End of graphic window,Beginning of graphic window" bitfld.long 0x00 2. " INTSYN ,Interrupt source" "Loading first frame of memory,Loading first frame to LCD" bitfld.long 0x00 0. " INTCON ,Interrupt condition" "EOF,BOF" else group.long 0x38++0x3 line.long 0x00 "LCDC_LICR,LCDC Interrupt Configuration Register" bitfld.long 0x00 4. " GW_INT_CON ,Graphic window interrupt condition" "End of graphic window,Beginning of graphic window" bitfld.long 0x00 2. " INTSYN ,Interrupt source" "Loading last frame of memory,Loading last frame to LCD" bitfld.long 0x00 0. " INTCON ,Interrupt condition" "EOF,BOF" endif textline " " group.long 0x3c++0x3 line.long 0x00 "LCDC_LIER,LCDC Interrupt Enable Register" bitfld.long 0x00 7. " GW_UDR_ERR_EN ,Graphic window under run error interrupt enable" "Disabled,Enabled" bitfld.long 0x00 5. " GW_EOF_EN ,Graphic window end of frame interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " GW_BOF_EN ,Graphic window beginning of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " UDR_ERR_EN ,Under run error interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " EOF_EN ,End of frame interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " BOF_EN ,Beginning of frame interrupt enable" "Disabled,Enabled" hgroup.long 0x40++0x3 hide.long 0x00 "LCDC_LISR,LCDC Interrupt Status Register" in group.long 0x50++0x1B line.long 0x00 "LCDC_LGWSAR,LCDC Graphic Window Start Address Register" hexmask.long 0x00 2.--31. 0x4 " GWSA ,Graphic window start address on LCD screen" line.long 0x04 "LCDC_LGWSR,LCDC Graphic Window Size Register" hexmask.long.byte 0x04 20.--26. 1. " GWW ,Graphic window width divided by 16" hexmask.long.word 0x04 0.--9. 1. " GWH ,Graphic window height" line.long 0x08 "LCDC_LGWVPWR,LCDC Graphic Window Virtual Page Width Register" hexmask.long.word 0x08 0.--10. 1. " GWVPW ,Graphic window virtual page width" line.long 0x0C "LCDC_LGWPOR,LCDC Graphic Window Panning Offset Register" bitfld.long 0x0C 0.--4. " GPWO ,Graphic window panning offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "LCDC_LGWPR,LCDC Graphic Window Position Register" hexmask.long.word 0x10 16.--25. 1. " GWXP ,Graphic window X position" hexmask.long.word 0x10 0.--9. 1. " GWYP ,Graphic window Y position" line.long 0x14 "LCDC_LGWCR,LCDC Graphic Window Control Register" hexmask.long.byte 0x14 24.--31. 1. " GWAV ,Graphic window alpha value" bitfld.long 0x14 23. " GWCKE ,Graphic window color keying enable" "Disabled,Enabled" textline " " bitfld.long 0x14 22. " GWE ,Graphic window enable" "Disabled,Enabled" bitfld.long 0x14 21. " GW_RVS ,Select graphic window scan direction" "Normal,Reverse" textline " " bitfld.long 0x14 12.--17. " GWCKR ,Graphic window color keying red component" "No red,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full red" bitfld.long 0x14 6.--11. " GWCKG ,Graphic window color keying green component" "No green,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full green" textline " " bitfld.long 0x14 0.--5. " GWCKB ,Graphic window color keying blue component" "No blue,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,Full blue" line.long 0x18 "LCDC_LGWDCR,LCDC Graphic Window DMA Control Register" bitfld.long 0x18 31. " GWBT ,Graphic window DMA burst type" "Dynamic,Fixed" hexmask.long.byte 0x18 16.--22. 1. " GWHM ,Graphic window DMA high mark" textline " " hexmask.long.byte 0x18 0.--6. 1. " GWTM ,Graphic window DMA low mark" if (((per.l(ad:0x400B6000+0x80)&0x80000000)==0x80000000)) group.long 0x80++0x3 line.long 0x00 "LCDC_LAUSCR,LCDC AUS Mode Control Register" bitfld.long 0x00 31. " AUS_MODE ,AUS mode control" "Normal,AUS" hexmask.long.byte 0x00 16.--23. 1. " AGWCKR ,AUS graphic window color keying red component" textline " " hexmask.long.byte 0x00 8.--15. 1. " AGWCKG ,AUS graphic window color keying green component" hexmask.long.byte 0x00 0.--7. 1. " AGWCKB ,AUS graphic window color keying blue component" else group.long 0x80++0x3 line.long 0x00 "LCDC_LAUSCR,LCDC AUS Mode Control Register" bitfld.long 0x00 31. " AUS_MODE ,AUS mode control" "Normal,AUS" endif if (((per.l(ad:0x400B6000+0x80))&0x80000000)==0x80000000) group.long 0x84++0x3 line.long 0x00 "LCDC_LAUSCCR,LCDC AUS Mode Cursor Control Register" hexmask.long.byte 0x00 16.--23. 1. " ACUR_COL_R ,AUS cursor red field" hexmask.long.byte 0x00 8.--15. 1. " ACUR_COL_G ,AUS cursor green field" textline " " hexmask.long.byte 0x00 0.--7. 1. " ACUR_COL_B ,AUS cursor blue field" else hgroup.long 0x84++0x3 hide.long 0x00 "LCDC_LAUSCCR,LCDC AUS Mode Cursor Control Register" endif width 0x0B tree.end tree.end textline ""